[bsp][lpc55sxx] add support of LPC5528/LPC55S28 (#6667)

* [bsp][lpc55sxx] add support of LPC5528/LPC55S28

1. add .ignore_format
2. add support of LPC55S28
3. fix LPC55S69 keil comiple error
3. refine README

* [bsp][lpc55sxx]

1. remove cmake file
2. formating code using rt-thread formating tools
3. CMSIS folder -> ../

* [bsp][lpc55s69]

 - add IAR support(IAR version: 9.30.1)

bsp/lpc55sxx/Libraries/.ignore_format.yml

+# files format check exclude path, please follow the instructions below to modify;
+
+dir_path:
+- LPC55S6X
+- LPC55S06
+- LPC5502
+- LPC55S28
+- LPC55S36

bsp/lpc55sxx/Libraries/Kconfig

-config SOC_LPC55S6X_SERIES
-    bool
-    select ARCH_ARM_CORTEX_M33
-    select ARCH_ARM_CORTEX_FPU
-    
-config SOC_LPC55S66_SERIES
+config SOC_LPC55S28_SERIES
     bool
     select ARCH_ARM_CORTEX_M33
     select ARCH_ARM_CORTEX_FPU

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/LPC55S28_features.h

+/*
+** ###################################################################
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b220303
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2022 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2018-08-22)
+**         Initial version based on v0.2UM
+**     - rev. 1.1 (2019-05-16)
+**         Initial A1 version based on v1.3UM
+**
+** ###################################################################
+*/
+
+#ifndef _LPC55S28_FEATURES_H_
+#define _LPC55S28_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief CASPER availability on the SoC. */
+#define FSL_FEATURE_SOC_CASPER_COUNT (1)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief CTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (2)
+/* @brief FLASH availability on the SoC. */
+#define FSL_FEATURE_SOC_FLASH_COUNT (1)
+/* @brief FLEXCOMM availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9)
+/* @brief GINT availability on the SoC. */
+#define FSL_FEATURE_SOC_GINT_COUNT (2)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (1)
+/* @brief SECGPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_SECGPIO_COUNT (1)
+/* @brief HASHCRYPT availability on the SoC. */
+#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (8)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (8)
+/* @brief INPUTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief IOCON availability on the SoC. */
+#define FSL_FEATURE_SOC_IOCON_COUNT (1)
+/* @brief LPADC availability on the SoC. */
+#define FSL_FEATURE_SOC_LPADC_COUNT (1)
+/* @brief MRT availability on the SoC. */
+#define FSL_FEATURE_SOC_MRT_COUNT (1)
+/* @brief OSTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
+/* @brief PINT availability on the SoC. */
+#define FSL_FEATURE_SOC_PINT_COUNT (1)
+/* @brief SECPINT availability on the SoC. */
+#define FSL_FEATURE_SOC_SECPINT_COUNT (1)
+/* @brief PMC availability on the SoC. */
+#define FSL_FEATURE_SOC_PMC_COUNT (1)
+/* @brief PUF availability on the SoC. */
+#define FSL_FEATURE_SOC_PUF_COUNT (1)
+/* @brief LPC_RNG1 availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SCT availability on the SoC. */
+#define FSL_FEATURE_SOC_SCT_COUNT (1)
+/* @brief SDIF availability on the SoC. */
+#define FSL_FEATURE_SOC_SDIF_COUNT (1)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (9)
+/* @brief SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
+/* @brief SYSCTL1 availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_USART_COUNT (8)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (1)
+/* @brief USBFSH availability on the SoC. */
+#define FSL_FEATURE_SOC_USBFSH_COUNT (1)
+/* @brief USBHSD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSD_COUNT (1)
+/* @brief USBHSH availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSH_COUNT (1)
+/* @brief USBPHY availability on the SoC. */
+#define FSL_FEATURE_SOC_USBPHY_COUNT (1)
+/* @brief UTICK availability on the SoC. */
+#define FSL_FEATURE_SOC_UTICK_COUNT (1)
+/* @brief WWDT availability on the SoC. */
+#define FSL_FEATURE_SOC_WWDT_COUNT (1)
+
+/* LPADC module features */
+
+/* @brief FIFO availability on the SoC. */
+#define FSL_FEATURE_LPADC_FIFO_COUNT (2)
+/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1)
+/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
+/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
+/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1)
+/* @brief Has conversion resolution select  (bitfield CMDLn[MODE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1)
+/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */
+#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)
+/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
+#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)
+/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1)
+/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1)
+/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1)
+/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
+/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
+/* @brief Has calibration (bitfield CFG[CALOFS]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
+/* @brief Has offset trim (register OFSTRIM). */
+#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
+/* @brief Has Trigger status register. */
+#define FSL_FEATURE_LPADC_HAS_TSTAT (1)
+/* @brief Has power select (bitfield CFG[PWRSEL]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1)
+/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0)
+/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0)
+/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */
+#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0)
+/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */
+#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0)
+/* @brief Conversion averaged bitfiled width. */
+#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3)
+/* @brief Has internal temperature sensor. */
+#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1)
+/* @brief Temperature sensor parameter A (slope). */
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (744.6f)
+/* @brief Temperature sensor parameter B (offset). */
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f)
+/* @brief Temperature sensor parameter Alpha. */
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f)
+/* @brief the buffer size of temperature sensor. */
+#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U)
+
+/* ANALOGCTRL module features */
+
+/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */
+#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1)
+/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */
+#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0)
+/* @brief Has auxiliary bias(register AUX_BIAS). */
+#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1)
+
+/* CASPER module features */
+
+/* @brief Base address of the CASPER dedicated RAM */
+#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000)
+/* @brief SW interleaving of the CASPER dedicated RAM */
+#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1)
+/* @brief CASPER dedicated RAM offset */
+#define FSL_FEATURE_CASPER_RAM_OFFSET (0xE)
+
+/* CTIMER module features */
+
+/* @brief CTIMER has no capture channel. */
+#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0)
+/* @brief CTIMER has no capture 2 interrupt. */
+#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0)
+/* @brief CTIMER capture 3 interrupt. */
+#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1)
+/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */
+#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0)
+/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */
+#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1)
+
+/* DMA module features */
+
+/* @brief Number of channels */
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23)
+/* @brief Align size of DMA descriptor */
+#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
+/* @brief DMA head link descriptor table align size */
+#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
+
+/* FLEXCOMM module features */
+
+/* @brief FLEXCOMM0 USART INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_USART_INDEX  (0)
+/* @brief FLEXCOMM0 SPI INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX  (0)
+/* @brief FLEXCOMM0 I2C INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX  (0)
+/* @brief FLEXCOMM0 I2S INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX  (0)
+/* @brief FLEXCOMM1 USART INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_USART_INDEX  (1)
+/* @brief FLEXCOMM1 SPI INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX  (1)
+/* @brief FLEXCOMM1 I2C INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX  (1)
+/* @brief FLEXCOMM1 I2S INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX  (1)
+/* @brief FLEXCOMM2 USART INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_USART_INDEX  (2)
+/* @brief FLEXCOMM2 SPI INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX  (2)
+/* @brief FLEXCOMM2 I2C INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX  (2)
+/* @brief FLEXCOMM2 I2S INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX  (2)
+/* @brief FLEXCOMM3 USART INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_USART_INDEX  (3)
+/* @brief FLEXCOMM3 SPI INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX  (3)
+/* @brief FLEXCOMM3 I2C INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX  (3)
+/* @brief FLEXCOMM3 I2S INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX  (3)
+/* @brief FLEXCOMM4 USART INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_USART_INDEX  (4)
+/* @brief FLEXCOMM4 SPI INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX  (4)
+/* @brief FLEXCOMM4 I2C INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX  (4)
+/* @brief FLEXCOMM4 I2S INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX  (4)
+/* @brief FLEXCOMM5 USART INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_USART_INDEX  (5)
+/* @brief FLEXCOMM5 SPI INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX  (5)
+/* @brief FLEXCOMM5 I2C INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX  (5)
+/* @brief FLEXCOMM5 I2S INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX  (5)
+/* @brief FLEXCOMM6 USART INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_USART_INDEX  (6)
+/* @brief FLEXCOMM6 SPI INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX  (6)
+/* @brief FLEXCOMM6 I2C INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX  (6)
+/* @brief FLEXCOMM6 I2S INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX  (6)
+/* @brief FLEXCOMM7 USART INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_USART_INDEX  (7)
+/* @brief FLEXCOMM7 SPI INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX  (7)
+/* @brief FLEXCOMM7 I2C INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX  (7)
+/* @brief FLEXCOMM7 I2S INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX  (7)
+/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */
+#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX  (8)
+/* @brief I2S has DMIC interconnection */
+#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0)
+
+/* HASHCRYPT module features */
+
+/* @brief the address of alias offset */
+#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000)
+
+/* I2S module features */
+
+/* @brief I2S support dual channel transfer. */
+#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0)
+/* @brief I2S has DMIC interconnection */
+#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0)
+
+/* IOCON module features */
+
+/* @brief Func bit field width */
+#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
+
+/* MRT module features */
+
+/* @brief number of channels. */
+#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS  (4)
+
+/* PINT module features */
+
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
+
+/* PLU module features */
+
+/* @brief Has WAKEINT_CTRL register. */
+#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1)
+
+/* PMC module features */
+
+/* @brief UTICK does not support PD configure. */
+#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
+/* @brief WDT OSC does not support PD configure. */
+#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
+
+/* POWERLIB module features */
+
+/* @brief Powerlib API is different with other LPC series devices. */
+#define FSL_FEATURE_POWERLIB_EXTEND (1)
+
+/* PUF module features */
+
+/* @brief Number of PUF key slots available on device. */
+#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4)
+/* @brief the shift status value */
+#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1)
+
+/* RTC module features */
+
+/* No feature definitions */
+
+/* SCT module features */
+
+/* @brief Number of events */
+#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)
+/* @brief Number of states */
+#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32)
+/* @brief Number of match capture */
+#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)
+/* @brief Number of outputs */
+#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
+
+/* SDIF module features */
+
+/* @brief FIFO depth, every location is a WORD */
+#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)
+/* @brief Max DMA buffer size */
+#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)
+/* @brief Max source clock in HZ */
+#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)
+/* @brief support 2 cards */
+#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1)
+
+/* SECPINT module features */
+
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2)
+
+/* SYSCON module features */
+
+/* @brief Flash page size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)
+/* @brief Flash sector size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
+/* @brief Flash size in bytes */
+#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288)
+/* @brief Has Power Down mode */
+#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1)
+/* @brief CCM_ANALOG availability on the SoC.  */
+#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
+/* @brief Starter register discontinuous. */
+#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1)
+
+/* SYSCTL1 module features */
+
+/* No feature definitions */
+
+/* USB module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_USB_RAM (0x00004000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USB version */
+#define FSL_FEATURE_USB_VERSION (200)
+/* @brief Number of the endpoint in USB FS */
+#define FSL_FEATURE_USB_EP_NUM (5)
+
+/* USBFSH module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBFSH version */
+#define FSL_FEATURE_USBFSH_VERSION (200)
+
+/* USBHSD module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBHSD version */
+#define FSL_FEATURE_USBHSD_VERSION (300)
+/* @brief Number of the endpoint in USB HS */
+#define FSL_FEATURE_USBHSD_EP_NUM (6)
+
+/* USBHSH module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBHSH version */
+#define FSL_FEATURE_USBHSH_VERSION (300)
+
+/* USBPHY module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBPHY_USB_RAM (0x00004000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBHSD version */
+#define FSL_FEATURE_USBPHY_VERSION (300)
+/* @brief Number of the endpoint in USB HS */
+#define FSL_FEATURE_USBPHY_EP_NUM (6)
+
+/* WWDT module features */
+
+/* @brief Has no RESET register. */
+#define FSL_FEATURE_WWDT_HAS_NO_RESET (1)
+/* @brief WWDT does not support oscillator lock. */
+#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)
+
+#endif /* _LPC55S28_FEATURES_H_ */
+

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55S28_flash.scf

+#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
+/*
+** ###################################################################
+**     Processors:          LPC55S28JBD100_cm33_core0
+**                          LPC55S28JBD64_cm33_core0
+**                          LPC55S28JEV98_cm33_core0
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b200722
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2020 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/* USB BDT size */
+#define usb_bdt_size                   0x0
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+#define  m_interrupts_start            0x00000000
+#define  m_interrupts_size             0x00000200
+
+#define m_text_start                   0x00000200
+#define m_text_size                    0x0007FDFF
+
+#define  m_data_start                  0x20000000
+#define  m_data_size                   0x00030000
+
+#define  m_usb_sram_start              0x40100000
+#define  m_usb_sram_size               0x00004000
+
+
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region
+
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (.isr_vector,+FIRST)
+  }
+
+  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+  }
+  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+
+  RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+    * (*m_usb_bdt)
+  }
+
+  RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+    * (*m_usb_global)
+  }
+}

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55S28_ram.scf

+#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
+/*
+** ###################################################################
+**     Processors:          LPC55S28JBD100_cm33_core0
+**                          LPC55S28JBD64_cm33_core0
+**                          LPC55S28JEV98_cm33_core0
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b200722
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2020 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/* USB BDT size */
+#define usb_bdt_size                   0x0
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+#define  m_interrupts_start            0x04000000
+#define  m_interrupts_size             0x00000200
+
+#define m_text_start                   0x04000200
+#define m_text_size                    0x00007DFF
+
+#define  m_data_start                  0x20000000
+#define  m_data_size                   0x00030000
+
+#define  m_usb_sram_start              0x40100000
+#define  m_usb_sram_size               0x00004000
+
+
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region
+
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (.isr_vector,+FIRST)
+  }
+
+  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+  }
+  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+
+  RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+    * (*m_usb_bdt)
+  }
+
+  RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+    * (*m_usb_global)
+  }
+}

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/arm/LPC55xx.dbgconf

+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <o0> SWO pin
+// <i> The SWO (Serial Wire Output) pin optionally provides data from the ITM
+// <i> for an external debug tool to evaluate.
+//      <0=> PIO0_10
+//      <1=> PIO0_8
+SWO_Pin = 0;
+// 
+
+// <h>Debug Configuration
+//   <o.0>    StopAfterBootloader       <i> Stop after Bootloader
+// </h>
+Dbg_CR = 0x00000001;
+//
+
+
+// <<< end of configuration section >>>
\ No newline at end of file

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_anactrl.c

+/*
+ * Copyright 2018-2021, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "fsl_anactrl.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.anactrl"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get instance number for ANACTRL module.
+ *
+ * @param base ANACTRL peripheral base address
+ */
+static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to ANACTRL bases for each instance. */
+static ANACTRL_Type *const s_anactrlBases[] = ANACTRL_BASE_PTRS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to ANACTRL clocks for each instance. */
+static const clock_ip_name_t s_anactrlClocks[] = ANALOGCTRL_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * brief Get the ANACTRL instance from peripheral base address.
+ *
+ * param base ANACTRL peripheral base address.
+ * return ANACTRL instance.
+ */
+static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_anactrlBases); instance++)
+    {
+        if (s_anactrlBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_anactrlBases));
+
+    return instance;
+}
+
+/*!
+ * brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function.
+ *
+ * param base ANACTRL peripheral base address.
+ */
+void ANACTRL_Init(ANACTRL_Type *base)
+{
+    assert(NULL != base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the clock for ANACTRL instance. */
+    CLOCK_EnableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function.
+ *
+ * param base ANACTRL peripheral base address.
+ */
+void ANACTRL_Deinit(ANACTRL_Type *base)
+{
+    assert(NULL != base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the clock for ANACTRL instance. */
+    CLOCK_DisableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock output
+ * and enable/disable 96MHZ clock output.
+ *
+ * param base ANACTRL peripheral base address.
+ * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure.
+ */
+void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config)
+{
+    assert(NULL != config);
+
+    uint32_t tmp32 = base->FRO192M_CTRL;
+
+    tmp32 &= ~(ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK);
+
+    if (config->enable12MHzClk)
+    {
+        tmp32 |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK;
+    }
+    if (config->enable96MHzClk)
+    {
+        tmp32 |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK;
+    }
+
+    base->FRO192M_CTRL |= tmp32;
+}
+
+/*!
+ * brief Gets the default configuration of FRO192M.
+ * The default values are:
+ * code
+    config->enable12MHzClk = true;
+    config->enable96MHzClk = false;
+    endcode
+ * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure.
+ */
+void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config)
+{
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->enable12MHzClk = true;
+    config->enable96MHzClk = false;
+}
+
+/*!
+ * brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU
+ * system, and so on.
+ *
+ * param base ANACTRL peripheral base address.
+ * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure.
+ */
+void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config)
+{
+    assert(NULL != config);
+
+    uint32_t tmp32 = base->XO32M_CTRL;
+
+    tmp32 &= ~(ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK | ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK);
+
+    /* Set XO32M CTRL. */
+#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \
+      FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD)
+    tmp32 &= ~ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK;
+    if (config->enablePllUsbOutput)
+    {
+        tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK;
+    }
+#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */
+
+    if (config->enableACBufferBypass)
+    {
+        tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK;
+    }
+
+    if (config->enableSysCLkOutput)
+    {
+        tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;
+    }
+    base->XO32M_CTRL = tmp32;
+
+#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \
+     FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD)
+    if (config->enableADCOutput)
+    {
+        base->DUMMY_CTRL |= ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK;
+    }
+    else
+    {
+        base->DUMMY_CTRL &= ~ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK;
+    }
+#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */
+}
+
+/*!
+ * brief Gets the default configuration of XO32M.
+ * The default values are:
+ * code
+    config->enableSysCLkOutput = false;
+    config->enableACBufferBypass = false;
+    endcode
+ * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure.
+ */
+void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config)
+{
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \
+      FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD)
+    config->enablePllUsbOutput = false;
+#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */
+    config->enableSysCLkOutput   = false;
+    config->enableACBufferBypass = false;
+#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \
+     FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD)
+    config->enableADCOutput = true;
+#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */
+}
+
+#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL)
+/*!
+ * brief Measures the frequency of the target clock source.
+ *
+ * This function measures target frequency according to a accurate reference frequency.The formula is:
+ * Ftarget = (CAPVAL * Freference) / ((1<<SCALE)-1)
+ *
+ * note Both tartget and reference clocks are selectable by programming the target clock select FREQMEAS_TARGET register
+ * in INPUTMUX and reference clock select FREQMEAS_REF register in INPUTMUX.
+ *
+ * param base ANACTRL peripheral base address.
+ * param scale Define the power of 2 count that ref counter counts to during measurement, ranges from 2 to 31.
+ * param refClkFreq frequency of the reference clock.
+ *
+ * return frequency of the target clock.
+ */
+uint32_t ANACTRL_MeasureFrequency(ANACTRL_Type *base, uint8_t scale, uint32_t refClkFreq)
+{
+    assert(scale >= 2U);
+
+    uint32_t targetClkFreq = 0U;
+    uint32_t capval        = 0U;
+
+    /* Init a measurement cycle. */
+    base->FREQ_ME_CTRL = ANACTRL_FREQ_ME_CTRL_PROG_MASK + ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(scale);
+    while (ANACTRL_FREQ_ME_CTRL_PROG_MASK == (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_PROG_MASK))
+    {
+    }
+
+    /* Calculate the target clock frequency. */
+    capval        = (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK);
+    targetClkFreq = (capval * refClkFreq) / ((1UL << scale) - 1UL);
+
+    return targetClkFreq;
+}
+#endif /* FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL */

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_anactrl.h

+/*
+ * Copyright 2018-2021, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FSL_ANACTRL_H__
+#define __FSL_ANACTRL_H__
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup anactrl
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief ANACTRL driver version. */
+#define FSL_ANACTRL_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version 2.3.0. */`
+
+/*!
+ * @brief ANACTRL interrupt flags
+ */
+enum _anactrl_interrupt_flags
+{
+#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN)
+    kANACTRL_BodVDDMainFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status
+                                                                               before Interrupt Enable. */
+    kANACTRL_BodVDDMainInterruptFlag =
+        ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_MASK,                     /*!< BOD VDDMAIN Interrupt status
+                                                                                 after Interrupt Enable. */
+    kANACTRL_BodVDDMainPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_MASK, /*!< Current value of BOD VDDMAIN
+                                                                                   power status output. */
+#else
+    kANACTRL_BodVbatFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK, /*!< BOD VBAT Interrupt status before
+                                                                                Interrupt Enable. */
+    kANACTRL_BodVbatInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK, /*!< BOD VBAT Interrupt status
+                                                                                            after Interrupt Enable. */
+    kANACTRL_BodVbatPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK, /*!< Current value of BOD VBAT power
+                                                                                    status output. */
+#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */
+    kANACTRL_BodCoreFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK, /*!< BOD CORE Interrupt status before
+                                                                                Interrupt Enable. */
+    kANACTRL_BodCoreInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK, /*!< BOD CORE Interrupt status
+                                                                                            after Interrupt Enable. */
+    kANACTRL_BodCorePowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK,      /*!< Current value of BOD CORE power
+                                                                                         status output. */
+    kANACTRL_DcdcFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK,              /*!< DCDC Interrupt status before
+                                                                                         Interrupt Enable. */
+    kANACTRL_DcdcInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK, /*!< DCDC Interrupt status after
+                                                                                        Interrupt Enable. */
+    kANACTRL_DcdcPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK,            /*!< Current value of DCDC power
+                                                                                       status output. */
+};
+
+/*!
+ * @brief ANACTRL interrupt control
+ */
+enum _anactrl_interrupt
+{
+#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN)
+    kANACTRL_BodVDDMainInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_MASK, /*!< BOD VDDMAIN
+                                                                                            interrupt control. */
+#else
+    kANACTRL_BodVbatInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK, /*!< BOD VBAT interrupt
+                                                                                            control. */
+#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */
+    kANACTRL_BodCoreInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK, /*!< BOD CORE interrupt
+                                                                                            control. */
+    kANACTRL_DcdcInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK,       /*!< DCDC interrupt control. */
+};
+
+/*!
+ * @brief ANACTRL status flags
+ */
+enum _anactrl_flags
+{
+    kANACTRL_FlashPowerDownFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK,     /*!< Flash power-down status. */
+    kANACTRL_FlashInitErrorFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK, /*!< Flash initialization
+                                                                                          error status. */
+};
+
+/*!
+ * @brief ANACTRL FRO192M and XO32M status flags
+ */
+enum _anactrl_osc_flags
+{
+    kANACTRL_OutputClkValidFlag      = ANACTRL_FRO192M_STATUS_CLK_VALID_MASK,  /*!< Output clock valid signal. */
+    kANACTRL_CCOThresholdVoltageFlag = ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK,  /*!< CCO threshold voltage detector
+                                                                                     output (signal vcco_ok). */
+    kANACTRL_XO32MOutputReadyFlag = ANACTRL_XO32M_STATUS_XO_READY_MASK << 16U, /*!< Indicates XO out
+                                                                                    frequency statibilty. */
+};
+
+/*!
+ * @brief Configuration for FRO192M
+ *
+ * This structure holds the configuration settings for the on-chip high-speed Free Running Oscillator. To initialize
+ * this structure to reasonable defaults, call the ANACTRL_GetDefaultFro192MConfig() function and pass a
+ * pointer to your config structure instance.
+ */
+typedef struct _anactrl_fro192M_config
+{
+    bool enable12MHzClk; /*!< Enable 12MHz clock. */
+    bool enable96MHzClk; /*!< Enable 96MHz clock. */
+} anactrl_fro192M_config_t;
+
+/*!
+ * @brief Configuration for XO32M
+ *
+ * This structure holds the configuration settings for the 32 MHz crystal oscillator. To initialize this
+ * structure to reasonable defaults, call the ANACTRL_GetDefaultXo32MConfig() function and pass a
+ * pointer to your config structure instance.
+ */
+typedef struct _anactrl_xo32M_config
+{
+    bool enableACBufferBypass; /*!< Enable XO AC buffer bypass in pll and top level. */
+#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \
+      FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD)
+    bool enablePllUsbOutput; /*!< Enable XO 32 MHz output to USB HS PLL. */
+#endif                       /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */
+    bool enableSysCLkOutput; /*!< Enable XO 32 MHz output to CPU system, SCT, and CLKOUT */
+#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \
+     FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD)
+    bool enableADCOutput; /*!< Enable High speed crystal oscillator output to ADC. */
+#endif                    /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */
+} anactrl_xo32M_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function.
+ *
+ * @param base ANACTRL peripheral base address.
+ */
+void ANACTRL_Init(ANACTRL_Type *base);
+
+/*!
+ * @brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function.
+ *
+ * @param base ANACTRL peripheral base address.
+ */
+void ANACTRL_Deinit(ANACTRL_Type *base);
+/* @} */
+
+/*!
+ * @name Set oscillators
+ * @{
+ */
+
+/*!
+ * @brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock
+ * output and enable/disable 96MHZ clock output.
+ *
+ * @param base ANACTRL peripheral base address.
+ * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure.
+ */
+void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config);
+
+/*!
+ * @brief Gets the default configuration of FRO192M.
+ * The default values are:
+ * @code
+    config->enable12MHzClk = true;
+    config->enable96MHzClk = false;
+    @endcode
+ * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure.
+ */
+void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config);
+
+/*!
+ * @brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU
+ * system, and so on.
+ *
+ * @param base ANACTRL peripheral base address.
+ * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure.
+ */
+void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config);
+
+/*!
+ * @brief Gets the default configuration of XO32M.
+ * The default values are:
+ * @code
+    config->enableSysCLkOutput = false;
+    config->enableACBufferBypass = false;
+    @endcode
+ * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure.
+ */
+void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config);
+
+/* @} */
+
+#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL)
+/*!
+ * @name Measure Frequency
+ * @{
+ */
+
+/*!
+ * @brief Measures the frequency of the target clock source.
+ *
+ * This function measures target frequency according to a accurate reference frequency.The formula is:
+ * Ftarget = (CAPVAL * Freference) / ((1<<SCALE)-1)
+ *
+ * @note Both tartget and reference clocks are selectable by programming the target clock select FREQMEAS_TARGET
+ * register in INPUTMUX and reference clock select FREQMEAS_REF register in INPUTMUX.
+ *
+ * @param base ANACTRL peripheral base address.
+ * @param scale Define the power of 2 count that ref counter counts to during measurement, ranges from 2 to 31.
+ * @param refClkFreq frequency of the reference clock.
+ *
+ * @return frequency of the target clock.
+ */
+uint32_t ANACTRL_MeasureFrequency(ANACTRL_Type *base, uint8_t scale, uint32_t refClkFreq);
+/* @} */
+#endif /* FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL */
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the ANACTRL interrupts.
+ *
+ * @param base ANACTRL peripheral base address.
+ * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration.
+ */
+static inline void ANACTRL_EnableInterrupts(ANACTRL_Type *base, uint32_t mask)
+{
+    base->BOD_DCDC_INT_CTRL |= (0x15U & mask);
+}
+
+/*!
+ * @brief Disables the ANACTRL interrupts.
+ *
+ * @param base ANACTRL peripheral base address.
+ * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration.
+ */
+static inline void ANACTRL_DisableInterrupts(ANACTRL_Type *base, uint32_t mask)
+{
+    base->BOD_DCDC_INT_CTRL &= ~(0x15U & mask);
+}
+
+/*!
+ * @brief Clears the ANACTRL interrupts.
+ *
+ * @param base ANACTRL peripheral base address.
+ * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration.
+ */
+static inline void ANACTRL_ClearInterrupts(ANACTRL_Type *base, uint32_t mask)
+{
+    base->BOD_DCDC_INT_CTRL |= (uint32_t)(mask << 1UL);
+}
+/* @} */
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets ANACTRL status flags.
+ *
+ * This function gets Analog control status flags. The flags are returned as the logical
+ * OR value of the enumerators @ref _anactrl_flags. To check for a specific status,
+ * compare the return value with enumerators in the @ref _anactrl_flags.
+ * For example, to check whether the flash is in power down mode:
+ * @code
+ *     if (kANACTRL_FlashPowerDownFlag & ANACTRL_ANACTRL_GetStatusFlags(ANACTRL))
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base ANACTRL peripheral base address.
+ * @return ANACTRL status flags which are given in the enumerators in the @ref _anactrl_flags.
+ */
+static inline uint32_t ANACTRL_GetStatusFlags(ANACTRL_Type *base)
+{
+    return base->ANALOG_CTRL_STATUS;
+}
+
+/*!
+ * @brief Gets ANACTRL oscillators status flags.
+ *
+ * This function gets Anactrl oscillators status flags. The flags are returned as the logical
+ * OR value of the enumerators @ref _anactrl_osc_flags. To check for a specific status,
+ * compare the return value with enumerators in the @ref _anactrl_osc_flags.
+ * For example, to check whether the FRO192M clock output is valid:
+ * @code
+ *     if (kANACTRL_OutputClkValidFlag & ANACTRL_ANACTRL_GetOscStatusFlags(ANACTRL))
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base ANACTRL peripheral base address.
+ * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags.
+ */
+static inline uint32_t ANACTRL_GetOscStatusFlags(ANACTRL_Type *base)
+{
+    return (base->FRO192M_STATUS & 0xFFU) | ((base->XO32M_STATUS & 0xFFU) << 16U);
+}
+
+/*!
+ * @brief Gets ANACTRL interrupt status flags.
+ *
+ * This function gets Anactrl interrupt status flags. The flags are returned as the logical
+ * OR value of the enumerators @ref _anactrl_interrupt_flags. To check for a specific status,
+ * compare the return value with enumerators in the @ref _anactrl_interrupt_flags.
+ * For example, to check whether the VBAT voltage level is above the threshold:
+ * @code
+ *     if (kANACTRL_BodVbatPowerFlag & ANACTRL_ANACTRL_GetInterruptStatusFlags(ANACTRL))
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base ANACTRL peripheral base address.
+ * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags.
+ */
+static inline uint32_t ANACTRL_GetInterruptStatusFlags(ANACTRL_Type *base)
+{
+    return base->BOD_DCDC_INT_STATUS & 0x1FFU;
+}
+/* @} */
+
+#if (defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) && (FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG == 1U))
+/*!
+ * @brief Aux_Bias Control Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Enables/disabless 1V reference voltage buffer.
+ *
+ * @param base ANACTRL peripheral base address.
+ * @param enable Used to enable or disable 1V reference voltage buffer.
+ */
+static inline void ANACTRL_EnableVref1V(ANACTRL_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->AUX_BIAS |= ANACTRL_AUX_BIAS_VREF1VENABLE_MASK;
+    }
+    else
+    {
+        base->AUX_BIAS &= ~ANACTRL_AUX_BIAS_VREF1VENABLE_MASK;
+    }
+}
+
+/* @} */
+#endif /* defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* @}*/
+
+#endif /* __FSL_ANACTRL_H__ */

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_casper.h

+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_CASPER_H_
+#define _FSL_CASPER_H_
+
+#include "fsl_common.h"
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*!
+ * @addtogroup casper_driver
+ * @{
+ */
+/*! @name Driver version */
+/*@{*/
+/*! @brief CASPER driver version. Version 2.2.3.
+ *
+ * Current version: 2.2.3
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - Initial version
+ * - Version 2.0.1
+ *   - Bug fix KPSDK-24531 double_scalar_multiplication() result may be all zeroes for some specific input
+ * - Version 2.0.2
+ *   - Bug fix KPSDK-25015 CASPER_MEMCPY hard-fault on LPC55xx when both source and destination buffers are outside of
+ * CASPER_RAM
+ * - Version 2.0.3
+ *   - Bug fix KPSDK-28107 RSUB, FILL and ZERO operations not implemented in enum _casper_operation.
+ * - Version 2.0.4
+ *   - For GCC compiler, enforce O1 optimize level, specifically to remove strict-aliasing option.
+ *     This driver is very specific and requires -fno-strict-aliasing.
+ * - Version 2.0.5
+ *   - Fix sign-compare warning.
+ * - Version 2.0.6
+ *   - Fix IAR Pa082 warning.
+ * - Version 2.0.7
+ *   - Fix MISRA-C 2012 issue.
+ * - Version 2.0.8
+ *   - Add feature macro for CASPER_RAM_OFFSET.
+ * - Version 2.0.9
+ *   - Remove unused function Jac_oncurve().
+ *   - Fix ECC384 build.
+ * - Version 2.0.10
+ *   - Fix MISRA-C 2012 issue.
+ * - Version 2.1.0
+ *   - Add ECC NIST P-521 elliptic curve.
+ * - Version 2.2.0
+ *   - Rework driver to support multiple curves at once.
+ * - Version 2.2.1
+ *   - Fix MISRA-C 2012 issue.
+ * - Version 2.2.2
+ *   - Enable hardware interleaving to RAMX0 and RAMX1 for CASPER by feature macro FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE
+ * - Version 2.2.3
+ *   - Added macro into CASPER_Init and CASPER_Deinit to support devices without clock and reset control.
+ */
+#define FSL_CASPER_DRIVER_VERSION (MAKE_VERSION(2, 2, 3))
+/*@}*/
+
+/*! @brief CASPER operation
+ *
+ */
+typedef enum _casper_operation
+{
+    kCASPER_OpMul6464NoSum = 0x01, /*! Walking 1 or more of J loop, doing r=a*b using 64x64=128*/
+    kCASPER_OpMul6464Sum =
+        0x02, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but assume inner j loop*/
+    kCASPER_OpMul6464FullSum =
+        0x03, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but sum all of w. */
+    kCASPER_OpMul6464Reduce =
+        0x04,               /*! Walking 1 or more of J loop, doing c,r[-1]=r+a*b using 64x64=128, but skip 1st write*/
+    kCASPER_OpAdd64 = 0x08, /*! Walking add with off_AB, and in/out off_RES doing c,r=r+a+c using 64+64=65*/
+    kCASPER_OpSub64 = 0x09, /*! Walking subtract with off_AB, and in/out off_RES doing r=r-a using 64-64=64, with last
+                               borrow implicit if any*/
+    kCASPER_OpDouble64 = 0x0A, /*! Walking add to self with off_RES doing c,r=r+r+c using 64+64=65*/
+    kCASPER_OpXor64    = 0x0B, /*! Walking XOR with off_AB, and in/out off_RES doing r=r^a using 64^64=64*/
+    kCASPER_OpRSub64   = 0x0C, /*! Walking subtract with off_AB, and in/out off_RES using r=a-r */
+    kCASPER_OpShiftLeft32 =
+        0x10, /*! Walking shift left doing r1,r=(b*D)|r1, where D is 2^amt and is loaded by app (off_CD not used)*/
+    kCASPER_OpShiftRight32 = 0x11, /*! Walking shift right doing r,r1=(b*D)|r1, where D is 2^(32-amt) and is loaded by
+                                      app (off_CD not used) and off_RES starts at MSW*/
+    kCASPER_OpCopy        = 0x14,  /*! Copy from ABoff to resoff, 64b at a time*/
+    kCASPER_OpRemask      = 0x15,  /*! Copy and mask from ABoff to resoff, 64b at a time*/
+    kCASPER_OpFill        = 0x16,  /*! Fill RESOFF using 64 bits at a time with value in A and B */
+    kCASPER_OpZero        = 0x17,  /*! Fill RESOFF using 64 bits at a time of 0s */
+    kCASPER_OpCompare     = 0x18,  /*! Compare two arrays, running all the way to the end*/
+    kCASPER_OpCompareFast = 0x19,  /*! Compare two arrays, stopping on 1st !=*/
+} casper_operation_t;
+
+/*! @brief Algorithm used for CASPER operation */
+typedef enum _casper_algo_t
+{
+    kCASPER_ECC_P256 = 0x01, /*!< ECC_P256*/
+    kCASPER_ECC_P384 = 0x02, /*!< ECC_P384 */
+    kCASPER_ECC_P521 = 0x03, /*!< ECC_P521 */
+} casper_algo_t;
+
+#define CASPER_CP          1
+#define CASPER_CP_CTRL0    (0x0 >> 2)
+#define CASPER_CP_CTRL1    (0x4 >> 2)
+#define CASPER_CP_LOADER   (0x8 >> 2)
+#define CASPER_CP_STATUS   (0xC >> 2)
+#define CASPER_CP_INTENSET (0x10 >> 2)
+#define CASPER_CP_INTENCLR (0x14 >> 2)
+#define CASPER_CP_INTSTAT  (0x18 >> 2)
+#define CASPER_CP_AREG     (0x20 >> 2)
+#define CASPER_CP_BREG     (0x24 >> 2)
+#define CASPER_CP_CREG     (0x28 >> 2)
+#define CASPER_CP_DREG     (0x2C >> 2)
+#define CASPER_CP_RES0     (0x30 >> 2)
+#define CASPER_CP_RES1     (0x34 >> 2)
+#define CASPER_CP_RES2     (0x38 >> 2)
+#define CASPER_CP_RES3     (0x3C >> 2)
+#define CASPER_CP_MASK     (0x60 >> 2)
+#define CASPER_CP_REMASK   (0x64 >> 2)
+#define CASPER_CP_LOCK     (0x80 >> 2)
+#define CASPER_CP_ID       (0xFFC >> 2)
+/* mcr (cp,  opc1, value, CRn, CRm, opc2) */
+#define CASPER_Wr32b(value, off) __arm_mcr(CASPER_CP, 0, value, ((off >> 4)), (off), 0)
+/* mcrr(coproc, opc1, value, CRm) */
+#define CASPER_Wr64b(value, off) __arm_mcrr(CASPER_CP, 0, value, off)
+/* mrc(coproc, opc1, CRn, CRm, opc2) */
+#define CASPER_Rd32b(off) __arm_mrc(CASPER_CP, 0, ((off >> 4)), (off), 0)
+
+/*  The model for this algo is that it can be implemented for a fixed size RSA key */
+/*  for max speed. If this is made into a variable (to allow varying size), then */
+/*  it will be slower by a bit. */
+/*  The file is compiled with N_bitlen passed in as number of bits of the RSA key */
+/*  #define N_bitlen 2048 */
+#define N_wordlen_max (4096U / 32U)
+
+enum
+{
+    kCASPER_RamOffset_Result   = 0x0u,
+    kCASPER_RamOffset_Base     = (N_wordlen_max + 8u),
+    kCASPER_RamOffset_TempBase = (2u * N_wordlen_max + 16u),
+    kCASPER_RamOffset_Modulus  = (kCASPER_RamOffset_TempBase + N_wordlen_max + 4u),
+    kCASPER_RamOffset_M64      = 1022U,
+};
+
+/*! @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @addtogroup casper_driver
+ * @{
+ */
+
+/*!
+ * @brief Enables clock and disables reset for CASPER peripheral.
+ *
+ * Enable clock and disable reset for CASPER.
+ *
+ * @param base CASPER base address
+ */
+void CASPER_Init(CASPER_Type *base);
+
+/*!
+ * @brief Disables clock for CASPER peripheral.
+ *
+ * Disable clock and enable reset.
+ *
+ * @param base CASPER base address
+ */
+void CASPER_Deinit(CASPER_Type *base);
+
+/*!
+ *@}
+ */ /* end of casper_driver */
+
+/*******************************************************************************
+ * PKHA API
+ ******************************************************************************/
+
+/*!
+ * @addtogroup casper_driver_pkha
+ * @{
+ */
+
+/*!
+ * @brief Performs modular exponentiation - (A^E) mod N.
+ *
+ * This function performs modular exponentiation.
+ *
+ * @param base CASPER base address
+ * @param signature first addend (in little endian format)
+ * @param pubN modulus (in little endian format)
+ * @param wordLen Size of pubN in bytes
+ * @param pubE exponent
+ * @param[out] plaintext Output array to store result of operation (in little endian format)
+ */
+void CASPER_ModExp(CASPER_Type *base,
+                   const uint8_t *signature,
+                   const uint8_t *pubN,
+                   size_t wordLen,
+                   uint32_t pubE,
+                   uint8_t *plaintext);
+
+/*!
+ * @brief Initialize prime modulus mod in Casper memory .
+ *
+ * Set the prime modulus mod in Casper memory and set N_wordlen
+ * according to selected algorithm.
+ *
+ * @param curve elliptic curve algoritm
+ */
+void CASPER_ecc_init(casper_algo_t curve);
+
+/*!
+ * @brief Performs ECC secp256r1 point single scalar multiplication
+ *
+ * This function performs ECC secp256r1 point single scalar multiplication
+ * [resX; resY] = scalar * [X; Y]
+ * Coordinates are affine in normal form, little endian.
+ * Scalars are little endian.
+ * All arrays are little endian byte arrays, uint32_t type is used
+ * only to enforce the 32-bit alignment (0-mod-4 address).
+ *
+ * @param base CASPER base address
+ * @param[out] resX Output X affine coordinate in normal form, little endian.
+ * @param[out] resY Output Y affine coordinate in normal form, little endian.
+ * @param X Input X affine coordinate in normal form, little endian.
+ * @param Y Input Y affine coordinate in normal form, little endian.
+ * @param scalar Input scalar integer, in normal form, little endian.
+ */
+void CASPER_ECC_SECP256R1_Mul(
+    CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]);
+
+/*!
+ * @brief Performs ECC secp256r1 point double scalar multiplication
+ *
+ * This function performs ECC secp256r1 point double scalar multiplication
+ * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2]
+ * Coordinates are affine in normal form, little endian.
+ * Scalars are little endian.
+ * All arrays are little endian byte arrays, uint32_t type is used
+ * only to enforce the 32-bit alignment (0-mod-4 address).
+ *
+ * @param base CASPER base address
+ * @param[out] resX Output X affine coordinate.
+ * @param[out] resY Output Y affine coordinate.
+ * @param X1 Input X1 affine coordinate.
+ * @param Y1 Input Y1 affine coordinate.
+ * @param scalar1 Input scalar1 integer.
+ * @param X2 Input X2 affine coordinate.
+ * @param Y2 Input Y2 affine coordinate.
+ * @param scalar2 Input scalar2 integer.
+ */
+void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base,
+                                 uint32_t resX[8],
+                                 uint32_t resY[8],
+                                 uint32_t X1[8],
+                                 uint32_t Y1[8],
+                                 uint32_t scalar1[8],
+                                 uint32_t X2[8],
+                                 uint32_t Y2[8],
+                                 uint32_t scalar2[8]);
+
+/*!
+ * @brief Performs ECC secp384r1 point single scalar multiplication
+ *
+ * This function performs ECC secp384r1 point single scalar multiplication
+ * [resX; resY] = scalar * [X; Y]
+ * Coordinates are affine in normal form, little endian.
+ * Scalars are little endian.
+ * All arrays are little endian byte arrays, uint32_t type is used
+ * only to enforce the 32-bit alignment (0-mod-4 address).
+ *
+ * @param base CASPER base address
+ * @param[out] resX Output X affine coordinate in normal form, little endian.
+ * @param[out] resY Output Y affine coordinate in normal form, little endian.
+ * @param X Input X affine coordinate in normal form, little endian.
+ * @param Y Input Y affine coordinate in normal form, little endian.
+ * @param scalar Input scalar integer, in normal form, little endian.
+ */
+void CASPER_ECC_SECP384R1_Mul(
+    CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]);
+
+/*!
+ * @brief Performs ECC secp384r1 point double scalar multiplication
+ *
+ * This function performs ECC secp384r1 point double scalar multiplication
+ * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2]
+ * Coordinates are affine in normal form, little endian.
+ * Scalars are little endian.
+ * All arrays are little endian byte arrays, uint32_t type is used
+ * only to enforce the 32-bit alignment (0-mod-4 address).
+ *
+ * @param base CASPER base address
+ * @param[out] resX Output X affine coordinate.
+ * @param[out] resY Output Y affine coordinate.
+ * @param X1 Input X1 affine coordinate.
+ * @param Y1 Input Y1 affine coordinate.
+ * @param scalar1 Input scalar1 integer.
+ * @param X2 Input X2 affine coordinate.
+ * @param Y2 Input Y2 affine coordinate.
+ * @param scalar2 Input scalar2 integer.
+ */
+void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base,
+                                 uint32_t resX[12],
+                                 uint32_t resY[12],
+                                 uint32_t X1[12],
+                                 uint32_t Y1[12],
+                                 uint32_t scalar1[12],
+                                 uint32_t X2[12],
+                                 uint32_t Y2[12],
+                                 uint32_t scalar2[12]);
+
+/*!
+ * @brief Performs ECC secp521r1 point single scalar multiplication
+ *
+ * This function performs ECC secp521r1 point single scalar multiplication
+ * [resX; resY] = scalar * [X; Y]
+ * Coordinates are affine in normal form, little endian.
+ * Scalars are little endian.
+ * All arrays are little endian byte arrays, uint32_t type is used
+ * only to enforce the 32-bit alignment (0-mod-4 address).
+ *
+ * @param base CASPER base address
+ * @param[out] resX Output X affine coordinate in normal form, little endian.
+ * @param[out] resY Output Y affine coordinate in normal form, little endian.
+ * @param X Input X affine coordinate in normal form, little endian.
+ * @param Y Input Y affine coordinate in normal form, little endian.
+ * @param scalar Input scalar integer, in normal form, little endian.
+ */
+void CASPER_ECC_SECP521R1_Mul(
+    CASPER_Type *base, uint32_t resX[18], uint32_t resY[18], uint32_t X[18], uint32_t Y[18], uint32_t scalar[18]);
+
+/*!
+ * @brief Performs ECC secp521r1 point double scalar multiplication
+ *
+ * This function performs ECC secp521r1 point double scalar multiplication
+ * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2]
+ * Coordinates are affine in normal form, little endian.
+ * Scalars are little endian.
+ * All arrays are little endian byte arrays, uint32_t type is used
+ * only to enforce the 32-bit alignment (0-mod-4 address).
+ *
+ * @param base CASPER base address
+ * @param[out] resX Output X affine coordinate.
+ * @param[out] resY Output Y affine coordinate.
+ * @param X1 Input X1 affine coordinate.
+ * @param Y1 Input Y1 affine coordinate.
+ * @param scalar1 Input scalar1 integer.
+ * @param X2 Input X2 affine coordinate.
+ * @param Y2 Input Y2 affine coordinate.
+ * @param scalar2 Input scalar2 integer.
+ */
+void CASPER_ECC_SECP521R1_MulAdd(CASPER_Type *base,
+                                 uint32_t resX[18],
+                                 uint32_t resY[18],
+                                 uint32_t X1[18],
+                                 uint32_t Y1[18],
+                                 uint32_t scalar1[18],
+                                 uint32_t X2[18],
+                                 uint32_t Y2[18],
+                                 uint32_t scalar2[18]);
+
+void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2);
+void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1);
+
+/*!
+ *@}
+ */ /* end of casper_driver_pkha */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_CASPER_H_ */

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_cmp.c

+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_cmp.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.cmp_1"
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief CMP initialization.
+ *
+ * This function enables the CMP module and do necessary settings.
+ *
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_Init(const cmp_config_t *config)
+{
+    assert(NULL != config);
+
+    uint32_t tmpReg = 0U;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the clock. */
+    CLOCK_EnableClock(kCLOCK_Comp);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_CMP_HAS_NO_RESET) && FSL_TEATURE_CMP_HAS_NO_RESET)
+    /* Reset the CMP module. */
+    RESET_PeripheralReset(kCMP_RST_SHIFT_RSTn);
+#endif /* FSL_FEATURE_CMP_HAS_NO_RESET */
+
+    tmpReg = (PMC->COMP & ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_FILTERCGF_CLKDIV_MASK |
+                            PMC_COMP_FILTERCGF_SAMPLEMODE_MASK));
+
+    if (true == config->enableLowPower)
+    {
+        tmpReg |= PMC_COMP_LOWPOWER_MASK;
+    }
+    else
+    {
+        tmpReg &= ~PMC_COMP_LOWPOWER_MASK;
+    }
+
+    if (true == config->enableHysteresis)
+    {
+        tmpReg |= PMC_COMP_HYST_MASK;
+    }
+    else
+    {
+        tmpReg &= ~PMC_COMP_HYST_MASK;
+    }
+
+    tmpReg |= (PMC_COMP_FILTERCGF_CLKDIV(config->filterClockDivider) |
+               PMC_COMP_FILTERCGF_SAMPLEMODE(config->filterSampleMode));
+
+    PMC->COMP = tmpReg;
+}
+
+/*!
+ * @brief CMP deinitialization.
+ *
+ * This function gates the clock for CMP module.
+ */
+void CMP_Deinit(void)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the clock. */
+    CLOCK_DisableClock(kCLOCK_Comp);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * @brief Initializes the CMP user configuration structure.
+ *
+ * This function initializes the user configuration structure to these default values.
+ * @code
+ *   config->enableHysteresis    = true;
+ *   config->enableLowPower      = true;
+ *   config->filterClockDivider  = kCMP_FilterClockDivide1;
+ *   config->filterSampleMode    = kCMP_FilterSampleMode0;
+ * @endcode
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_GetDefaultConfig(cmp_config_t *config)
+{
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->enableHysteresis   = true;
+    config->enableLowPower     = true;
+    config->filterClockDivider = kCMP_FilterClockDivide1;
+    config->filterSampleMode   = kCMP_FilterSampleMode0;
+}
+
+/*!
+ * @brief Configures the VREFINPUT.
+ *
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_SetVREF(const cmp_vref_config_t *config)
+{
+    assert(NULL != config);
+    assert(config->vrefValue < 32U);
+
+    uint32_t tmpReg = PMC->COMP & ~(PMC_COMP_VREF_MASK | PMC_COMP_VREFINPUT_MASK);
+
+    tmpReg |= PMC_COMP_VREFINPUT(config->vrefSource) | PMC_COMP_VREF(config->vrefValue);
+
+    PMC->COMP = tmpReg;
+}

bsp/lpc55sxx/Libraries/LPC55S28/LPC55S28/drivers/fsl_cmp.h

+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FSL_CMP_H_
+#define __FSL_CMP_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup cmp_1
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions.
+ *****************************************************************************/
+/*! @name Driver version */
+/*@{*/
+/*! @brief Driver version 2.2.1. */
+#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 1U))
+/*@}*/
+
+/*! @brief CMP input mux for positive and negative sides. */
+enum _cmp_input_mux
+{
+    kCMP_InputVREF = 0U, /*!< Cmp input from VREF. */
+    kCMP_Input1    = 1U, /*!< Cmp input source 1. */
+    kCMP_Input2    = 2U, /*!< Cmp input source 2. */
+    kCMP_Input3    = 3U, /*!< Cmp input source 3. */
+    kCMP_Input4    = 4U, /*!< Cmp input source 4. */
+    kCMP_Input5    = 5U, /*!< Cmp input source 5. */
+};
+
+/*! @brief CMP interrupt type. */
+enum _cmp_interrupt_type
+{
+    kCMP_EdgeDisable       = 0U, /*!< Disable edge interupt. */
+    kCMP_EdgeRising        = 2U, /*!< Interrupt on falling edge. */
+    kCMP_EdgeFalling       = 4U, /*!< Interrupt on rising edge. */
+    kCMP_EdgeRisingFalling = 6U, /*!< Interrupt on both rising and falling edges. */
+
+    kCMP_LevelDisable = 1U, /*!< Disable level interupt. */
+    kCMP_LevelHigh    = 3U, /*!< Interrupt on high level. */
+    kCMP_LevelLow     = 5U, /*!< Interrupt on low level. */
+};
+
+/*! @brief CMP Voltage Reference source. */
+typedef enum _cmp_vref_source
+{
+    KCMP_VREFSourceVDDA         = 1U, /*!< Select VDDA as VREF. */
+    KCMP_VREFSourceInternalVREF = 0U, /*!< Select internal VREF as VREF. */
+} cmp_vref_source_t;
+
+typedef struct _cmp_vref_config
+{
+    cmp_vref_source_t vrefSource; /*!< Reference voltage source. */
+    uint8_t vrefValue; /*!< Reference voltage step. Available range is 0-31. Per step equals to VREFINPUT/31. */
+} cmp_vref_config_t;
+
+/*! @brief CMP Filter sample mode. */
+typedef enum _cmp_filtercgf_samplemode
+{
+    kCMP_FilterSampleMode0 = 0U, /*!< Bypass mode. Filtering is disabled. */
+    kCMP_FilterSampleMode1 = 1U, /*!< Filter 1 clock period. */
+    kCMP_FilterSampleMode2 = 2U, /*!< Filter 2 clock period. */
+    kCMP_FilterSampleMode3 = 3U  /*!< Filter 3 clock period. */
+} cmp_filtercgf_samplemode_t;
+
+/*! @brief CMP Filter clock divider. */
+typedef enum _cmp_filtercgf_clkdiv
+{
+    kCMP_FilterClockDivide1  = 0U, /*!< Filter clock period duration equals 1 analog comparator clock period. */
+    kCMP_FilterClockDivide2  = 1U, /*!< Filter clock period duration equals 2 analog comparator clock period. */
+    kCMP_FilterClockDivide4  = 2U, /*!< Filter clock period duration equals 4 analog comparator clock period. */
+    kCMP_FilterClockDivide8  = 3U, /*!< Filter clock period duration equals 8 analog comparator clock period. */
+    kCMP_FilterClockDivide16 = 4U, /*!< Filter clock period duration equals 16 analog comparator clock period. */
+    kCMP_FilterClockDivide32 = 5U, /*!< Filter clock period duration equals 32 analog comparator clock period. */
+    kCMP_FilterClockDivide64 = 6U  /*!< Filter clock period duration equals 64 analog comparator clock period. */
+} cmp_filtercgf_clkdiv_t;
+
+/*! @brief CMP configuration structure. */
+typedef struct _cmp_config
+{
+    bool enableHysteresis;                     /*!< Enable hysteresis. */
+    bool enableLowPower;                       /*!< Enable low power mode. */
+    cmp_filtercgf_clkdiv_t filterClockDivider; /* Filter clock divider. Filter clock equals the Analog Comparator clock
+                                                  divided by 2^FILTERCGF_CLKDIV. */
+    cmp_filtercgf_samplemode_t
+        filterSampleMode; /* Filter sample mode. Control the filtering of the Analog Comparator output. */
+} cmp_config_t;
+
+/*************************************************************************************************
+ * API
+ ************************************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief CMP initialization.
+ *
+ * This function enables the CMP module and do necessary settings.
+ *
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_Init(const cmp_config_t *config);
+
+/*!
+ * @brief CMP deinitialization.
+ *
+ * This function gates the clock for CMP module.
+ */
+void CMP_Deinit(void);
+
+/*!
+ * @brief Initializes the CMP user configuration structure.
+ *
+ * This function initializes the user configuration structure to these default values.
+ * @code
+ *   config->enableHysteresis    = true;
+ *   config->enableLowPower      = true;
+ *   config->filterClockDivider  = kCMP_FilterClockDivide1;
+ *   config->filterSampleMode    = kCMP_FilterSampleMode0;
+ * @endcode
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_GetDefaultConfig(cmp_config_t *config);
+
+/* @} */
+
+/*!
+ * @name Compare Interface
+ * @{
+ */
+
+/*
+ * @brief Set the input channels for the comparator.
+ *
+ * @param positiveChannel Positive side input channel number. See "_cmp_input_mux".
+ * @param negativeChannel Negative side input channel number. See "_cmp_input_mux".
+ */
+static inline void CMP_SetInputChannels(uint8_t positiveChannel, uint8_t negativeChannel)
+{
+    PMC->COMP &= ~(PMC_COMP_PMUX_MASK | PMC_COMP_NMUX_MASK);
+    PMC->COMP |= (PMC_COMP_PMUX(positiveChannel) | PMC_COMP_NMUX(negativeChannel));
+}
+
+/*!
+ * @brief Configures the VREFINPUT.
+ *
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_SetVREF(const cmp_vref_config_t *config);
+
+/*!
+ * @brief Get CMP compare output.
+ *
+ * @return The output result. true: voltage on positive side is greater than negative side.
+ *                            false: voltage on positive side is lower than negative side.
+ */
+static inline bool CMP_GetOutput(void)
+{
+    return SYSCON_COMP_INT_STATUS_VAL_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_VAL_MASK);
+}
+
+/* @} */
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief CMP enable interrupt.
+ *
+ * @param type CMP interrupt type. See "_cmp_interrupt_type".
+ */
+static inline void CMP_EnableInterrupt(uint32_t type)
+{
+    SYSCON->COMP_INT_CTRL |= (SYSCON_COMP_INT_CTRL_INT_CTRL(type) | SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK);
+}
+
+/*!
+ * @brief CMP disable interrupt.
+ *
+ */
+static inline void CMP_DisableInterrupt(void)
+{
+    SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK;
+}
+
+/*!
+ * @brief CMP clear interrupt.
+ *
+ */
+static inline void CMP_ClearInterrupt(void)
+{
+    SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK;
+}
+
+/*!
+ * @brief Select which Analog comparator output (filtered or un-filtered) is used for interrupt detection.
+ *
+ * @param enable false: Select Analog Comparator raw output (unfiltered) as input for interrupt detection.
+ *               true: Select Analog Comparator filtered output as input for interrupt detection.
+ *
+ * @note: When CMP is configured as the wakeup source in power down mode, this function must use the raw output as the
+ *        interupt source, that is, call this function and set parameter enable to false.
+ */
+static inline void CMP_EnableFilteredInterruptSource(bool enable)
+{
+    if (enable)
+    {
+        SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK;
+    }
+    else
+    {
+        SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK;
+    }
+}
+/* @} */
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Get CMP interrupt status before interupt enable.
+ *
+ * @return Interrupt status. true: interrupt pending,
+ *                           false: no interrupt pending.
+ */
+static inline bool CMP_GetPreviousInterruptStatus(void)
+{
+    return SYSCON_COMP_INT_STATUS_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_STATUS_MASK);
+}
+
+/*!
+ * @brief Get CMP interrupt status after interupt enable.
+ *
+ * @return Interrupt status. true: interrupt pending,
+ *                           false: no interrupt pending.
+ */
+static inline bool CMP_GetInterruptStatus(void)
+{
+    return SYSCON_COMP_INT_STATUS_INT_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK);
+}
+/* @} */
+
+/*!
+ * @name Filter Interface
+ * @{
+ */
+
+/*!
+ * @brief CMP Filter Sample Config.
+ *
+ * This function allows the users to configure the sampling mode and clock divider of the CMP Filter.
+ *
+ * @param filterSampleMode   CMP Select filter sample mode
+ * @param filterClockDivider CMP Set fileter clock divider
+ */
+static inline void CMP_FilterSampleConfig(cmp_filtercgf_samplemode_t filterSampleMode,
+                                          cmp_filtercgf_clkdiv_t filterClockDivider)
+{
+    uint32_t comp = PMC->COMP;
+
+    comp &= ~(PMC_COMP_FILTERCGF_CLKDIV_MASK | PMC_COMP_FILTERCGF_SAMPLEMODE_MASK);
+    comp |= (((uint32_t)filterClockDivider << PMC_COMP_FILTERCGF_CLKDIV_SHIFT) |
+             ((uint32_t)filterSampleMode << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT));
+
+    PMC->COMP = comp;
+}
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+#endif /* __FSL_CMP_H_ */