riscv64-noop,cte: use machine mode CSR

am/include/arch/riscv64-noop.h

@@ -8,9 +8,9 @@ struct _Context {
     struct _AddressSpace *as;
     uint64_t gpr[32];
   };
-  uint64_t cause;
-  uint64_t status;
-  uint64_t epc;
+  uint64_t mcause;
+  uint64_t mstatus;
+  uint64_t mepc;
 };
 
 #define GPR1 gpr[17] // a7

am/src/riscv64/noop/cte.c

@@ -15,14 +15,14 @@ _Context* __am_irq_handle(_Context *c) {
   _Context *next = c;
   if (user_handler) {
     _Event ev = {0};
-    switch (c->cause) {
+    switch (c->mcause) {
       //case 0: ev.event = _EVENT_IRQ_TIMER; break;
       case 2:
-        if (__am_illegal_instr(c)) c->epc += 4;
+        if (__am_illegal_instr(c)) c->mepc += 4;
         break;
       case 11:
         ev.event = (c->GPR1 == -1) ? _EVENT_YIELD : _EVENT_SYSCALL;
-        c->epc += 4;
+        c->mepc += 4;
         break;
       default: ev.event = _EVENT_ERROR; break;
     }
@@ -53,8 +53,8 @@ int _cte_init(_Context*(*handler)(_Event, _Context*)) {
 _Context *_kcontext(_Area stack, void (*entry)(void *), void *arg) {
   _Context *c = (_Context*)stack.end - 1;
 
-  c->epc = (uintptr_t)entry;
-  c->status = 0x000c0100;
+  c->mepc = (uintptr_t)entry;
+  c->mstatus = 0x000c0100;
   return c;
 }
 

am/src/riscv64/noop/instr.c

@@ -83,7 +83,7 @@ int __am_illegal_instr(_Context *c) {
     };
     uint32_t val;
   } instr;
-  instr.val = *(uint32_t *)(c->epc);
+  instr.val = *(uint32_t *)(c->mepc);
 
   if (instr.opcode == 0x33 && instr.func2 == 1) {
     // M extension