* Now the following four testcases can be covered:
* Dma_master send write to cpu_dma, and hit the l3, so no transaction to real ddr
* Dma_master send write to cpu_dma, and miss the l3, so there will i_soc.mem port write real ddr
* Dma_master send read to cpu_dma, and hit the l3, so no transaction to real ddr
* Dma_master send read to cpu_dma, and miss the l3, so there will i_soc.mem port read read ddr