Makefile

@@ -32,7 +32,6 @@ ABS_WORK_DIR := $(shell pwd)
 RUN_BIN_DIR ?= $(ABS_WORK_DIR)/ready-to-run
 RUN_BIN ?= coremark-2-iteration
 CONSIDER_FSDB ?= 1
-MFC ?= 0
 
 ifdef FLASH
 	RUN_OPTS := +flash=$(RUN_BIN_DIR)/$(RUN_BIN).bin
@@ -62,13 +61,8 @@ endif
 RELEASE_ARGS = --disable-all --remove-assert --fpga-platform
 DEBUG_ARGS   = --enable-difftest
 
-ifeq ($(MFC),1)
-RELEASE_ARGS += -X none -E chirrtl --output-file $(TOP).chirrtl.fir
-DEBUG_ARGS += -X none -E chirrtl --output-file $(SIM_TOP).chirrtl.fir
-else
-RELEASE_ARGS += --emission-options disableRegisterRandomization -E verilog --output-file $(TOP).v
-DEBUG_ARGS += --emission-options disableRegisterRandomization -E verilog --output-file $(SIM_TOP).v
-endif
+RELEASE_ARGS += --emission-options disableRegisterRandomization -E verilog
+DEBUG_ARGS += --emission-options disableRegisterRandomization -E verilog
 
 ifeq ($(RELEASE),1)
 override SIM_ARGS += $(RELEASE_ARGS)
@@ -85,13 +79,7 @@ $(TOP_V): $(SCALA_FILE)
 	mkdir -p $(@D)
 	time -o $(@D)/time.log mill -i XiangShan.runMain $(FPGATOP) -td $(@D) \
 		--config $(CONFIG) --full-stacktrace --num-cores $(NUM_CORES) \
-		$(RELEASE_ARGS)
-ifeq ($(MFC),1)
-	time -a -o $(@D)/time.log firtool --disable-all-randomization --disable-annotation-unknown \
-	--annotation-file=$(BUILD_DIR)/$(TOP).anno.json --format=fir \
-	--lowering-options=noAlwaysComb,disallowExpressionInliningInPorts,explicitBitcast \
-	--verilog --dedup -o $(TOP_V) $(BUILD_DIR)/$(TOP).chirrtl.fir
-endif
+		$(RELEASE_ARGS) --output-file $(TOP)
 	sed -e 's/\(peripheral\|memory\)_0_\(aw\|ar\|w\|r\|b\)_bits_/m_\1_\2_/g' \
 	-e 's/\(dma\)_0_\(aw\|ar\|w\|r\|b\)_bits_/s_\1_\2_/g' $@ > $(BUILD_DIR)/tmp.v
 	sed -e 's/\(peripheral\|memory\)_0_\(aw\|ar\|w\|r\|b\)_/m_\1_\2_/g' \
@@ -108,6 +96,11 @@ endif
 
 verilog: $(TOP_V)
 
+verilog-release:
+	$(MAKE) verilog RELEASE=1
+	# split rtl modules and sim top, copy extra files
+	python3 scripts/parser.py XSTop --config $(CONFIG)
+
 SIM_TOP_V = $(BUILD_DIR)/$(SIM_TOP).v
 $(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
 	mkdir -p $(@D)
@@ -115,17 +108,13 @@ $(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
 	@date -R | tee -a $(@D)/time.log
 	time -o $(@D)/time.log mill -i XiangShan.test.runMain $(SIMTOP) -td $(@D) \
 		--config $(CONFIG) --full-stacktrace --num-cores $(NUM_CORES) \
-		$(SIM_ARGS)
-ifeq ($(MFC),1)
-	time -a -o $(@D)/time.log firtool --disable-all-randomization --disable-annotation-unknown \
-	--annotation-file=$(BUILD_DIR)/$(SIM_TOP).anno.json --format=fir \
-	--lowering-options=noAlwaysComb,disallowExpressionInliningInPorts,explicitBitcast \
-	--verilog --dedup -o $(SIM_TOP_V) $(BUILD_DIR)/$(SIM_TOP).chirrtl.fir
-
-	sed '/\/\/ ----- 8< ----- .*----- 8< -----/,$d' $(SIM_TOP_V) > res.v
-	rm $(SIM_TOP_V)
-	mv res.v $(SIM_TOP_V)
-endif
+		$(SIM_ARGS) --output-file $(SIM_TOP)
+	sed -e 's/\(peripheral\|memory\)_0_\(aw\|ar\|w\|r\|b\)_bits_/m_\1_\2_/g' \
+	-e 's/\(dma\)_0_\(aw\|ar\|w\|r\|b\)_bits_/s_\1_\2_/g' $@ > $(BUILD_DIR)/tmp.v
+	sed -e 's/\(peripheral\|memory\)_0_\(aw\|ar\|w\|r\|b\)_/m_\1_\2_/g' \
+	-e 's/\(dma\)_0_\(aw\|ar\|w\|r\|b\)_\(ready\|valid\)/s_\1_\2_\3/g' $(BUILD_DIR)/tmp.v > $(BUILD_DIR)/tmp1.v
+	rm $@ $(BUILD_DIR)/tmp.v
+	mv $(BUILD_DIR)/tmp1.v $@
 	@git log -n 1 >> .__head__
 	@git diff >> .__diff__
 	@sed -i 's/^/\/\// ' .__head__
@@ -136,13 +125,24 @@ endif
 	sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V)
 
 FILELIST := $(ABS_WORK_DIR)/build/cpu_flist.f
+
 sim-verilog: $(SIM_TOP_V)
 	find $(ABS_WORK_DIR)/build -name "*.v" > $(FILELIST)
 
+sim-verilog-release:
+	$(MAKE) $(SIM_TOP_V) RELEASE=1
+	# split rtl modules and sim top, copy extra files
+	python3 scripts/parser.py SimTop --config $(CONFIG) \
+		--ignore XSTop --include difftest          \
+        --no-sram-conf --no-sram-xlsx
+
 clean:
 	$(MAKE) -C ./difftest clean
 	rm -rf ./build
 
+clean-release:
+	rm -rf ./*-Release-*
+
 init:
 	git submodule update --init
 	cd rocket-chip && git submodule update --init api-config-chipsalliance hardfloat

huancun @ 75b7d144

-Subproject commit ee5b6c0426a675b55389d71ba192cc562ed260df
+Subproject commit 75b7d144ddb54cfcfdda7186d86e9da6c71b882c

src/main/scala/top/Configs.scala

@@ -281,7 +281,10 @@ class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1
           )
         },
         enablePerf = true,
-        ctrl = None,
+        ctrl = Some(CacheCtrl(
+          address = 0x39000000,
+          numCores = tiles.size
+        )),
         sramClkDivBy2 = true,
         sramDepthDiv = 4,
         tagECC = None,

src/main/scala/top/Top.scala

@@ -163,6 +163,10 @@ class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
     dontTouch(io)
     dontTouch(peripheral)
     dontTouch(memory)
+    dontTouch(scan_mode)
+    dontTouch(dft_lgc_rst_n)
+    dontTouch(dft_mode)
+    dontTouch(dfx_reset)
     misc.module.ext_intrs := io.extIntrs
 
     for ((core, i) <- core_with_l2.zipWithIndex) {
@@ -222,6 +226,7 @@ class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
       None
     }
     if(dft.isDefined){
+      dontTouch(dft.get)
       if(mbistBroadCastToTile.isDefined){
         mbistBroadCastToTile.get := dft.get
       }

src/main/scala/xiangshan/XSCore.scala

@@ -24,8 +24,8 @@ import freechips.rocketchip.diplomacy.{BundleBridgeSource, LazyModule, LazyModul
 import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple}
 import freechips.rocketchip.tile.HasFPUParameters
 import freechips.rocketchip.tilelink.TLBuffer
-import huancun.mbist.MBISTPipeline
-import huancun.utils.{ModuleNode, ResetGen, ResetGenNode, SRAMTemplate, DFTResetSignals}
+import huancun.mbist.{MBISTInterface, MBISTPipeline}
+import huancun.utils.{DFTResetSignals, ModuleNode, ResetGen, ResetGenNode, SRAMTemplate}
 import system.HasSoCParameter
 import utils._
 import xiangshan.backend._
@@ -434,10 +434,26 @@ class XSCoreImp(outer: XSCoreBase) extends LazyModuleImp(outer)
   } else {
     None
   }
-  val mbist = if(coreParams.hasMbist && coreParams.hasShareBus) Some(IO(mbistPipeline.get.io.mbist.get.cloneType)) else None
-  if(coreParams.hasMbist && coreParams.hasShareBus){
-    mbist.get <> mbistPipeline.get.io.mbist.get
+
+  val coreMbistIntf = if (coreParams.hasMbist && coreParams.hasShareBus) {
+    val params = mbistPipeline.get.bd.params
+    val node = mbistPipeline.get.node
+    val intf = Some(Module(new MBISTInterface(
+      params = Seq(params),
+      ids = Seq(node.children.flatMap(_.array_id)),
+      name = s"MBIST_intf_core",
+      pipelineNum = 1
+    )))
+    intf.get.toPipeline.head <> mbistPipeline.get.io.mbist.get
+    mbistPipeline.get.genCSV(intf.get.info, "MBIST_Core")
+    intf.get.mbist := DontCare
+    dontTouch(intf.get.mbist)
+    //TODO: add mbist controller connections here
+    intf
+  } else {
+    None
   }
+
   val sigFromSrams = if(coreParams.hasMbist) Some(SRAMTemplate.genBroadCastBundleTop()) else None
   val dft = if(coreParams.hasMbist) Some(IO(sigFromSrams.get.cloneType)) else None
   if(coreParams.hasMbist) {

src/main/scala/xiangshan/XSTile.scala

@@ -180,25 +180,6 @@ class XSTileImp(outer: XSTile) extends LazyHardenModuleImp(outer) {
     outer.misc.module.beu_errors.l2 <> 0.U.asTypeOf(outer.misc.module.beu_errors.l2)
   }
 
-  val coreMbistIntf = if(outer.coreParams.hasMbist && outer.coreParams.hasShareBus){
-    val params = outer.core.module.mbistPipeline.get.bd.params
-    val node = outer.core.module.mbistPipeline.get.node
-    val intf = Some(Module(new MBISTInterface(
-      params = Seq(params),
-      ids = Seq(node.children.flatMap(_.array_id)),
-      name = s"MBIST_intf_core",
-      pipelineNum = 1
-    )))
-    intf.get.toPipeline.head <> outer.core.module.mbist.get
-    outer.core.module.mbistPipeline.get.genCSV(intf.get.info, "MBIST_Core")
-    intf.get.mbist := DontCare
-    dontTouch(intf.get.mbist)
-    //TODO: add mbist controller connections here
-    intf
-  } else {
-    None
-  }
-
   val l2MbistIntf = if(outer.l2cache.isDefined){
     if(p(XSCoreParamsKey).L2CacheParamsOpt.get.hasMbist && p(XSCoreParamsKey).L2CacheParamsOpt.get.hasShareBus){
       val params = outer.l2cache.get.module.l2TopPipeLine.get.bd.params