# Conflicts:
#	.gitmodules
#	build.sc
#	src/main/scala/top/Configs.scala
#	src/main/scala/xiangshan/Bundle.scala
#	src/main/scala/xiangshan/Parameters.scala
#	src/main/scala/xiangshan/XSCore.scala
#	src/main/scala/xiangshan/backend/CtrlBlock.scala
#	src/main/scala/xiangshan/backend/MemBlock.scala
#	src/main/scala/xiangshan/backend/Scheduler.scala
#	src/main/scala/xiangshan/backend/issue/ReservationStation.scala
#	src/main/scala/xiangshan/backend/issue/StatusArray.scala
#	src/main/scala/xiangshan/backend/rob/Rob.scala
#	src/main/scala/xiangshan/mem/MemCommon.scala
#	src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
#	src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
#	src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
#	src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
#	src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala

* icache: Acquire -> Get to L2

* gitmodules: add coupledL2 as submodule

* cpl2: merge coupledL2 into master

* Changes includes:
*   coupledL2 integration
*   modify user&echo fields in i$/d$/ptw
*   set d$ never always-releasedata
*   remove hw perfcnt connection for L2

* bump utility

* icache: remove unused releaseUnit

* config: minimalconfig includes l2

* Otherwise, dirty bits maintainence may be broken
* Known issue: L2 should have more than 1 bank to avoid compiling problem

* bump Utility

* bump coupledL2: fix bugs in dual-core

* bump coupledL2

* icache: set icache as non-coherent node

* bump coupledL2: fix dirty problem in L2 ProbeAckData

---------
Co-authored-by: Nguohongyu <20373696@buaa.edu.cn>
Co-authored-by: NXiChen <chenxi171@mails.ucas.ac.cn>

* script: enable chiseldb by default on running emu by xiangshan.py

* script: move db file to wave_home if emu failed

BPU: online history checker

* fix uncache buffer writeback fsm

* fix uncache buffer writeback fsm

* fix uncache buffer writeback control

---------
Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>

* Set uopNum at rob's enq instead of using enqCnt to avoid committing before all uop enq.
* There are many uops mapped to the same robIdx. When some of the uops enter rob, while others blocked at rename stage for the lack of free regfiles, committing before all uop enq would happen.
* Distinguish std wb status as before