- 21 6月, 2023 1 次提交
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由 lixin 提交于
* all miss entries will have chance to wakeup load replay queue
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- 19 6月, 2023 1 次提交
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由 Haoyuan Feng 提交于
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- 15 6月, 2023 1 次提交
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由 sfencevma 提交于
Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>
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- 13 6月, 2023 2 次提交
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由 sfencevma 提交于
Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>
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由 sfencevma 提交于
* Replay cycles increased from 2 to 3 cycles * Simplified replay selection logic
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- 12 6月, 2023 7 次提交
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由 Maxpicca 提交于
* dcache: fix the timing coupling of `ecc_resp` and `s1_tag_match` * dcache: fix bug in cacheOp's ecc * dcache: fix bug of compilation
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由 Maxpicca 提交于
* dcache: fix the timing coupling of `ecc_resp` and `s1_tag_match` * dcache: fix bug in cacheOp's ecc * dcache: fix bug of compilation
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由 sfencevma 提交于
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由 happy-lx 提交于
* dcache: split missqueue enq logic Now, the miss request entering the missqueue is split into two cycles, the first cycle determines whether it can enq or merge, and the second cycle does the actual data update. In order to send acquire request to L2 as quickly as possible, the pipeline register also sends acquire when the situation allows. If it sends successfully, the s_acquire does not need to be updated to false when updating MSHR * missqueue: adjust priority Make acquire from pipereg have highest priority * dcache: add some pf counter * missqueue: fix acquire source in pipeline reg
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由 Haoyuan Feng 提交于
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由 sfencevma 提交于
* In latest design, delay release check will not happen.
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由 xinyao zheng 提交于
* CancelCount to EngPtr violates the timing requirement * Adding one cycle by regnext for better timing.
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- 09 6月, 2023 1 次提交
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由 Maxpicca 提交于
* Divide dcache sram into N parts above 8 banks in a cache line. * N is configurable, and when it is 1, it is the original config. * Fine-grained read-write bank conflicts base on dcache divide.
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- 06 6月, 2023 1 次提交
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由 wakafa 提交于
* config: disable chiseldb by default to minimize db size * note that tllog is still enabled when alwaysBasicDB is set * bump huancun & utility
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- 02 6月, 2023 2 次提交
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由 Tang Haojin 提交于
* topdown: add defines of topdown counters enum * redirect: add redirect type for perf * top-down: add stallReason IOs frontend -> ctrlBlock -> decode -> rename -> dispatch * top-down: add dummy connections * top-down: update TopdownCounters * top-down: imp backend analysis and counter dump * top-down: add HartId in `addSource` * top-down: broadcast lqIdx of ROB head * top-down: frontend signal done * top-down: add memblock topdown interface * Bump HuanCun: add TopDownMonitor * top-down: receive and handle reasons in dispatch * top-down: remove previous top-down code * TopDown: add MemReqSource enum * TopDown: extend mshr_latency range * TopDown: add basic Req Source TODO: distinguish prefetch * dcache: distinguish L1DataPrefetch and CPUData * top-down: comment out debugging perf counters in ibuffer * TopDown: add path to pass MemReqSource to HuanCun * TopDown: use simpler logic to count reqSource and update Probe count * frontend: update topdown counters * Update HuanCun Topdown for MemReqSource * top-down: fix load stalls * top-down: Change the priority of different stall reasons * top-down: breakdown OtherCoreStall * sbuffer: fix eviction * when valid count reaches StoreBufferSize, do eviction * sbuffer: fix replaceIdx * If the way selected by the replacement algorithm cannot be written into dcache, its result is not used. * dcache, ldu: fix vaddr in missqueue This commit prevents the high bits of the virtual address from being truncated * fix-ldst_pri-230506 * mainpipe: fix loadsAreComing * top-down: disable dedup * top-down: remove old top-down config * top-down: split lq addr from ls_debug * top-down: purge previous top-down code * top-down: add debug_vaddr in LoadQueueReplay * add source rob_head_other_repay * remove load_l1_cache_stall_with/wihtou_bank_conflict * dcache: split CPUData & refill latency * split CPUData to CPUStoreData & CPULoadData & CPUAtomicData * monitor refill latency for all type of req * dcache: fix perfcounter in mq * io.req.bits.cancel should be applied when counting req.fire * TopDown: add TopDown for CPL2 in XiangShan * top-down: add hartid params to L2Cache * top-down: fix dispatch queue bound * top-down: no DqStall when robFull * topdown: buspmu support latency statistic (#2106) * perf: add buspmu between L2 and L3, support name argument * bump difftest * perf: busmonitor supports latency stat * config: fix cpl2 compatible problem * bump utility * bump coupledL2 * bump huancun * misc: adapt to utility key&field * config: fix key&field source, remove deprecated argument * buspmu: remove debug print * bump coupledl2&huancun * top-down: fix sq full condition * top-down: classify "lq full" load bound * top-down: bump submodules * bump coupledL2: fix reqSource in data path * bump coupledL2 --------- Co-authored-by: Ntastynoob <934348725@qq.com> Co-authored-by: NGuokai Chen <chenguokai17@mails.ucas.ac.cn> Co-authored-by: Nlixin <1037997956@qq.com> Co-authored-by: NXiChen <chenxi171@mails.ucas.ac.cn> Co-authored-by: NZhou Yaoyang <shinezyy@qq.com> Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local> Co-authored-by: Nwakafa <wangkaifan@ict.ac.cn>
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由 happy-lx 提交于
* hint: add CustomHint interface * dcache: fix replacement & mshrId update * access replacement only once per load * update mshrId in replayqueue only when this load enters mshr * replay: block cache miss load * block cache miss load until hint or dcache refill appears * buffer: fix hint buffer depth to 1 * ldu: add dcache miss l2hint fast replay path * bump coupledL2 * bump utility --------- Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local> Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>
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- 31 5月, 2023 1 次提交
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由 wakafa 提交于
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- 30 5月, 2023 3 次提交
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由 sfencevma 提交于
Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>
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由 Maxpicca 提交于
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由 sfencevma 提交于
* LoadQueueReplay: fix worst case, all oldest instructions are allocated to the same bank, and the number of instructions is greater than the number of stages in load unit. * Remove bank conflict block * Increase priority for data replay The deadlock scenario is as follows: The LoadQueueReplay entry will not be released immediately after the instruction is replayed from LoadQueueReplay. For example, after instruction a is replayed from LoadQueueReplay, entry 1 is still valid. If instruction a still needs to be replayed, Entry 1 will be updated again, otherwise entry 1 can be released. If only the time of the first enqueue is used to select replay instructions (age matrix), when there are too many instructions (in LoadQueueReplay) to be replay, some instructions may not be selected. Using the pointer ldWbPtr of the oldest instruction, when the saved lqIdx of the instruction is equal to ldWbPtr and can be replayed, LoadQueueReplay will give priority to the instruction instead of using the selection result of the age matrix. To select older instructions, LoadQueueReplay will calculate pointers such as ldWbPtr, ldWbPtr+1, ldWbPtr+2, ldWbPtr+3..., and if the lqIdx of the instruction is in these results, it will be selected first. When the pointer is compared, there will be an n-bit long mask, and LoadQueueReplay will be from 0 to n-1. When i th bit is valid, select i th instruction. The stride of the pointer comparison is larger than the number of pipeline stages of the load unit, and the selected instruction still needs to be replayed after the first replay (for example, the data is not ready). Worse, in the bit of the mask generated by pointer comparison, the instructions (lqIdx is ldWbPtr+1, ldWbPtr+2, ...) after the oldest instruction (lqIdx is equal to ldWbPtr) are in the lower bit and the oldest instruction is in the higher bit. It cannot select the oldest instruction.
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- 28 5月, 2023 1 次提交
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由 sfencevma 提交于
This commit provides MDP adaptation for #2077 * fix mdp: disable LFST, ssing ssid comparison instead of LFST * add loadWaitStrict when compare SSID * fix store data wakeup logic Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>
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- 26 5月, 2023 1 次提交
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由 wakafa 提交于
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- 25 5月, 2023 2 次提交
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由 wakafa 提交于
* icache: Acquire -> Get to L2 * gitmodules: add coupledL2 as submodule * cpl2: merge coupledL2 into master * Changes includes: * coupledL2 integration * modify user&echo fields in i$/d$/ptw * set d$ never always-releasedata * remove hw perfcnt connection for L2 * bump utility * icache: remove unused releaseUnit * config: minimalconfig includes l2 * Otherwise, dirty bits maintainence may be broken * Known issue: L2 should have more than 1 bank to avoid compiling problem * bump Utility * bump coupledL2: fix bugs in dual-core * bump coupledL2 * icache: set icache as non-coherent node * bump coupledL2: fix dirty problem in L2 ProbeAckData --------- Co-authored-by: Nguohongyu <20373696@buaa.edu.cn> Co-authored-by: NXiChen <chenxi171@mails.ucas.ac.cn>
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由 wakafa 提交于
* script: enable chiseldb by default on running emu by xiangshan.py * script: move db file to wave_home if emu failed
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- 24 5月, 2023 2 次提交
- 23 5月, 2023 7 次提交
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由 Easton Man 提交于
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由 Easton Man 提交于
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由 Easton Man 提交于
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由 Easton Man 提交于
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由 Easton Man 提交于
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由 Easton Man 提交于
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由 sfencevma 提交于
* fix uncache buffer writeback fsm * fix uncache buffer writeback fsm * fix uncache buffer writeback control --------- Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>
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- 21 5月, 2023 1 次提交
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由 sfencevma 提交于
BREAKING CHANGE: new LSU/LQ architecture introduced in this PR In this commit, we replace unified LQ with: * virtual load queue * load replay queue * load rar queue * load raw queue * uncache buffer It will provide larger ooo load window. NOTE: IPC loss in this commit is caused by MDP problems, for previous MDP does not fit new LSU architecture. MDP update is not included in this commit, IPC loss will be fixed by MDP update later. --------- Co-authored-by: NLyn <lyn@Lyns-MacBook-Pro.local>
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- 16 5月, 2023 1 次提交
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由 happy-lx 提交于
* When replacing happens in loadpipe and mainpipe and there are invalid ways, use invalid ways first instead of way calulated by replacer. * Update replacement on 2nd miss only when this request is firstly issued. * dcache: prefer using invalid way when replace When replacing happens in loadpipe and mainpipe and there are invalid ways, use these ways first instead of way calulated by replacer * dcache: fix replacement If a request is merged by dcache, update replacement only when this request is firstly issued * loadpipe: fix compile * ldu: fix s1_repl_way_en
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- 15 5月, 2023 2 次提交
- 10 5月, 2023 3 次提交
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由 Maxpicca 提交于
* add a switch for the WPU in dataArray * dcache: fix cacheop dup logic * dcache: fix wpu parameter
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由 Ma-YX 提交于
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由 Guokai Chen 提交于
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