* According to The RISC-V Instruction Set Manual Volume II:
Privileged Architecture, for instruction-fetch access or
page-fault exceptions on systems with variable-length instructions,
m/stval will contain the virtual address of the portion
of the instruction that caused the fault while m/sepc will
point to the beginning of the instruction.

Makefile: add version information to the generated verilog

See merge request projectn/noop!65

Fetch mmio

See merge request projectn/noop!64

* This will skip instruction fetching from MMIO, which is hard to
  compare with NEMU.

* IFU will send 64-bit fetch requests. Originally flash will only
  response with rdata = 0x00000000????????. For instrucitons aligned at
  4-byte address, IDU will select 0x00000000 as the target instruction.
* To fix this, we let flash reponse with 2 copies.
* Note that RVC instruction stream like 0xccbbbbbbbbaa in flash can not
  be handled correctly. The current solution only support non-RVC code
  in flash.

* NOTE: if we fetch and execute a store instruction from MMIO, currently
  DiffTest can not handle this situation.

Peripheral

See merge request projectn/noop!63

Otherwise the upstream dmemXbar will not behave correctly.

This reverts commit 196971d7.

This reverts commit d336f385.

Otherwise dmemXbar will not behave correctly.

Misc

See merge request projectn/noop!62

* TLB makes timing worse

L2cache prefetch

See merge request projectn/noop!61

Dev linux tlb reconstruct md

See merge request projectn/noop!60

Dev linux

See merge request projectn/noop!59