* ICache:send Get instead of Acquire to L2

* ICache:add vaild_array in metaArray

* [WIP]ICache:annotate invalid coherence modules for icache

* ICache:delete invalid coherence modules for icache

* ICache : add fencei logic

* ICache : fix check multi-hit logic

* pass riscv-tests rv64ui, um tests

* issued should be set to false when not stage success

* deqResp.success is only used by sta

* wakeup can take effect only when valid is assert

* support float memory load/store
* refactor regfile read parameters
  * replace `numSrc` with `numRegSrc` to notice the src data being from regfile
* refactor BusyTable read port
  * make int/vf BusyTable have the same number of read ports to simplify connection in Dispatch2Iq
  * the unused read port will be optimized
* regular IQSize parameters
* split writeback port for scheduler into two kinds by reg types

* srcType of store data is from dispatch2iq.io.out(x).bits.srcType(1)

* `rsIdx` and `isFirstIssue` should be guarded by valid instead connecting from IQ to memBlock directly.

* constant variable: add FPAGPlatform parameter

* scripts: set WITH_CONSTANTIN to 1 by default

* submodules: version to lyq repository for test

* Revert "constant variable: add FPAGPlatform parameter"

This reverts commit fc2f03b7.

* constant: add FPGA init

* chiseldb: add FPGA init

* difftest: version

* chisledb: add envFPGA situation

* DCacheWrapper: add missdb and fix bug in `real_miss`

* DCacheWrapper: add constant control of missdb

* DCacheWrapper: correct the constant control logic

* databases: add constant control

* constantin: afix some bug

* constantin: fix txt

* fixbug: constant control in double core

* constantin: postfix changed in `verilator.mk`

* instDB: add robIdx and some TIME signals

* loadMissDB-copt: rm `resp.bits.firstHit` add `s2_first_hit`

* difftest: update

* yml: update the git workflow

* submodules: fix the binding commit-id of personal fork rep

* fix: github workflow add NOOP_HOME

because in constantin.scala use the absolute path of workdir by environment variable `NOOP_HOME`

* Only dequeue common accepted inst in main deq policy
* Add guard assert in exe unit to avoid some inst not dispatched to fu

* top-down: add rob head type into consideration

* top-down: put counters into EnableTopDown scope

* code opt: optimize duplicate codes

* code opt: fix index

* code opt: add more comments for readability

* code opt: add comments

* code opt: fix comments

* cachedup: code opt for readability

* difftest: monitor cache miss latency

* lq, ldu, dcache: remove lq's data

* lq's data is no longer used
* replay cache miss load from lq (use counter to delay)
* if dcache's mshr gets refill data, wake up lq's missed load
* uncache load will writeback to ldu using ldout_0
* ldout_1 is no longer used

* lq, ldu: add forward port

* forward D and mshr in load S1, get result in S2
* remove useless code logic in loadQueueData

* misc: revert monitor

* lq: change replay cycle

* lq: change replay cycle
* change cycle to 11 36 10 10

* Revert "lq: change replay cycle"

This reverts commit 3ca74b63.
And change replay cycles

* lq: change replay cycle according to dramsim

* change Reselectlen to 7
* change replay cycle to (11, 18, 127, 17) to fit refill delay (14, 36,
188)

* lq: change replay cycle

* change block_cycles_cache to (7, 0, 32, 51)

* lq: change replay cycle

* change block_cycles_cache to (7, 0, 126, 95)

* lq: fix replay ptr update logic

* fix priority of updating ptr
* revert block_cycles_cache

* lq: change tlb replay cycle

* change tlbReplayDelayCycleCtrl to (15, 0, 126, 0)