* Set uopNum at rob's enq instead of using enqCnt to avoid committing before all uop enq.
* There are many uops mapped to the same robIdx. When some of the uops enter rob, while others blocked at rename stage for the lack of free regfiles, committing before all uop enq would happen.
* Distinguish std wb status as before

* all piped function units should extends PipedFuncUnit

* use 9 bits FuOpType

* calculate number of source reg instead of using immediate number

* Add vector config

* Use ctrlVec and dataVec instead of robIdxVec, pcVec, etc.

* OptionWrapper(condition, new T) is more readable than if(condition) Some(new T) else None.

* Since the exu writes different pregs using the same wb bundle,
  intWen/fpWen/vecWen should be considered in WbArbiter's input.

func(UopDivType): support UopDivType.VEC_COMPRESS & vcompress test pass
func(VIMac): add VIMac
pom(yunsuan): add VimacType

* func(UopDivType): support UopDivType.VEC_COMPRESS & vcompress test pass

* func(VIMac): add VIMac

1. support for vmul/vmvmulh/vmvmulhu/vmvmulhsu
2. support for vmacc/vnmsac/vmadd/vnmsub

* pom(yunsuan): add VimacType

* Add unit-test for vset base module

* Add class VType, VConfig
* Add object VSew, VLmul