XiangShan is jointly released by ICT and PCL.

* Now can pass compiling.

[WIP] comment out-of-date code in frontend

[WIP] move NewFtq to xiangshan.frontend and rename class to Ftq

Ibuffer: update sigal names for new IFU

[WIP] remove redundant NewFrontend

[WIP] set entry_fetch_status to f_sent once send req to buf

Fix syntax error in IFU

Fix syntax error in IFU/ICache/Ibuffer

[WIP] indent fix in ftq

BPU: Move GlobalHistory define from IFU.scala to BPU.scala

[WIP] fix some compilation errors

BPU: Remove HasIFUConst
and move some bundles from BPU.scala to frontendBundle.scala

[WIP] fix some compilation errors

[WIP] rename ftq-bpu ios

[WIP] recover some const definitions

[WIP] fix some compilation errors

[WIP]connect some IOs in frontend

BPU: fix syntax error

[WIP] fix compilation errors in predecode

BPU: fix RAS syntax error

[WIP] add some simulation perf counters back

BPU: Remove numBr redefine in ubtb and bim

In this commit, we add License for XiangShan project. 

* LoadQueue: send stFtqIdx via rollback request

* It will make it possible for setore set to update its SSIT

* StoreSet: setup store set update req

* StoreSet: add store set identifier table (SSIT)

* StoreSet: add last fetched store table (LFST)

* StoreSet: put SSIT into decode stage

* StoreSet: put LFST into dispatch1

* Future work: optimize timing

* RS: store rs now supports delayed issue

* StoreSet: add perf counter

* StoreSet: fix SSIT update logic

* StoreSet: delay LFST update input for 1 cycle

* StoreSet: fix LFST update logic

* StoreSet: fix LFST raddr width

* StoreSet: do not force store in ss issue in order

Classic store set requires store in the same store set issue in seq.
However, in current micro-architecture, such restrict will lead to
severe perf lost. We choose to disable it until we find another way
to fix it.

* StoreSet: support ooo store in the same store set

* StoreSet: fix store set merge logic

* StoreSet: check earlier store when read LFST

* If store-load pair is in the same dispatch bundle, loadWaitBit should
also be set for load

* StoreSet: increase default SSIT flush period

* StoreSet: fix LFST read logic

* Fix commit c0e541d1

* StoreSet: add StoreSetEnable parameter

* RSFeedback: add source type

* StoreQueue: split store addr and store data

* StoreQueue: update ls forward logic

* Now it supports splited addr and data

* Chore: force assign name for load/store unit

* RS: add rs'support for store a-d split

* StoreQueue: fix stlf logic

* StoreQueue: fix addr wb sq update logic

* AtomicsUnit: support splited a/d

* Parameters: disable store set by default

* WaitTable: wait table will not cause store delay

* WaitTable: recover default reset period to 2^17

* Fix dev-stad merge conflict

* StoreSet: enable storeset

* RS: disable store rs delay logic

CI perf shows that current delay logic will cause perf loss. Disable
unnecessary delay logic will help.

To be more specific, `io.readyVec` caused the problem. It will be
updated in future commits.

* RS: opt select logic with load delay (ldWait)

* StoreSet: disable 2-bit lwt
Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr.
(2) DPI-C is cross-platform (Verilator, VCS, ...)
(3) difftest APIs are splited from emu.cpp to possibly support more backend platforms
(NEMU, Spike, ...)

The performance at this commit is quite slower than the original emu.
Performance issues will be fixed later.

* [WIP] SimTop: try to use 'XSTop' as soc

* CircularQueuePtr: ues F-bounded polymorphis instead implict helper

* Refactor parameters & Clean up code

* difftest: support basic difftest

* Support diffetst in new sim top

* Difftest; convert recode fmt to ieee754 when comparing fp regs

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Debug: add int/exc inst wb to debug queue

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Difftest: fix naive commit num limit
Co-authored-by: NYinan Xu <xuyinan1997@gmail.com>
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

* ras: partly handle stack overflow problems

* ras: add overflow and underflow statistics

* csr: remove unused input perfcnt io

* perfcnt: add some in-core hardware performance counters

* perfcnt: optimize timing for hardware performance counters

XSPerfAccumulate: sum up performance values.
XSPerfHistogram: count the occurrence of performance values, split them
into bins, so that we can estimate their distribution.
XSPerfMax: get max of performance values.

* perf: set acc arg of XSPerf as false by default

* perf: add write-port competition counter for intBlock & floatBlock

* perf: remove prefix of perf signal

* perf: add perf-cnt for interface between frontend & backend

* perf: modify perf-cnt for prefetchers

* Ftq: bypass 'commit state' to fix dequeue bug

* perf: uptimize perf-cnt in ctrlblock & ftq

* perf: fix compilation problem in ftq

* perf: remove duplicate perf-cnt

* perf: calcu extra walk cycle exceeding frontend flush bubble

* Revert "perf: calcu extra walk cycle exceeding frontend flush bubble"

This reverts commit 2c30e9896b6af93a34e2d8d78055d810ebd0ac70.

* perf: add perf-cnt for ifu

* perf: add perf-cnt for rs

* RS: optimize numExist signal

* RS: fix some typo

* perf: add QueuePerf util to monitor usage info of queues

* perf: remove some duprecate perfcnt

* add perf counters for btb and ubtb
* update btb only on not hit or jalr mispredicts to reduce write stalls

previously the biggest problem was using '+' instead of '+&' to
do sums

* core: enable sc

* sc: calculate sum again on update

* sc: clean ups

* sc: add some debug info

* sc, tage, bim: fix wrbypass logic, add wrbypass for SC

* sc: restrict threshold update conditions and prevent overflow problem

* sc: use seperative thresholds for each bank

* sc: update debug info

* sc: use adaptive threshold algorithm from the original O-GEHL

* tage, bim, sc: optimize wrbypass logic

* sc: initialize threshold to 60

* loop: remove unuseful RegNext on redirect

* ifu: add perf counters

* Perf: Add loopPredictor perf counters

* sc: fix perf logics
Co-authored-by: Njinyue110 <jinyue161@mails.ucas.ac.cn>
Co-authored-by: Nzoujr <18870680299@163.com>

* core: enable sc

* sc: calculate sum again on update

* sc: clean ups

* sc: add some debug info

* sc, tage, bim: fix wrbypass logic, add wrbypass for SC

* sc: restrict threshold update conditions and prevent overflow problem

* sc: use seperative thresholds for each bank

* sc: update debug info

* sc: use adaptive threshold algorithm from the original O-GEHL

* tage, bim, sc: optimize wrbypass logic

* sc: initialize threshold to 60

* loop: remove unuseful RegNext on redirect

* Replacement: change state in way method.

* State change is also needed when miss occurs, otherwise we will choose
a way that has been just refilled into cache as the victim.

* Optimize ctrlblock timing (#620)

* CtrlBlock: delay exception flush for 1 cycle

* CtrlBlock: delay load replay for 1 cycle

* roq: delay wb from exu for one clock cycle to meet timing

* CtrlBlock: fix pipeline bug between decode and rename
Co-authored-by: NYinan Xu <xuyinan1997@gmail.com>

* L1plusCache: use plru replacement policy.

* ICache: fix mmio bugs

1. MMIO cut helper uses packet align logic
2. still send req to uncache when flush

* ICache: change packet from mmio

use packet align as the mem

* IntrUncache: fix state bug

state will change into s_invalid and get stuck

* fix Registers that not being initiated

* core: enable sc

* sc: calculate sum again on update

* sc: clean ups

* sc: add some debug info

* sc, tage, bim: fix wrbypass logic, add wrbypass for SC

* core: disable sc by default
Co-authored-by: Njinyue110 <jinyue161@mails.ucas.ac.cn>

We pass redirect ghist directly to a mux, whose output is connected
to bpu.s1_hist, so that the delay of three cascaded 64-bit-wide 2-1
mux could be saved