wrap pipeline-connect into module

BlockInclusiveCache: track new commits.

LoadUnit, LoadQueue: add independent fp load wb port

Fp load uses different wb port from int load for 2 reasons:
* Fp load needs recode, which is quite slow. We need one complete cycle
for recoding.
* Fp load data has nothing to do with int load data. There is no reason
to mix them together.

An extra recode stage (load_s3) is added for fp load, while int load will
still be writebackd at load_s2.

ICache: enable icache ECC

Opt sbuffer timing

BlockInclusiveCache: track new commits(turn off L2 log by default).

ram,axi4: move axi things out of ram.cpp and fix some bugs

L1plusCache: change default size configuration to 128KB.

ram: update DRAMsim3 interface

dispatch queue: wrap data into DataModuleTemplate