Previously the BranchPredictionUpdate bundle was inherited from
BranchPredictionBundle, and that made some field of the bundle
unused. It was hard to find which signals are really in use.
Now we make BranchPredictionUpdate a independent bundle, so that
the signals in it are all in use.

if a req with a last half but miss predicted enters in wb stage, and this cycle f3 stalls, we set a flag to notify f3 that the last half flag need not to be set.

* <bug-fix> IFU: cancel lastHalf for miss prediction

* <bug-fix> ICacheMainPipe: latch tlb resp for stall

* <bug-fix> only tlb_slot.valid can raise has_latch

* copy Ftq to ICache read valid signal

* move sram read data and miss data selection to IFU (after predecode)

* copy address select signal for every copied port
* add 1 more copy for itlb request use
* add 1 cycle latency for ftq_pc_mem read before sending to IPrefetch

* this bug is caused by trigger wait_state for a hit pmp af req

* <bug-fix>: fix port_1_read_0 condition

* should use RegNext on ftq_pc_mem rdata with the wrapper implementation now

ftq, ctrl: fix newest_target logic, pass it to ctrlblock, remove jalrTargetMem and read target from pc_mem

* add diff for upate_target and pc_mem result

ftq, ctrl: add second write port logic of jalrTargetMem, and delay write of pc/target mem for two cycles