- 21 12月, 2021 1 次提交
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由 William Wang 提交于
This commit removed PriorityEncoder in sbuffer enq path. It should improve sbuffer enqueue timing.
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- 22 10月, 2021 1 次提交
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由 William Wang 提交于
* mem: support ld-ld violation check * mem: do not fast wakeup if ld vio check failed * mem: disable ld-ld vio check after core reset
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- 19 9月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit adds load balance strategy in issue selection logic for reservation stations. Previously we have a load balance option in ExuBlock, but it cannot work if the function units have feedbacks to RS. In this commit it is removed. This commit adds a victim index option for oldestFirst. For LOAD, the first issue port has better performance and thus we set the victim index to 0. For other function units, we use the last issue port.
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- 05 9月, 2021 1 次提交
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由 Yinan Xu 提交于
This commit adds assertion in MaskData to check the width of mask and data. When the width of mask is smaller than the width of data, (~mask & data) and (mask & data) will always clear the upper bits of the data. This usually causes unexpected behavior. This commit adds explicit width declarations where MaskData is used.
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- 24 7月, 2021 1 次提交
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由 Yinan Xu 提交于
XiangShan is jointly released by ICT and PCL.
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- 17 7月, 2021 1 次提交
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由 Yinan Xu 提交于
* better select policy timing * unified RS enqueue ports for 4 ALUs * wrap imm extractor into a module * backend,rs: wrap dataArray in RawDataModuleTemplate * should only bypass data between the same addr when allocate.valid
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- 08 7月, 2021 1 次提交
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由 Yinan Xu 提交于
* better select policy timing * unified RS enqueue ports for 4 ALUs * wrap imm extractor into a module * backend,rs: wrap dataArray in RawDataModuleTemplate * should only bypass data between the same addr when allocate.valid
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- 04 6月, 2021 1 次提交
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由 Lemover 提交于
In this commit, we add License for XiangShan project.
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- 11 3月, 2021 1 次提交
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由 Yinan Xu 提交于
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- 28 2月, 2021 1 次提交
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由 William Wang 提交于
* WaitTable: add waittable framework * WaitTable: get replay info from RedirectGenerator * StoreQueue: maintain issuePtr for load rs * RS: add loadWait to rs (only for load Unit's rs) * WaitTable: fix update logic * StoreQueue: fix issuePtr update logic * chore: set loadWaitBit in ibuffer * StoreQueue: fix issuePtrExt update logic Former logic does not work well with mmio logic We may also make sure that issuePtrExt is not before cmtPtrExt * WaitTable: write with priority * StoreQueue: fix issuePtrExt update logic for mmio * chore: fix typos * CSR: add slvpredctrl * slvpredctrl will control load violation predict micro architecture * WaitTable: use xor folded pc to index waittable Co-authored-by: NZhangZifei <1773908404@qq.com>
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- 28 1月, 2021 1 次提交
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由 William Wang 提交于
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- 24 1月, 2021 1 次提交
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由 Allen 提交于
Now, it can compile.
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- 12 12月, 2020 1 次提交
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由 Yinan Xu 提交于
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- 11 12月, 2020 1 次提交
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由 Yinan Xu 提交于
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- 22 11月, 2020 2 次提交
- 16 9月, 2020 1 次提交
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由 LinJiawei 提交于
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- 07 9月, 2020 1 次提交
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由 William Wang 提交于
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- 30 7月, 2020 1 次提交
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由 Allen 提交于
Now mshrs can end transaction and go to replay.
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- 24 7月, 2020 1 次提交
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由 Allen 提交于
Just compiles.
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- 16 7月, 2020 1 次提交
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由 GouLingrui 提交于
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- 14 7月, 2020 2 次提交
- 04 10月, 2019 1 次提交
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由 Zihao Yu 提交于
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- 03 10月, 2019 2 次提交
- 26 9月, 2019 1 次提交
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由 Zihao Yu 提交于
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- 19 9月, 2019 2 次提交
- 25 8月, 2019 1 次提交
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由 Zihao Yu 提交于
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