Todo: connect them

Todo: support more policies

Todo: support more policies

New DataArray will be used as immArray and payloadArray in IssueQueue.

TODO: fix wfi bug in misc-tests

In other words, rm param/if-else from extraio(csrio/frm/fence)

In order to make different bundle of Int and Vec to look like the
same or to use as the same, add a method to include both.
Such as:
issue: {
  val issueInt
  val issueVec
  def issue = issueInt ++ issueFp
}
or Exu's FuIn: {
  val fromInt
  val fromVec
  def fuIn = fromInt or fromVec
}

Unify different type of bundle by the "def" method.

There are actual useful changes besides coding style. Meaningful
changes that makes codes more clean by divides int/fp/vec into their
sub-class will be done later.

Creates ExuBlock/FUBlock/Schduler's sub-class. The sub-class has
not meaningful codes now.

There are no actual useful changes. Just from Seq(ExuBlock) into
  intExuBlock + vecExuBlock

TODO: modify the asynchronous read regfile to synchronous read regfile

chore(*): Change Sequential Parameter Pass to Parameter Name Parameter Passing

refactor(Regfile): Modify Synchronous Read to Asynchronous Read

refactor(Scheduler, ReservationStationBase): Connect the asynchronous read port of the register and the reserved station

1. add parameter( numIntRfReadPorts, numFpRfReadPorts, params.exuCfg)
2. fix extractReadRf
3. remove dataArray and add dataArrayWrite, dataArrayMultiWrite,
s1_out_addr
4. add immBypassedData2 for bypass and fix DataSelect

refactor(ReservationStationStd):  fix connect between s1_deqRfDataSel and readFpRf_asyn(i).data

refactor(ReservationStationJump):  add jalrMem and fix immExts connect

* Remove vxsatWen in generate
* Fix duplicated BitPat error
  * VNCLIPU_WV -> VNCLIPU_WX/VNCLIPU_WI
  * VNCLIP_WV -> VNCLIP_WX/VNCLIP_WI

* Use default params to avoid modification when adding new decode fields
* Add new decode field "vecWen"
* Replace rocketchip.decoder with ListLookUp
  * chisel3.minimizer causes Java OutOfMemory exception or function params error when adding new vector insts
  * Replace all X's with 0's, since the type param of ListLookUp must inherit chisel3.Data and BitPat does not inherit from chisel3.Data

This commit sets up a basic dcache way predictor framework and a dummy predictor.
A Way Predictor Unit (WPU) module has been added to dcache. Dcache data SRAMs
have been reorganized for that. 

The dummy predictor is disabled by default. 

Besides, dcache bank conflict check has been optimized. It may cause timing problems,
to be fixed in the future.

* ideal wpu

* BankedDataArray: change architecture to reduce bank_conflict

* BankedDataArray: add db analysis

* Merge: the rest

* BankedDataArray: change the logic of rrl_bank_conflict, but let the number of rw_bank_conflict up

* Load Logic: changed to be as expected

reading data will be delayed by one cycle to make selection
writing data will be also delayed by one cycle to do write operation

* fix: ecc check error

* update the gitignore

* WPU: add regular wpu and change the replay mechanism

* WPU: fix refill fail bug, but a new addiw fail bug appears

* WPU: temporarily turn off to PR

* WPU: tfix all bug

* loadqueue: fix the initialization of replayCarry

* bankeddataarray: fix the bug

* DCacheWrapper: fix bug

* ready-to-run: correct the version

* WayPredictor: comments clean

* BankedDataArray: fix ecc_bank bug

* Parameter: set the enable signal of wpu

This commit changes the reset of all modules to asynchronous style,
including changes on the initialization values of some registers.
For async registers, they must have constant reset values.