* make vme will extract verilog module from sim_top.v
* make phy_evaluate/phy_evaluate_atc will generate timing rpts
using remote server

ram: fix write index checking

don't bypass psrc1/psrc2/psrc3/old_pdest in rename and leave them to dispatch1 for bypassing

Writeback cached store in pipeline

* To make future update easier, we keep using microOp instead of
separate fields

XiangShanStage: use '--remove-assert' to remove all '$fatal' in verilog

Opt ibuf

bug fixes in DecodeBuffer, Roq, Dispatch1 and Freelist

SoC: move l2cache to SoC

replace $fatal with $finish to avoid verilator abort

Makefile: replace $fatal with $stop to avoid verialtor stopped during eval without providing snapshots

Rename now provides vectors indicating whether there're matches between lsrc1/lsrc2/lsrc3/ldest
and previous instructions' ldest. Dispatch1 updates uops' psrc1/psrc2/psrc3/old_pdest with
previous instructions pdest. This method optimizes rename' timing.