* Add cache ctrl node

* L2/L3: Reduce client dir size

* Ctrl: connect soft reset from L3 to core

* Add pll

* Config: seperate SocParams and CoreParams to get correct number of cores

* Bump huancun

* Add pll output

* Fix inclusive cache config

* Add one more pll ctrl reg

* Bump huancun

It helps frontend to get hit result at same cycle and keep req when miss.
Then the itlb can set 'samecycle' to false for better timing.
In a word, it helps to better change non-blocked dtlb to a blocked itlb

* bump huancun

* ptw: consider flush in mem_arb's ready

* l2tlb: add repeater/filter's object apply method

* l2tlb: add one more cycle(repeater) between itlb and l2tlb

* mem: update lsu op encoding
* decode: remove prefetch bits from CtrlSignals
* mem: simplify software prefetch logic in loadpipe
* mem: fix wrong dcacheShouldResp assertion

* Bump huancun

* Simplify l2 -> l3 cross bar

* HuanCun: remove debug print

* Svinval: implement Svinval
* add three new instructions(SINVAL_VMA SFENCE_W_INVAL SFENCE_INVAL_IR)
* TODO : test

* Prevent illegal software code by adding an assert
* make sure the software runs as follow:
  begin instruction of svinval extension
  svinval xxxx
  svinval xxxx
  ...
  end instruction of svinval extension

* Svinval: add an CSR to control it and some annotations

* Roq: fix assert bug of Svinval

* Svinval: fix svinval.vma's rs2 type
* make it reg instead of imm

* Svinval: change assert logic and fix bug
* fix the condition judging Svinval.vma instruction
* using doingSvinval in assert

* ci: add rv64mi-p-svinval to ci

* fix typo

* fix bug that lost ','

* when svinval disable, raise illegal instr excep

* CSR: mv svinval ctl to srnctl(1)

* rob: when excep, do not set dosvinval

* decode: when disable svinval, do not set flushpipe

* bump ready-to-run
Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>

* pc which is the start of a pagefault cacheline was not treated as page fault

top: remove osc_clock and pll_output

remove the old hard-wired pma and turn to pmp-like csr registers. the pma config is writen in pma register.
1. pma are m-priv csr, so only m-mode csrrw can change pma
2. even in m-mode, pma should be always checked, no matter lock or not
3. so carefully write pma, make sure not to "suicide"

* pma: add pmp-like pma, just module/bundle added, not to circuit

use reserved 2 bits as atomic and cached

* pma: add pmp-like pma into pmp module

pma have two more attribute than pmp
1. atmoic;
2. c/cache, if false, go to mmio.

pma uses 16+4 machine-level custom ready write csr.
pma will always be checked even in m-mode.

* pma: remove the old MemMap in tlb, mmio arrives next cycle

* pma: ptw raise af when mmio

* pma: fix bug of match's zip with last entry

* pma: fix bug of pass reset signal through method's parameter

strange bug, want to reset, pass reset signal to a method, does not
work.
import chisel3.Module.reset, the method can access reset it's self.

* pma: move some method to trait and fix bug of pma_init value

* pma: fix bug of pma init value assign way

* tlb: fix stupid bug that pf.ld not & fault_valid

* loadunit: fix bug that uop is flushed, pmp's dcache kill failed also

* ifu: mmio access needs f2_valid now

* loadunit: if mmio and have sent fastUop, flush pipe when commit

* storeunit: stu->lsq at stage1 and re-in lsq at stage2 to update mmio

* Bump HuanCun
* Increase L2/L3 latency
* Change 10MB L3 to default config
* Bump difftest

This commit changes when instructions enter load/store queue.
Now, at dispatch2, load/store instructions enter load/store queue.

share ftb tail slot for br and jmp, fix ittage performance bugs

* Add perf counters
* add reg from hpm counter source
* add print perfcounter enable

* l2tlb: opt timing of req_addr_low to page cache

* l2tlb: change signal name from first/secode to stage1/2

* l2tlb: page cache forgot satp.changed before, add it

* util: update DataHoldBypass, more general

* util: update PipelineConnect, add block signal

* l2tlb: page cache now need 3 cycle: in/read | read back/ecc check | out

* l2tlb: set ecc block to XLEN(64)

* l2tlb: when ecc error, dont hit. do it same cycle

* tlb: optimize repalce io, for covering refill and better timing

Now uncache store may commit together with cached store. For example:

0: sd to uncache_addr
4: sd to cache_addr
8: sd to cache_addr
May commit in the same cycle.

It should eliminate wrong assertion in xalancbmk.

* InstrUncache: change into 1 instruciton logic

* Frontend: add MMIO fetch port

* IFU: flush pipeline and only pass 1 instruction to backend when
finding the address is mmio

* BPU: set the resetVector to 10000000

* Frontend: connect ifu.uncache to instrUncache

* IFU: Fix conflict with master

* IFU: fix mmio instruction prediction problem

* IFU: fix tlb af only hold 1 cycle

This PR optimizes out isFused and crossPageIPFFix usages in Rob's DispatchData. They will not be stored in ROB. Now DispatchData has only 38 bits.

* isFused is merged with commitType (2 bits reduced)
* crossPageIPFFix is used only in ExceptionGen (1 bit reduced)
* rename: reduce ldest usages
* decode: set isMove to false if ldest is zero

* bump difftest & huancun

* mem: support ld-ld violation check
* mem: do not fast wakeup if ld vio check failed
* mem: disable ld-ld vio check after core reset

In the latest version of dcache, replace pipe is blocked by main pipe according to set, because replace and store/probe should not try to modify data or meta at the same time, which might result in inconsistency between data and meta. For performance reasons, replace is blocked by store, not the other way around, because replace can be delayed so it can bring dirty data written by store down to L2.

Now this consideration brings another dead-lock. Store buffer keeps sending store request without a break, so main pipe stays occupied handling store. In the meantime, miss queue rejects these store request so store buffer keeps replaying all the time. Replace pipe cannot advance because of set conflict with main pipe, so the corresponding miss entry cannot be released and keeps rejecting new store request.

To break this dead-lock, this pull request tries to set replace pipe higher priority than main pipe, and let write-back queue handle consistency between data and meta if a store interrupts.

Modify FTB replacement strategy to PLRU