- 12 11月, 2021 3 次提交
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由 ZhangZifei 提交于
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由 ZhangZifei 提交于
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由 ZhangZifei 提交于
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- 11 11月, 2021 1 次提交
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由 ZhangZifei 提交于
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- 05 11月, 2021 3 次提交
- 04 11月, 2021 4 次提交
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由 Steve Gou 提交于
PreDecode: fix cross-line false hit condition
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由 Steve Gou 提交于
Predecode: Fixed the bug that Predecode did not compare jal offset wh…
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由 William Wang 提交于
* dcache: do not check readline rmask This should opt bank_conflict check timing * dcache: block replace if store s1 valid It takes quite long to generate way_en in mainpipe s1. As a result, use s1 way_en to judge if replace should be blocked will cause severe timing problem Now we simply block replace if mainpipe.s1.valid Refill timing to be optmized later * sbuffer: delay sbuffer enqueue for 1 cycle With store queue growing larger, read data from datamodule nearly costs a whole cycle. Hence we delay sbuffer enqueue for 1 cycle for better timing. * dcache: reduce probe queue size * dcache: replace probe pipe req RRArbiter with Arbiter * dcache: reduce writeback queue size for timing opt * dcache: delay wbqueue enqueue req for 1 cycle Addr enqueue req will compare its addr with addrs in all writeback entries to check if it should be blocked. Delay enqueue req will give that process more time. * dcache: set default replacer to setplru It does not change current design * dcache: fix wbqueue req_delayed deadlock We delayed writeback queue enq for 1 cycle, missQ req does not depend on wbQ enqueue. As a result, missQ req may be blocked in req_delayed. When grant comes, that req should also be updated * dcache: remove outdated require * dcache: replace missReqArb RRArbiter with Arbiter * perf: add detailed histogram for low dcache latency * dcache: fix wbqueue entry alloc logic * dcache: opt probe req timing In current design, resv_set is maintained in dcache. All probe req will be blocked if that addr is in resv_set. However, checking if that addr is in resv_set costs almost half a cycle, which causes severe timing problem. Now when we update update_resv_set, all probe reqs will be blocked in the next cycle. It should give Probe reservation set addr compare an independent cycle, which will lead to better timing
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由 JinYue 提交于
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- 02 11月, 2021 2 次提交
- 01 11月, 2021 3 次提交
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由 zoujr 提交于
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由 Jay 提交于
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由 Lemover 提交于
* tlb: timing optimization, fault doesn't care hit now * mem.atomic: 'paddr write to reg' dont care hit * mem.atomic: regnext exception and check them next cycle * tlb.hit: dont care set-bits when hit check * storequeue: divide tlb.miss with paddr write for opt timing * mem.atomic: fix bug that wrong usage addrAligned
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- 30 10月, 2021 2 次提交
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由 Yinan Xu 提交于
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由 Jiawei Lin 提交于
* Add cache ctrl node * L2/L3: Reduce client dir size * Ctrl: connect soft reset from L3 to core * Add pll * Config: seperate SocParams and CoreParams to get correct number of cores * Bump huancun * Add pll output * Fix inclusive cache config * Add one more pll ctrl reg * Bump huancun
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- 29 10月, 2021 5 次提交
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由 Lemover 提交于
It helps frontend to get hit result at same cycle and keep req when miss. Then the itlb can set 'samecycle' to false for better timing. In a word, it helps to better change non-blocked dtlb to a blocked itlb
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由 William Wang 提交于
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由 William Wang 提交于
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由 Jiawei Lin 提交于
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由 Jay 提交于
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- 28 10月, 2021 1 次提交
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由 wakafa 提交于
* bump huancun * ptw: consider flush in mem_arb's ready
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- 27 10月, 2021 4 次提交
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由 Lemover 提交于
* l2tlb: add repeater/filter's object apply method * l2tlb: add one more cycle(repeater) between itlb and l2tlb
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由 William Wang 提交于
* mem: update lsu op encoding * decode: remove prefetch bits from CtrlSignals * mem: simplify software prefetch logic in loadpipe * mem: fix wrong dcacheShouldResp assertion
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由 Jiawei Lin 提交于
* Bump huancun * Simplify l2 -> l3 cross bar * HuanCun: remove debug print
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由 happy-lx 提交于
* Svinval: implement Svinval * add three new instructions(SINVAL_VMA SFENCE_W_INVAL SFENCE_INVAL_IR) * TODO : test * Prevent illegal software code by adding an assert * make sure the software runs as follow: begin instruction of svinval extension svinval xxxx svinval xxxx ... end instruction of svinval extension * Svinval: add an CSR to control it and some annotations * Roq: fix assert bug of Svinval * Svinval: fix svinval.vma's rs2 type * make it reg instead of imm * Svinval: change assert logic and fix bug * fix the condition judging Svinval.vma instruction * using doingSvinval in assert * ci: add rv64mi-p-svinval to ci * fix typo * fix bug that lost ',' * when svinval disable, raise illegal instr excep * CSR: mv svinval ctl to srnctl(1) * rob: when excep, do not set dosvinval * decode: when disable svinval, do not set flushpipe * bump ready-to-run Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
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- 26 10月, 2021 4 次提交
- 25 10月, 2021 1 次提交
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由 Lemover 提交于
remove the old hard-wired pma and turn to pmp-like csr registers. the pma config is writen in pma register. 1. pma are m-priv csr, so only m-mode csrrw can change pma 2. even in m-mode, pma should be always checked, no matter lock or not 3. so carefully write pma, make sure not to "suicide" * pma: add pmp-like pma, just module/bundle added, not to circuit use reserved 2 bits as atomic and cached * pma: add pmp-like pma into pmp module pma have two more attribute than pmp 1. atmoic; 2. c/cache, if false, go to mmio. pma uses 16+4 machine-level custom ready write csr. pma will always be checked even in m-mode. * pma: remove the old MemMap in tlb, mmio arrives next cycle * pma: ptw raise af when mmio * pma: fix bug of match's zip with last entry * pma: fix bug of pass reset signal through method's parameter strange bug, want to reset, pass reset signal to a method, does not work. import chisel3.Module.reset, the method can access reset it's self. * pma: move some method to trait and fix bug of pma_init value * pma: fix bug of pma init value assign way * tlb: fix stupid bug that pf.ld not & fault_valid * loadunit: fix bug that uop is flushed, pmp's dcache kill failed also * ifu: mmio access needs f2_valid now * loadunit: if mmio and have sent fastUop, flush pipe when commit * storeunit: stu->lsq at stage1 and re-in lsq at stage2 to update mmio
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- 24 10月, 2021 3 次提交
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由 Jiawei Lin 提交于
* Bump HuanCun * Increase L2/L3 latency * Change 10MB L3 to default config * Bump difftest
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由 Yinan Xu 提交于
This commit changes when instructions enter load/store queue. Now, at dispatch2, load/store instructions enter load/store queue.
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由 zhanglinjuan 提交于
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- 23 10月, 2021 4 次提交