- 10 1月, 2023 1 次提交
-
-
由 Ziyue Zhang 提交于
-
- 09 1月, 2023 2 次提交
-
-
由 Ziyue Zhang 提交于
-
由 Ziyue Zhang 提交于
-
- 08 1月, 2023 3 次提交
-
-
由 ZhangZifei 提交于
-
由 ZhangZifei 提交于
-
由 ZhangZifei 提交于
There are actual useful changes besides coding style. Meaningful changes that makes codes more clean by divides int/fp/vec into their sub-class will be done later. Creates ExuBlock/FUBlock/Schduler's sub-class. The sub-class has not meaningful codes now.
-
- 07 1月, 2023 1 次提交
-
-
由 ZhangZifei 提交于
There are no actual useful changes. Just from Seq(ExuBlock) into intExuBlock + vecExuBlock
-
- 06 1月, 2023 8 次提交
-
-
由 czw 提交于
TODO: modify the asynchronous read regfile to synchronous read regfile
-
-
由 czw 提交于
chore(*): Change Sequential Parameter Pass to Parameter Name Parameter Passing refactor(Regfile): Modify Synchronous Read to Asynchronous Read refactor(Scheduler, ReservationStationBase): Connect the asynchronous read port of the register and the reserved station 1. add parameter( numIntRfReadPorts, numFpRfReadPorts, params.exuCfg) 2. fix extractReadRf 3. remove dataArray and add dataArrayWrite, dataArrayMultiWrite, s1_out_addr 4. add immBypassedData2 for bypass and fix DataSelect refactor(ReservationStationStd): fix connect between s1_deqRfDataSel and readFpRf_asyn(i).data refactor(ReservationStationJump): add jalrMem and fix immExts connect
-
由 Xuan Hu 提交于
-
由 Xuan Hu 提交于
-
由 Xuan Hu 提交于
* Remove vxsatWen in generate * Fix duplicated BitPat error * VNCLIPU_WV -> VNCLIPU_WX/VNCLIPU_WI * VNCLIP_WV -> VNCLIP_WX/VNCLIP_WI
-
由 Xuan Hu 提交于
* Use default params to avoid modification when adding new decode fields * Add new decode field "vecWen" * Replace rocketchip.decoder with ListLookUp * chisel3.minimizer causes Java OutOfMemory exception or function params error when adding new vector insts * Replace all X's with 0's, since the type param of ListLookUp must inherit chisel3.Data and BitPat does not inherit from chisel3.Data
-
由 Xuan Hu 提交于
-
- 05 1月, 2023 2 次提交
-
-
由 ZhangZifei 提交于
-
由 ZhangZifei 提交于
-
- 04 1月, 2023 1 次提交
-
-
由 Maxpicca 提交于
This commit sets up a basic dcache way predictor framework and a dummy predictor. A Way Predictor Unit (WPU) module has been added to dcache. Dcache data SRAMs have been reorganized for that. The dummy predictor is disabled by default. Besides, dcache bank conflict check has been optimized. It may cause timing problems, to be fixed in the future. * ideal wpu * BankedDataArray: change architecture to reduce bank_conflict * BankedDataArray: add db analysis * Merge: the rest * BankedDataArray: change the logic of rrl_bank_conflict, but let the number of rw_bank_conflict up * Load Logic: changed to be as expected reading data will be delayed by one cycle to make selection writing data will be also delayed by one cycle to do write operation * fix: ecc check error * update the gitignore * WPU: add regular wpu and change the replay mechanism * WPU: fix refill fail bug, but a new addiw fail bug appears * WPU: temporarily turn off to PR * WPU: tfix all bug * loadqueue: fix the initialization of replayCarry * bankeddataarray: fix the bug * DCacheWrapper: fix bug * ready-to-run: correct the version * WayPredictor: comments clean * BankedDataArray: fix ecc_bank bug * Parameter: set the enable signal of wpu
-
- 03 1月, 2023 3 次提交
-
-
由 Haoyuan Feng 提交于
-
由 ZhangZifei 提交于
-
由 ZhangZifei 提交于
-
- 02 1月, 2023 3 次提交
-
-
由 Yinan Xu 提交于
This commit changes the reset of all modules to asynchronous style, including changes on the initialization values of some registers. For async registers, they must have constant reset values.
-
由 Yinan Xu 提交于
-
由 Haoyuan Feng 提交于
* PTW: Fix a bug when sfence * PTW: Fix mem_addr_update when sfence
-
- 29 12月, 2022 3 次提交
-
-
由 ZhangZifei 提交于
-
由 ZhangZifei 提交于
-
由 ZhangZifei 提交于
-
- 28 12月, 2022 1 次提交
-
-
由 happy-lx 提交于
This PR remove data in lq. All cache miss load instructions will be replayed by lq, and the forward path to the D channel and mshr is added to the pipeline. Special treatment is made for uncache load. The data is no longer stored in the datamodule but stored in a separate register. ldout is only used as uncache writeback, and only ldout0 will be used. Adjust the priority so that the replayed instruction has the highest priority in S0. Future work: 1. fix `milc` perf loss 2. remove data from MSHRs * difftest: monitor cache miss latency * lq, ldu, dcache: remove lq's data * lq's data is no longer used * replay cache miss load from lq (use counter to delay) * if dcache's mshr gets refill data, wake up lq's missed load * uncache load will writeback to ldu using ldout_0 * ldout_1 is no longer used * lq, ldu: add forward port * forward D and mshr in load S1, get result in S2 * remove useless code logic in loadQueueData * misc: revert monitor
-
- 25 12月, 2022 8 次提交
-
-
-
由 Ziyue Zhang 提交于
-
由 ZhangZifei 提交于
-
由 ZhangZifei 提交于
-
由 ZhangZifei 提交于
-
由 wakafa 提交于
* misc: add utility submodule * misc: adjust to new utility framework * bump utility: revert resetgen * bump huancun
-
由 ZhangZifei 提交于
-
由 ZhangZifei 提交于
-
- 24 12月, 2022 4 次提交
-
-
-
由 Haojin Tang 提交于
-
-
由 Ziyue Zhang 提交于
-