• W
    mem: refactor l1 error implementation (#1391) · 9ef181f4
    William Wang 提交于
    * dcache: add source info in L1CacheErrorInfo
    
    * ICache: fix valid signal and add source/opType
    
    * dcache: fix bug in ecc error
    
    * mem,csr: send full L1CacheErrorInfo to CSR
    
    * icache: provide cache error info for CSR
    
    * dcache: force resp hit if tag ecc error happens
    
    * mem: reorg l1 cache error report path
    
    Now dcache tag error will force trigger a hit
    
    * dcache: fix readline ecc check error
    
    * dcache: mainpipe will not be influenced by tag error
    
    * dcache: fix data ecc check error
    
    * dcache: if coh state is Nothing, do not raise error
    Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>
    Co-authored-by: NJinYue <jinyue20s@ict.ac.cn>
    9ef181f4
ICacheMainPipe.scala 27.6 KB