• W
    Optmize memblock timing (#1218) · 96b1e495
    William Wang 提交于
    DCache timing problem has not been solved yet. DCache structure will be further changed.
    
    * sbuffer: add extra perf counters
    
    * sbuffer: optmize timeout replay check timing
    
    * sbuffer: optmize do_uarch_drain check timing
    
    Now we only compare merge entry's vtag, check will not start until
    mergeIdx is generated by PriorityEncoder
    
    * mem, lq: optmize writeback select logic timing
    
    * dcache: replace missqueue reill req arbiter
    
    * dcache: refactor missqueue entry select logic
    
    * mem: add comments for lsq data
    
    * dcache: give amo alu an extra cycle
    
    * sbuffer: optmize sbuffer forward data read timing
    96b1e495
MissQueue.scala 23.0 KB