• W
    l1,missq: enable aggressive prefetch/store merge · 26360b3c
    William Wang 提交于
    This commit update coh check assertion to enable aggressive
    prefetch miss req / store miss req merge. Previous wrong
    assertion forbids store req from stoping a previous prefetch
    
    For example, consider 2 reqs with the same p address fire in order:
    1) A prefetch with alias bit 00 need to change coh state from N->T
    2) A store with alias bit 11 need to change coh state from B->T
    Then prefetch and store miss req will be merged in the same missq
    entry. Store req (2) should be able to stop prefetch (1) so that a
    ping-pong process will not start
    26360b3c
MissQueue.scala 29.6 KB