- 15 4月, 2020 1 次提交
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由 Zihao Yu 提交于
X86 opt See merge request projectn/nemu!53
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- 07 4月, 2020 16 次提交
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
* we should not write to dsrc1 * the masking of shamt can be eliminated
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
* shift instructions only use the lower 5 bits as shift amount, therefore there is no need to clear the high part of shift amount
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由 Zihao Yu 提交于
* `lui_imm` only have 20 bits
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
Rv64 statistic See merge request projectn/nemu!52
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
Kvm improve See merge request projectn/nemu!51
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由 Zihao Yu 提交于
* this helps to execute store instructions to mmio in compile mode
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
Fix x86 eflags See merge request projectn/nemu!50
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由 Zihao Yu 提交于
* this can directly compute most of the CC, include CC_E and CC_NE * for CC_S and CC_NS, we should re-compute the difference again
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由 Zihao Yu 提交于
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- 06 4月, 2020 4 次提交
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由 Zihao Yu 提交于
* need refactor
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由 Zihao Yu 提交于
* this can eliminate masking the result of subtraction with 0xff or 0xffff
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由 Zihao Yu 提交于
* Treating (dsrc1 + CF) as whole, which is introduced in 051786, is wrong. (dsrc1 + CF) may generate carry bit. Treating them as whole will miss such carry. * Also we should introduce a new rtl register s2 to compute the CF of adc/sbb.
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由 Zihao Yu 提交于
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- 05 4月, 2020 3 次提交
- 04 4月, 2020 6 次提交
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由 Zihao Yu 提交于
Kvm See merge request projectn/nemu!49
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
* x86 will clear eflags.TF after executing an INT instruction. This will disable single step after transferring to the interrupt handler. * To solve this, we snoopy for an INT instruction after every single step. If we find it, we compute the entry point and set it as a watchpoint in the debug register. The watchpoint will intercept the execution of interrupt handler, and we can enable single step again. * Another solution may be to set the Monitor Trap Flag (MTF) in the Virtual Machine Control Structure (VMCS). But it seems that KVM does not provide an API to access the VMCS.
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- 03 4月, 2020 1 次提交
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由 Zihao Yu 提交于
* when an interrupt is taken, it also needs to access GDT
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- 02 4月, 2020 6 次提交
- 31 3月, 2020 3 次提交