riscv64,mmu: add load/store misaligned exceptions to run x86-nemu on debian

src/isa/riscv64/intr.c

@@ -23,7 +23,12 @@ void raise_intr(word_t NO, vaddr_t epc) {
     mstatus->spp = cpu.mode;
     mstatus->spie = mstatus->sie;
     mstatus->sie = 0;
-    if (NO != EX_IPF && NO != EX_LPF && NO != EX_SPF) stval->val = 0;
+    switch (NO) {
+      case EX_IPF: case EX_LPF: case EX_SPF:
+      case EX_LAM: case EX_SAM:
+        break;
+      default: stval->val = 0;
+    }
     cpu.mode = MODE_S;
     rtl_li(&s0, stvec->val);
   } else {
@@ -32,7 +37,12 @@ void raise_intr(word_t NO, vaddr_t epc) {
     mstatus->mpp = cpu.mode;
     mstatus->mpie = mstatus->mie;
     mstatus->mie = 0;
-    if (NO != EX_IPF && NO != EX_LPF && NO != EX_SPF) mtval->val = 0;
+    switch (NO) {
+      case EX_IPF: case EX_LPF: case EX_SPF:
+      case EX_LAM: case EX_SAM:
+        break;
+      default: mtval->val = 0;
+    }
     cpu.mode = MODE_M;
     rtl_li(&s0, mtvec->val);
   }

src/isa/riscv64/mmu.c

@@ -2,6 +2,7 @@
 #include "memory/memory.h"
 #include "csr.h"
 #include "intr.h"
+#include "cpu/decode.h"
 
 typedef union PageTableEntry {
   struct {
@@ -116,6 +117,18 @@ static inline paddr_t page_translate(vaddr_t addr, bool is_write) {
 }
 
 word_t isa_vaddr_read(vaddr_t addr, int len) {
+  if (!cpu.fetching) {
+    if ((addr & (len - 1)) != 0) {
+      //Log("misalgined load addr = " FMT_WORD ", pc = " FMT_WORD", instr = %x",
+      //    addr, cpu.pc, decinfo.isa.instr.val);
+      mtval->val = addr;
+      if (cpu.amo) {
+        cpu.amo = false;
+        longjmp_raise_intr(EX_SAM);
+      }
+      longjmp_raise_intr(EX_LAM);
+    }
+  }
   paddr_t paddr = addr;
   uint32_t mode = (mstatus->mprv && !cpu.fetching ? mstatus->mpp : cpu.mode);
   if (mode < MODE_M) {
@@ -128,6 +141,13 @@ word_t isa_vaddr_read(vaddr_t addr, int len) {
 }
 
 void isa_vaddr_write(vaddr_t addr, word_t data, int len) {
+  if ((addr & (len - 1)) != 0) {
+    //Log("misalgined store addr = " FMT_WORD ", pc = " FMT_WORD", instr = %x",
+    //    addr, cpu.pc, decinfo.isa.instr.val);
+    if (cpu.amo) cpu.amo = false;
+    mtval->val = addr;
+    longjmp_raise_intr(EX_SAM);
+  }
   paddr_t paddr = addr;
   uint32_t mode = (mstatus->mprv && !cpu.fetching ? mstatus->mpp : cpu.mode);
   if (mode < MODE_M) {