riscv32: add interrupt

src/isa/riscv32/exec/system.c

@@ -3,7 +3,7 @@
 static inline rtlreg_t* csr_decode(uint32_t csr) {
   switch (csr) {
     case 0x180: return &cpu.satp.val;
-    case 0x100: return &cpu.sstatus;
+    case 0x100: return &cpu.sstatus.val;
     case 0x105: return &cpu.stvec;
     case 0x141: return &cpu.sepc;
     case 0x142: return &cpu.scause;
@@ -48,6 +48,8 @@ make_EHelper(priv) {
       print_asm("ecall");
       break;
     case 0x102:
+      cpu.sstatus.sie = cpu.sstatus.spie;
+      cpu.sstatus.spie = 1;
       rtl_li(&s0, cpu.sepc);
       rtl_jr(&s0);
       print_asm("sret");

src/isa/riscv32/include/isa/reg.h

@@ -17,7 +17,19 @@ typedef struct {
   vaddr_t stvec;
   vaddr_t scause;
   vaddr_t sepc;
-  vaddr_t sstatus;
+  union {
+    struct {
+      uint32_t uie : 1;
+      uint32_t sie : 1;
+      uint32_t pad0: 2;
+      uint32_t upie: 1;
+      uint32_t spie: 1;
+      uint32_t pad1: 2;
+      uint32_t spp : 1;
+      uint32_t dontcare :21;
+    };
+    uint32_t val;
+  } sstatus;
   union {
     struct {
       uint32_t ppn :22;

src/isa/riscv32/init.c

@@ -13,7 +13,7 @@ const long isa_default_img_size = sizeof(isa_default_img);
 void init_isa(void) {
   cpu.gpr[0]._32 = 0;
   cpu.pc = PC_START;
-  cpu.sstatus = 0x000c0100;
+  cpu.sstatus.val = 0x000c0100;
 
   register_pmem(0x80000000u);
 }

src/isa/riscv32/intr.c

@@ -7,10 +7,17 @@ void raise_intr(uint32_t NO, vaddr_t epc) {
 
   cpu.scause = NO;
   cpu.sepc = epc;
+  cpu.sstatus.spie = cpu.sstatus.sie;
+  cpu.sstatus.sie = 0;
   rtl_li(&s0, cpu.stvec);
   rtl_jr(&s0);
 }
 
 bool isa_query_intr(void) {
+  if (cpu.INTR && cpu.sstatus.sie) {
+    cpu.INTR = false;
+    raise_intr(0x80000005, cpu.pc);
+    return true;
+  }
   return false;
 }