riscv64,exec: pass all cputests

src/isa/riscv64/decode.c

@@ -193,19 +193,24 @@ make_DHelper(C_LWSP) {
   decinfo.width = 4;
 }
 
-static void decode_C_xxx_imm_rd(bool is_rs1_zero) {
-  decode_op_r(id_src, (is_rs1_zero ? 0 : decinfo.isa.instr.c_rd_rs1), true);
+static void decode_C_xxx_imm_rd(bool is_rs1_zero, bool is_reg_compress) {
+  int reg = (is_reg_compress ? creg2reg(decinfo.isa.instr.c_rd_rs1_) : decinfo.isa.instr.c_rd_rs1);
+  decode_op_r(id_src, (is_rs1_zero ? 0 : reg), true);
   sword_t simm = (decinfo.isa.instr.c_simm12 << 5) | decinfo.isa.instr.c_imm6_2;
   decode_op_i(id_src2, simm, true);
-  decode_op_r(id_dest, decinfo.isa.instr.c_rd_rs1, false);
+  decode_op_r(id_dest, reg, false);
 }
 
 make_DHelper(C_0_imm_rd) {
-  decode_C_xxx_imm_rd(true);
+  decode_C_xxx_imm_rd(true, false);
 }
 
 make_DHelper(C_rs1_imm_rd) {
-  decode_C_xxx_imm_rd(false);
+  decode_C_xxx_imm_rd(false, false);
+}
+
+make_DHelper(C_rs1__imm_rd_) {
+  decode_C_xxx_imm_rd(false, true);
 }
 
 static void decode_C_xxx_xxx_xxx(bool is_rs1_zero, bool is_rs2_zero, bool is_rd_zero) {
@@ -239,6 +244,21 @@ make_DHelper(C_ADDI16SP) {
   decode_op_r(id_dest, 2, false);
 }
 
+make_DHelper(C_SW) {
+  decode_op_r(id_src, creg2reg(decinfo.isa.instr.c_rd_rs1_), true);
+  uint32_t imm6 = ((decinfo.isa.instr.c_imm6_5) & 0x1);
+  uint32_t imm5_3 = decinfo.isa.instr.c_imm12_10;
+  uint32_t imm2 = ((decinfo.isa.instr.c_imm6_5 >> 1) & 0x1);
+  word_t imm = (imm6 << 6) | (imm5_3 << 3) | (imm2 << 2);
+  decode_op_i(id_src2, imm, true);
+
+  rtl_add(&id_src->addr, &id_src->val, &id_src2->val);
+
+  decode_op_r(id_dest, creg2reg(decinfo.isa.instr.c_rs2_), true);
+
+  decinfo.width = 4;
+}
+
 make_DHelper(C_LW) {
   decode_op_r(id_src, creg2reg(decinfo.isa.instr.c_rd_rs1_), true);
   uint32_t imm6 = ((decinfo.isa.instr.c_imm6_5) & 0x1);
@@ -254,7 +274,50 @@ make_DHelper(C_LW) {
   decinfo.width = 4;
 }
 
+make_DHelper(C_SD) {
+  decode_op_r(id_src, creg2reg(decinfo.isa.instr.c_rd_rs1_), true);
+  uint32_t imm7_6 = decinfo.isa.instr.c_imm6_5;
+  uint32_t imm5_3 = decinfo.isa.instr.c_imm12_10;
+  word_t imm = (imm7_6 << 6) | (imm5_3 << 3);
+  decode_op_i(id_src2, imm, true);
+
+  rtl_add(&id_src->addr, &id_src->val, &id_src2->val);
+
+  decode_op_r(id_dest, creg2reg(decinfo.isa.instr.c_rs2_), true);
+
+  decinfo.width = 8;
+}
+
+make_DHelper(C_LD) {
+  decode_op_r(id_src, creg2reg(decinfo.isa.instr.c_rd_rs1_), true);
+  uint32_t imm7_6 = decinfo.isa.instr.c_imm6_5;
+  uint32_t imm5_3 = decinfo.isa.instr.c_imm12_10;
+  word_t imm = (imm7_6 << 6) | (imm5_3 << 3);
+  decode_op_i(id_src2, imm, true);
+
+  rtl_add(&id_src->addr, &id_src->val, &id_src2->val);
+
+  decode_op_r(id_dest, creg2reg(decinfo.isa.instr.c_rd_), false);
+
+  decinfo.width = 8;
+}
+
 make_DHelper(C_J) {
   decode_CJ(pc);
   decode_op_r(id_dest, 0, false);
 }
+
+make_DHelper(C_JALR) {
+  decode_op_r(id_src, decinfo.isa.instr.c_rd_rs1, true);
+  decode_op_r(id_src2, 0, true);
+  decode_op_r(id_dest, 1, false);
+}
+
+make_DHelper(C_ADDI4SPN) {
+  decode_op_r(id_src, 2, true);
+  word_t imm = (decinfo.isa.instr.c_imm9_6 << 6) | (decinfo.isa.instr.c_imm5_4 << 4) |
+    (decinfo.isa.instr.c_imm3 << 3) | (decinfo.isa.instr.c_imm2 << 2);
+  assert(imm != 0);
+  decode_op_i(id_src2, imm, true);
+  decode_op_r(id_dest, creg2reg(decinfo.isa.instr.c_rd_), false);
+}

src/isa/riscv64/exec/control.c

 #include "cpu/exec.h"
 
 make_EHelper(jal) {
-  rtl_addi(&s0, &cpu.pc, 4);
+  rtl_li(&s0, decinfo.seq_pc);
   rtl_sr(id_dest->reg, &s0, 4);
   rtl_j(decinfo.jmp_pc);
 
@@ -9,7 +9,7 @@ make_EHelper(jal) {
 }
 
 make_EHelper(jalr) {
-  rtl_addi(&s0, &cpu.pc, 4);
+  rtl_li(&s0, decinfo.seq_pc);
   rtl_sr(id_dest->reg, &s0, 4);
 
   rtl_add(&s0, &id_src->val, &id_src2->val);

src/isa/riscv64/exec/exec.c

@@ -75,7 +75,7 @@ static OpcodeEntry opcode_table [32] = {
 
 static make_EHelper(C_10_100) {
   static OpcodeEntry table [8] = {
-    EMPTY, EMPTY, IDEX(C_rs1_rs2_0, jalr), IDEX(C_0_rs2_rd, add), EMPTY, EMPTY, EMPTY, IDEX(C_rs1_rs2_rd, add),
+    EMPTY, EMPTY, IDEX(C_rs1_rs2_0, jalr), IDEX(C_0_rs2_rd, add), EMPTY, EMPTY, IDEX(C_JALR, jalr), IDEX(C_rs1_rs2_rd, add),
   };
   uint32_t cond_c_simm12_not0 = (decinfo.isa.instr.c_simm12 != 0);
   uint32_t cond_c_rd_rs1_not0 = (decinfo.isa.instr.c_rd_rs1 != 0);
@@ -93,29 +93,29 @@ static make_EHelper(C_01_011) {
 }
 
 static make_EHelper(C_01_100) {
-  int func = decinfo.isa.instr.c_func6 & 0x3;
-  switch (func) {
-    case 3: {
-      decode_CR(pc);
-      static OpcodeEntry table [8] = {
-        EX(sub), EMPTY, EMPTY, EMPTY, EMPTY, EX(addw), EMPTY, EMPTY,
-      };
-
-      uint32_t idx2 = (decinfo.isa.instr.c_func6 >> 2) & 0x1;
-      uint32_t idx1_0 = decinfo.isa.instr.c_func2;
-      uint32_t idx = (idx2 << 2) | idx1_0;
-      assert(idx < 8);
-      idex(pc, &table[idx]);
-      break;
-    }
-    default: assert(0);
+  uint32_t func = decinfo.isa.instr.c_func6 & 0x3;
+  if (func == 3) {
+    decode_CR(pc);
+    static OpcodeEntry table [8] = {
+      EX(sub), EMPTY, EX(or), EX(and), EX(subw), EX(addw), EMPTY, EMPTY,
+    };
+
+    uint32_t idx2 = (decinfo.isa.instr.c_func6 >> 2) & 0x1;
+    uint32_t idx1_0 = decinfo.isa.instr.c_func2;
+    uint32_t idx = (idx2 << 2) | idx1_0;
+    assert(idx < 8);
+    idex(pc, &table[idx]);
+  } else {
+    decode_C_rs1__imm_rd_(pc);
+    static OpcodeEntry table [3] = { EX(srl), EMPTY, EX(and) };
+    idex(pc, &table[func]);
   }
 }
 
 static OpcodeEntry rvc_table [3][8] = {
-  {EMPTY, EMPTY, IDEX(C_LW, lds), EMPTY, EMPTY, EMPTY, EMPTY, EMPTY, },
-  {IDEX(C_rs1_imm_rd, add), IDEX(C_rs1_imm_rd, addw), IDEX(C_0_imm_rd, add), EX(C_01_011), EX(C_01_100), IDEX(C_J, jal), IDEX(CB, beq), IDEX(CB, bne), },
-  {EMPTY, EMPTY, IDEX(C_LWSP, lds), IDEX(C_LDSP, ld), EX(C_10_100), EMPTY, IDEX(C_SWSP, st), IDEX(C_SDSP, st), },
+  {IDEX(C_ADDI4SPN, add), EMPTY, IDEX(C_LW, lds), IDEX(C_LD, ld), EMPTY, EMPTY, IDEX(C_SW, st), IDEX(C_SD, st)},
+  {IDEX(C_rs1_imm_rd, add), IDEX(C_rs1_imm_rd, addw), IDEX(C_0_imm_rd, add), EX(C_01_011), EX(C_01_100), IDEX(C_J, jal), IDEX(CB, beq), IDEX(CB, bne)},
+  {IDEX(C_rs1_imm_rd, sll), EMPTY, IDEX(C_LWSP, lds), IDEX(C_LDSP, ld), EX(C_10_100), EMPTY, IDEX(C_SWSP, st), IDEX(C_SDSP, st)}
 };
 
 void isa_exec(vaddr_t *pc) {

src/isa/riscv64/include/isa/decode.h

@@ -119,11 +119,18 @@ make_DHelper(C_LDSP);
 make_DHelper(C_LWSP);
 make_DHelper(C_0_imm_rd);
 make_DHelper(C_rs1_imm_rd);
+make_DHelper(C_rs1__imm_rd_);
 make_DHelper(C_0_rs2_rd);
 make_DHelper(C_rs1_rs2_0);
 make_DHelper(C_rs1_rs2_rd);
 make_DHelper(C_ADDI16SP);
 make_DHelper(C_LW);
+make_DHelper(C_SW);
+make_DHelper(C_LD);
+make_DHelper(C_SD);
 make_DHelper(C_J);
+make_DHelper(C_JALR);
+
+make_DHelper(C_ADDI4SPN);
 
 #endif