engine,rv64: define tmp_reg as enum

src/engine/rv64/isa/mips32.c

@@ -5,7 +5,6 @@
 #include <isa.h>
 #include <isa/riscv64.h>
 #include "../tran.h"
-#include "../spill.h"
 
 uint32_t rtlreg2varidx(DecodeExecState *s, const rtlreg_t* dest) {
   rtlreg_t* gpr_start = (rtlreg_t *)cpu.gpr;
@@ -16,8 +15,8 @@ uint32_t rtlreg2varidx(DecodeExecState *s, const rtlreg_t* dest) {
     switch (rvidx) {
       case tmp0:         return 1 | SPMIDX_MASK; break;   // fixed to tmp0
       case spm_base:     return 2 | SPMIDX_MASK; break;   // used to store sratchpad addr
-      case TMP_REG_1:    return 3 | SPMIDX_MASK; break;   // tmp_reg 1
-      case TMP_REG_2:    return 4 | SPMIDX_MASK; break;   // tmp_reg 2
+      case tmp_reg1:     return 3 | SPMIDX_MASK; break;   // tmp_reg 1
+      case tmp_reg2:     return 4 | SPMIDX_MASK; break;   // tmp_reg 2
       case mask32:       return 5 | SPMIDX_MASK; break;   // fixed to mask32
       default: return rvidx;
     }
@@ -40,7 +39,7 @@ void guest_getregs(CPU_state *mips32) {
   int i;
   for (i = 0; i < 32; i ++) {
     switch (i) {
-      case tmp0: case mask32: case spm_base: case TMP_REG_1: case TMP_REG_2: continue;
+      case tmp0: case mask32: case spm_base: case tmp_reg1: case tmp_reg2: continue;
     }
     mips32->gpr[i]._32 = r.gpr[i]._64;
   }
@@ -55,7 +54,7 @@ void guest_setregs(const CPU_state *mips32) {
   int i;
   for (i = 0; i < 32; i ++) {
     switch (i) {
-      case tmp0: case mask32: case spm_base: case TMP_REG_1: case TMP_REG_2: continue;
+      case tmp0: case mask32: case spm_base: case tmp_reg1: case tmp_reg2: continue;
     }
     r.gpr[i]._64 = mips32->gpr[i]._32;
   }

src/engine/rv64/spill.c

@@ -3,6 +3,8 @@
 #include "rv64-backend/rv_ins_def.h"
 #include "rtl/rtl.h"
 
+#define TMP_REG_NUM 2
+
 typedef struct {
   uint32_t rvidx;
   uint32_t spmidx;
@@ -12,8 +14,8 @@ static Tmp_reg tmp_regs[TMP_REG_NUM];
 
 void spill_init() {
   assert(TMP_REG_NUM == 2);
-  tmp_regs[0].rvidx = TMP_REG_1;
-  tmp_regs[1].rvidx = TMP_REG_2;
+  tmp_regs[0].rvidx = tmp_reg1;
+  tmp_regs[1].rvidx = tmp_reg2;
 }
 
 void spill_flush(int tmpidx) {

src/engine/rv64/spill.h

@@ -4,12 +4,6 @@
 #include <common.h>
 #include <cpu/decode.h>
 
-// Temp GPR Registers Setting (can set any registers but $0, $1, $28)
-// default is $26, $27, which has low perf loss
-#define TMP_REG_1     26
-#define TMP_REG_2     27
-#define TMP_REG_NUM 2
-
 uint32_t spmidx2rvidx(uint32_t);
 uint32_t spill_out_and_remap(DecodeExecState*, uint32_t);
 void spill_flush_all();

src/engine/rv64/tran.h

@@ -31,12 +31,12 @@ enum { x0 = 0 };
 
 // static register allocation
 #if defined(__ISA_x86__)
-enum { tmp0 = 30, mask32 = 24, mask16 = 25, spm_base = 0 };
+enum { tmp0 = 30, mask32 = 24, mask16 = 25, spm_base = 0, tmp_reg1 = 0, tmp_reg2 = 0 };
 #elif defined(__ISA_mips32__)
-enum { tmp0 = 1, mask32 = 28, mask16 = 0, spm_base = 25 };
+enum { tmp0 = 1, mask32 = 28, mask16 = 0, spm_base = 25, tmp_reg1 = 26, tmp_reg2 = 27 };
 #define REG_SPILLING
 #elif defined(__ISA_riscv32__)
-enum { tmp0 = 3, mask32 = 4, mask16 = 0, spm_base = 0 };
+enum { tmp0 = 3, mask32 = 4, mask16 = 0, spm_base = 0, tmp_reg1 = 0, tmp_reg2 = 0 };
 //#define REG_SPILLING
 #endif