Merge branch 'xs' of https://github.com/RISCVERS/NEMU into xs

src/isa/riscv64/mmu.c

@@ -114,7 +114,32 @@ static paddr_t ptw(vaddr_t vaddr, int type) {
 }
 
 int isa_vaddr_check(vaddr_t vaddr, int type, int len) {
+
   bool ifetch = (type == MEM_TYPE_IFETCH);
+
+  // riscv-privileged 4.4.1: Addressing and Memory Protection: 
+  // Instruction fetch addresses and load and store effective addresses, 
+  // which are 64 bits, must have bits 63–39 all equal to bit 38, or else a page-fault exception will occur.
+  word_t va_mask = ((((word_t)1) << (63 - 39 + 1)) - 1);
+  word_t va_msbs = vaddr >> 39;
+  bool va_msbs_ok = (va_msbs == va_mask) || va_msbs == 0;
+  if(!va_msbs_ok){
+    if(ifetch){
+      stval->val = vaddr;
+      cpu.mem_exception = EX_IAF;
+    } else if(type == MEM_TYPE_READ){
+      if (cpu.mode == MODE_M) mtval->val = vaddr;
+      else stval->val = vaddr;
+      cpu.mem_exception = (cpu.amo ? EX_SAF : EX_LAF);
+    } else {
+      if (cpu.mode == MODE_M) mtval->val = vaddr;
+      else stval->val = vaddr;
+      cpu.mem_exception = EX_SAF;
+    }
+    return MEM_RET_FAIL;
+  }
+
+  
   if ((!ifetch) && (vaddr & (len - 1)) != 0) {
     mtval->val = vaddr;
     cpu.mem_exception = (cpu.amo || type == MEM_TYPE_WRITE ? EX_SAM : EX_LAM);