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提交 804e3967 编写于 作者: Nameless-Y's avatar Nameless-Y
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[bsp][stm32/libraries] update STM32G0xx_HAL lib to V1.3.0

上级 0cde9a27
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Showing with 6055 addition and 4395 deletion
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g030xx.h
浏览文件 @ 804e3967
......@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
......@@ -22,7 +22,7 @@
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
******************************************************************************
*/
/** @addtogroup CMSIS_Device
......@@ -95,7 +95,7 @@ typedef enum
TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
I2C2_IRQn = 24, /*!< I2C2 Interrupt */
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */
SPI2_IRQn = 26, /*!< SPI2 Interrupt */
USART1_IRQn = 27, /*!< USART1 Interrupt */
USART2_IRQn = 28, /*!< USART2 Interrupt */
......@@ -146,6 +146,7 @@ typedef struct
/**
* @brief CRC calculation unit
*/
......@@ -517,7 +518,6 @@ typedef struct
#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */
/*!< Peripheral memory map */
......@@ -577,7 +577,6 @@ typedef struct
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC)
/*!< IOPORT */
#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
......@@ -618,7 +617,6 @@ typedef struct
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
......@@ -637,7 +635,6 @@ typedef struct
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
......@@ -652,7 +649,6 @@ typedef struct
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE)
#define DBG ((DBG_TypeDef *) DBG_BASE)
......@@ -1280,9 +1276,10 @@ typedef struct
#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
/* Legacy */
#define ADC_CCR_LFMEN_Pos (25U)
#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */
/******************************************************************************/
......@@ -1728,27 +1725,6 @@ typedef struct
#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */
/***************** Bits definition for DMAMUX_IPHW_CFGR2 register ************/
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos (0U)
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources */
/***************** Bits definition for DMAMUX_IPHW_CFGR1 register ************/
#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos (0U)
#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */
#define DMAMUX_IPHW_CFGR1_NB_STREAMS DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams */
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos (8U)
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests */
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos (16U)
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos (24U)
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks */
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
......@@ -2264,7 +2240,6 @@ typedef struct
#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
/******************************************************************************/
/* */
/* FLASH */
......@@ -3864,6 +3839,7 @@ typedef struct
#define PWR_PUCRD_PU3_Pos (3U)
#define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) /*!< 0x00000008 */
#define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk /*!< Pin PD3 Pull-Up set */
/******************** Bit definition for PWR_PDCRD register *****************/
#define PWR_PDCRD_PD0_Pos (0U)
#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
......@@ -4347,10 +4323,10 @@ typedef struct
#define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
#define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk
#define RCC_APBSMENR1_WWDGSMEN_Pos (11U)
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk
#define RCC_APBSMENR1_SPI2SMEN_Pos (14U)
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk
#define RCC_APBSMENR1_USART2SMEN_Pos (17U)
#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
......@@ -5070,7 +5046,6 @@ typedef struct
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
......@@ -5242,7 +5217,6 @@ typedef struct
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
......@@ -6934,7 +6908,6 @@ typedef struct
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* Window WATCHDOG */
......@@ -7074,7 +7047,6 @@ typedef struct
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOF))
/******************************* GPIO AF Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
......@@ -7100,6 +7072,7 @@ typedef struct
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2))
/******************************** SPI Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
......@@ -7295,7 +7268,9 @@ typedef struct
((INSTANCE) == TIM3))
/******************* TIM Instances : Timer input selection ********************/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM14) || \
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM14) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g031xx.h
浏览文件 @ 804e3967
......@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
......@@ -22,7 +22,7 @@
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
******************************************************************************
*/
/** @addtogroup CMSIS_Device
......@@ -99,7 +99,7 @@ typedef enum
TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
I2C2_IRQn = 24, /*!< I2C2 Interrupt */
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */
SPI2_IRQn = 26, /*!< SPI2 Interrupt */
USART1_IRQn = 27, /*!< USART1 Interrupt */
USART2_IRQn = 28, /*!< USART2 Interrupt */
......@@ -151,6 +151,7 @@ typedef struct
/**
* @brief CRC calculation unit
*/
......@@ -550,7 +551,6 @@ typedef struct
#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */
/*!< Peripheral memory map */
......@@ -615,7 +615,6 @@ typedef struct
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC)
/*!< IOPORT */
#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
......@@ -661,7 +660,6 @@ typedef struct
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
......@@ -680,7 +678,6 @@ typedef struct
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
......@@ -695,7 +692,6 @@ typedef struct
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE)
#define DBG ((DBG_TypeDef *) DBG_BASE)
......@@ -1323,9 +1319,10 @@ typedef struct
#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
/* Legacy */
#define ADC_CCR_LFMEN_Pos (25U)
#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */
/******************************************************************************/
......@@ -1771,27 +1768,6 @@ typedef struct
#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */
/***************** Bits definition for DMAMUX_IPHW_CFGR2 register ************/
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos (0U)
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources */
/***************** Bits definition for DMAMUX_IPHW_CFGR1 register ************/
#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos (0U)
#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */
#define DMAMUX_IPHW_CFGR1_NB_STREAMS DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams */
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos (8U)
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests */
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos (16U)
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos (24U)
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks */
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
......@@ -2346,7 +2322,6 @@ typedef struct
#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
/******************************************************************************/
/* */
/* FLASH */
......@@ -4041,6 +4016,7 @@ typedef struct
#define PWR_PUCRD_PU3_Pos (3U)
#define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) /*!< 0x00000008 */
#define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk /*!< Pin PD3 Pull-Up set */
/******************** Bit definition for PWR_PDCRD register *****************/
#define PWR_PDCRD_PD0_Pos (0U)
#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
......@@ -4562,10 +4538,10 @@ typedef struct
#define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
#define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk
#define RCC_APBSMENR1_WWDGSMEN_Pos (11U)
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk
#define RCC_APBSMENR1_SPI2SMEN_Pos (14U)
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk
#define RCC_APBSMENR1_USART2SMEN_Pos (17U)
#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
......@@ -5314,7 +5290,6 @@ typedef struct
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
......@@ -5486,7 +5461,6 @@ typedef struct
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
......@@ -7395,7 +7369,6 @@ typedef struct
#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* VREFBUF */
......@@ -7568,7 +7541,6 @@ typedef struct
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOF))
/******************************* GPIO AF Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
......@@ -7594,6 +7566,7 @@ typedef struct
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2))
/******************************** SPI Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
......@@ -7840,7 +7813,6 @@ typedef struct
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g041xx.h
浏览文件 @ 804e3967
......@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
......@@ -22,7 +22,7 @@
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
******************************************************************************
*/
/** @addtogroup CMSIS_Device
......@@ -99,7 +99,7 @@ typedef enum
TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
I2C2_IRQn = 24, /*!< I2C2 Interrupt */
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */
SPI2_IRQn = 26, /*!< SPI2 Interrupt */
USART1_IRQn = 27, /*!< USART1 Interrupt */
USART2_IRQn = 28, /*!< USART2 Interrupt */
......@@ -152,6 +152,7 @@ typedef struct
/**
* @brief CRC calculation unit
*/
......@@ -592,7 +593,6 @@ typedef struct
#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */
/*!< Peripheral memory map */
......@@ -659,7 +659,6 @@ typedef struct
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC)
/*!< IOPORT */
#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
......@@ -705,7 +704,6 @@ typedef struct
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
......@@ -727,7 +725,6 @@ typedef struct
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
......@@ -742,7 +739,6 @@ typedef struct
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE)
#define DBG ((DBG_TypeDef *) DBG_BASE)
......@@ -1370,9 +1366,10 @@ typedef struct
#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
/* Legacy */
#define ADC_CCR_LFMEN_Pos (25U)
#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */
/******************************************************************************/
......@@ -2007,27 +2004,6 @@ typedef struct
#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */
/***************** Bits definition for DMAMUX_IPHW_CFGR2 register ************/
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos (0U)
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Pos) /*!< 0x000000FF */
#define DMAMUX_IPHW_CFGR2_NB_EXT_REQ DMAMUX_IPHW_CFGR2_NB_EXT_REQ_Msk /*!< Number of external request sources */
/***************** Bits definition for DMAMUX_IPHW_CFGR1 register ************/
#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos (0U)
#define DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_STREAMS_Pos) /*!< 0x000000FF */
#define DMAMUX_IPHW_CFGR1_NB_STREAMS DMAMUX_IPHW_CFGR1_NB_STREAMS_Msk /*!< Number of DMA streams */
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos (8U)
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Pos) /*!< 0x0000FF00 */
#define DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ DMAMUX_IPHW_CFGR1_NB_PERIPH_REQ_Msk /*!< Number of peripheral requests */
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos (16U)
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Pos) /*!< 0x00FF0000 */
#define DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG DMAMUX_IPHW_CFGR1_NB_SYNC_TRIG_Msk /*!< Number of synchronization triggers */
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos (24U)
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk (0xFFUL << DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Pos) /*!< 0xFF000000 */
#define DMAMUX_IPHW_CFGR1_NB_REQ_GEN DMAMUX_IPHW_CFGR1_NB_REQ_GEN_Msk /*!< Number of request generation blocks */
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
......@@ -2582,7 +2558,6 @@ typedef struct
#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
/******************************************************************************/
/* */
/* FLASH */
......@@ -4277,6 +4252,7 @@ typedef struct
#define PWR_PUCRD_PU3_Pos (3U)
#define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) /*!< 0x00000008 */
#define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk /*!< Pin PD3 Pull-Up set */
/******************** Bit definition for PWR_PDCRD register *****************/
#define PWR_PDCRD_PD0_Pos (0U)
#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
......@@ -4816,10 +4792,10 @@ typedef struct
#define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
#define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk
#define RCC_APBSMENR1_WWDGSMEN_Pos (11U)
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk
#define RCC_APBSMENR1_SPI2SMEN_Pos (14U)
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk
#define RCC_APBSMENR1_USART2SMEN_Pos (17U)
#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
......@@ -5612,7 +5588,6 @@ typedef struct
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
......@@ -5784,7 +5759,6 @@ typedef struct
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
......@@ -7699,7 +7673,6 @@ typedef struct
#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* VREFBUF */
......@@ -7874,7 +7847,6 @@ typedef struct
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOF))
/******************************* GPIO AF Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
......@@ -7902,6 +7874,7 @@ typedef struct
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2))
/******************************** SPI Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
......@@ -8148,7 +8121,6 @@ typedef struct
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g070xx.h
浏览文件 @ 804e3967
......@@ -22,7 +22,7 @@
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
******************************************************************************
*/
/** @addtogroup CMSIS_Device
......@@ -98,7 +98,7 @@ typedef enum
TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
I2C2_IRQn = 24, /*!< I2C2 Interrupt */
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */
SPI2_IRQn = 26, /*!< SPI2 Interrupt */
USART1_IRQn = 27, /*!< USART1 Interrupt */
USART2_IRQn = 28, /*!< USART2 Interrupt */
......@@ -150,6 +150,7 @@ typedef struct
/**
* @brief CRC calculation unit
*/
......@@ -521,7 +522,6 @@ typedef struct
#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
#define SRAM_SIZE_MAX (0x00008000UL) /*!< maximum SRAM size (up to 32 KBytes) */
/*!< Peripheral memory map */
......@@ -590,7 +590,6 @@ typedef struct
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC)
/*!< IOPORT */
#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
......@@ -636,7 +635,6 @@ typedef struct
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
......@@ -657,7 +655,6 @@ typedef struct
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
......@@ -674,7 +671,6 @@ typedef struct
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE)
#define DBG ((DBG_TypeDef *) DBG_BASE)
......@@ -1302,9 +1298,10 @@ typedef struct
#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
/* Legacy */
#define ADC_CCR_LFMEN_Pos (25U)
#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */
/******************************************************************************/
......@@ -2265,7 +2262,6 @@ typedef struct
#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
/******************************************************************************/
/* */
/* FLASH */
......@@ -4505,10 +4501,10 @@ typedef struct
#define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
#define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk
#define RCC_APBSMENR1_WWDGSMEN_Pos (11U)
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk
#define RCC_APBSMENR1_SPI2SMEN_Pos (14U)
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk
#define RCC_APBSMENR1_USART2SMEN_Pos (17U)
#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
......@@ -5242,7 +5238,6 @@ typedef struct
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
......@@ -5414,7 +5409,6 @@ typedef struct
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
......@@ -7128,7 +7122,6 @@ typedef struct
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* Window WATCHDOG */
......@@ -7280,7 +7273,6 @@ typedef struct
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOF))
/******************************* GPIO AF Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
......@@ -7306,6 +7298,7 @@ typedef struct
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2))
/******************************** SPI Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
......@@ -7532,7 +7525,9 @@ typedef struct
((INSTANCE) == TIM15))
/******************* TIM Instances : Timer input selection ********************/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM14) || \
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM14) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g071xx.h
浏览文件 @ 804e3967
......@@ -22,7 +22,7 @@
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
******************************************************************************
*/
/** @addtogroup CMSIS_Device
......@@ -101,7 +101,7 @@ typedef enum
TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
I2C2_IRQn = 24, /*!< I2C2 Interrupt */
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */
SPI2_IRQn = 26, /*!< SPI2 Interrupt */
USART1_IRQn = 27, /*!< USART1 Interrupt */
USART2_IRQn = 28, /*!< USART2 Interrupt */
......@@ -152,6 +152,7 @@ typedef struct
__IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
} ADC_Common_TypeDef;
/**
* @brief HDMI-CEC
*/
......@@ -633,7 +634,6 @@ typedef struct
#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
#define SRAM_SIZE_MAX (0x00008000UL) /*!< maximum SRAM size (up to 32 KBytes) */
/*!< Peripheral memory map */
......@@ -714,7 +714,6 @@ typedef struct
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC)
/*!< IOPORT */
#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
......@@ -771,7 +770,6 @@ typedef struct
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
......@@ -794,7 +792,6 @@ typedef struct
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
......@@ -811,7 +808,6 @@ typedef struct
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE)
#define DBG ((DBG_TypeDef *) DBG_BASE)
......@@ -1439,9 +1435,10 @@ typedef struct
#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
/* Legacy */
#define ADC_CCR_LFMEN_Pos (25U)
#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */
/******************************************************************************/
/* */
......@@ -2868,7 +2865,6 @@ typedef struct
#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
/******************************************************************************/
/* */
/* FLASH */
......@@ -5265,10 +5261,10 @@ typedef struct
#define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
#define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk
#define RCC_APBSMENR1_WWDGSMEN_Pos (11U)
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk
#define RCC_APBSMENR1_SPI2SMEN_Pos (14U)
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk
#define RCC_APBSMENR1_USART2SMEN_Pos (17U)
#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
......@@ -6049,7 +6045,6 @@ typedef struct
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
......@@ -6221,7 +6216,6 @@ typedef struct
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
......@@ -8233,7 +8227,6 @@ typedef struct
#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* VREFBUF */
......@@ -8750,7 +8743,6 @@ typedef struct
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOF))
/******************************* GPIO AF Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
......@@ -8776,6 +8768,7 @@ typedef struct
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2))
/******************************** SPI Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
......@@ -9055,7 +9048,6 @@ typedef struct
((INSTANCE) == USART3) || \
((INSTANCE) == USART4))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g081xx.h
浏览文件 @ 804e3967
......@@ -22,7 +22,7 @@
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
******************************************************************************
*/
/** @addtogroup CMSIS_Device
......@@ -101,7 +101,7 @@ typedef enum
TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
I2C2_IRQn = 24, /*!< I2C2 Interrupt */
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */
SPI2_IRQn = 26, /*!< SPI2 Interrupt */
USART1_IRQn = 27, /*!< USART1 Interrupt */
USART2_IRQn = 28, /*!< USART2 Interrupt */
......@@ -153,6 +153,7 @@ typedef struct
__IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
} ADC_Common_TypeDef;
/**
* @brief HDMI-CEC
*/
......@@ -675,7 +676,6 @@ typedef struct
#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
#define SRAM_SIZE_MAX (0x00008000UL) /*!< maximum SRAM size (up to 32 KBytes) */
/*!< Peripheral memory map */
......@@ -758,7 +758,6 @@ typedef struct
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
#define DMAMUX1_IdRegisters_BASE (DMAMUX1_BASE + 0x000003EC)
/*!< IOPORT */
#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
......@@ -815,7 +814,6 @@ typedef struct
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
......@@ -841,7 +839,6 @@ typedef struct
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
......@@ -858,7 +855,6 @@ typedef struct
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define DMAMUX1_IdRegisters ((DMAMUX_IdRegisters_TypeDef *) DMAMUX1_IdRegisters_BASE)
#define DBG ((DBG_TypeDef *) DBG_BASE)
......@@ -1486,9 +1482,10 @@ typedef struct
#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
/* Legacy */
#define ADC_CCR_LFMEN_Pos (25U)
#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< ADC common clock low frequency mode */
#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */
/******************************************************************************/
/* */
......@@ -3104,7 +3101,6 @@ typedef struct
#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
/******************************************************************************/
/* */
/* FLASH */
......@@ -5519,10 +5515,10 @@ typedef struct
#define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
#define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk
#define RCC_APBSMENR1_WWDGSMEN_Pos (11U)
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
#define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk
#define RCC_APBSMENR1_SPI2SMEN_Pos (14U)
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
#define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk
#define RCC_APBSMENR1_USART2SMEN_Pos (17U)
#define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
......@@ -6347,7 +6343,6 @@ typedef struct
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
......@@ -6519,7 +6514,6 @@ typedef struct
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
......@@ -8537,7 +8531,6 @@ typedef struct
#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* VREFBUF */
......@@ -9056,7 +9049,6 @@ typedef struct
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOF))
/******************************* GPIO AF Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
......@@ -9084,6 +9076,7 @@ typedef struct
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2))
/******************************** SPI Instances *******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
......@@ -9363,7 +9356,6 @@ typedef struct
((INSTANCE) == USART3) || \
((INSTANCE) == USART4))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Include/stm32g0xx.h
浏览文件 @ 804e3967
......@@ -57,10 +57,13 @@
application
*/
#if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx)
#if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) && !defined (STM32G030xx) && !defined (STM32G031xx) && !defined (STM32G041xx)
/* #define STM32G070xx */ /*!< STM32G070xx Devices */
/* #define STM32G071xx */ /*!< STM32G071xx Devices */
/* #define STM32G081xx */ /*!< STM32G081xx Devices */
/* #define STM32G030xx */ /*!< STM32G030xx Devices */
/* #define STM32G031xx */ /*!< STM32G031xx Devices */
/* #define STM32G041xx */ /*!< STM32G041xx Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
......@@ -79,7 +82,7 @@
* @brief CMSIS Device version number $VERSION$
*/
#define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32G0_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
#define __STM32G0_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
#define __STM32G0_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\
......@@ -101,6 +104,12 @@
#include "stm32g081xx.h"
#elif defined(STM32G070xx)
#include "stm32g070xx.h"
#elif defined(STM32G031xx)
#include "stm32g031xx.h"
#elif defined(STM32G041xx)
#include "stm32g041xx.h"
#elif defined(STM32G030xx)
#include "stm32g030xx.h"
#else
#error "Please select first the target STM32G0xx device used in your application (in stm32g0xx.h file)"
#endif
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g030xx.s
浏览文件 @ 804e3967
......@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g031xx.s
浏览文件 @ 804e3967
......@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g041xx.s
浏览文件 @ 804e3967
......@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g070xx.s
浏览文件 @ 804e3967
......@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2018 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g071xx.s
浏览文件 @ 804e3967
......@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2018 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/arm/startup_stm32g081xx.s
浏览文件 @ 804e3967
......@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2018 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g030xx.s
浏览文件 @ 804e3967
......@@ -2,7 +2,7 @@
******************************************************************************
* @file startup_stm32g030xx.s
* @author MCD Application Team
* @brief STM32G030xx devices vector table for Atollic TrueSTUDIO toolchain.
* @brief STM32G030xx devices vector table for SW4STM32 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
......@@ -14,8 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2019 STMicroelectronics. All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
......@@ -85,9 +84,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bl entry
LoopForever:
b LoopForever
......@@ -218,8 +217,8 @@ g_pfnVectors:
.weak DMA1_Channel2_3_IRQHandler
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
.weak DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
.thumb_set DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler,Default_Handler
.weak DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler
.thumb_set DMA1_Ch4_5_DMAMUX1_OVR_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g031xx.s
浏览文件 @ 804e3967
......@@ -2,7 +2,7 @@
******************************************************************************
* @file startup_stm32g031xx.s
* @author MCD Application Team
* @brief STM32G031xx devices vector table for Atollic TrueSTUDIO toolchain.
* @brief STM32G031xx devices vector table for SW4STM32 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
......@@ -14,8 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2019 STMicroelectronics. All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
......@@ -85,9 +84,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bl entry
LoopForever:
b LoopForever
......@@ -273,5 +272,8 @@ g_pfnVectors:
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g041xx.s
浏览文件 @ 804e3967
......@@ -2,7 +2,7 @@
******************************************************************************
* @file startup_stm32g041xx.s
* @author MCD Application Team
* @brief STM32G041xx devices vector table for Atollic TrueSTUDIO toolchain.
* @brief STM32G041xx devices vector table for SW4STM32 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
......@@ -14,8 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2019 STMicroelectronics. All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
......@@ -85,9 +84,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bl entry
LoopForever:
b LoopForever
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g070xx.s
浏览文件 @ 804e3967
......@@ -2,7 +2,7 @@
******************************************************************************
* @file startup_stm32g070xx.s
* @author MCD Application Team
* @brief STM32G070xx devices vector table for Atollic TrueSTUDIO toolchain.
* @brief STM32G070xx devices vector table for SW4STM32 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
......@@ -14,8 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2018 STMicroelectronics. All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
......@@ -85,9 +84,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bl entry
LoopForever:
b LoopForever
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g071xx.s
浏览文件 @ 804e3967
......@@ -2,7 +2,7 @@
******************************************************************************
* @file startup_stm32g071xx.s
* @author MCD Application Team
* @brief STM32G071xx devices vector table for Atollic TrueSTUDIO toolchain.
* @brief STM32G071xx devices vector table for SW4STM32 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
......@@ -14,8 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2018 STMicroelectronics. All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
......@@ -85,7 +84,7 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
/* bl __libc_init_array */
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl entry
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/gcc/startup_stm32g081xx.s
浏览文件 @ 804e3967
......@@ -2,7 +2,7 @@
******************************************************************************
* @file startup_stm32g081xx.s
* @author MCD Application Team
* @brief STM32G051xx devices vector table for Atollic TrueSTUDIO toolchain.
* @brief STM32G081xx devices vector table for SW4STM32 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
......@@ -14,8 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
* Copyright (c) 2018 STMicroelectronics. All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
......@@ -85,9 +84,9 @@ LoopFillZerobss:
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* bl __libc_init_array */
/* Call the application's entry point.*/
bl main
bl entry
LoopForever:
b LoopForever
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g030xx.s
浏览文件 @ 804e3967
......@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g031xx.s
浏览文件 @ 804e3967
......@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g041xx.s
浏览文件 @ 804e3967
......@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2019 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g070xx.s
浏览文件 @ 804e3967
......@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2018 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g071xx.s
浏览文件 @ 804e3967
......@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2018 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/iar/startup_stm32g081xx.s
浏览文件 @ 804e3967
......@@ -14,8 +14,7 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2018 STMicroelectronics. All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the
......
bsp/stm32/libraries/STM32G0xx_HAL/CMSIS/ST/STM32G0xx/Source/Templates/system_stm32g0xx.c
浏览文件 @ 804e3967
......@@ -79,19 +79,19 @@
#include "stm32g0xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
#if !defined (LSI_VALUE)
#define LSI_VALUE 32000U /*!< Value of LSI in Hz*/
#define LSI_VALUE (32000UL) /*!< Value of LSI in Hz*/
#endif /* LSI_VALUE */
#if !defined (LSE_VALUE)
#define LSE_VALUE 32768U /*!< Value of LSE in Hz*/
#define LSE_VALUE (32768UL) /*!< Value of LSE in Hz*/
#endif /* LSE_VALUE */
/**
......@@ -140,10 +140,10 @@
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = 16000000U;
uint32_t SystemCoreClock = 16000000UL;
const uint32_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint32_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
const uint32_t AHBPrescTable[16UL] = {0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL, 6UL, 7UL, 8UL, 9UL};
const uint32_t APBPrescTable[8UL] = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
/**
* @}
......@@ -241,25 +241,26 @@ void SystemCoreClockUpdate(void)
break;
case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U;
switch (pllsource)
{
case 0x03: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm);
break;
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL;
case 0x02: /* HSI used as PLL clock source */
default:
if(pllsource == 0x03UL) /* HSE used as PLL clock source */
{
pllvco = (HSE_VALUE / pllm);
}
else /* HSI used as PLL clock source */
{
pllvco = (HSI_VALUE / pllm);
break;
}
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U);
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
SystemCoreClock = pllvco/pllr;
break;
}
case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
default: /* HSI used as system clock */
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV))>> RCC_CR_HSIDIV_Pos));
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal.h
浏览文件 @ 804e3967
......@@ -89,6 +89,23 @@ extern "C" {
* @}
*/
#if defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx)
/** @defgroup SYSCFG_ClampingDiode Clamping Diode
* @{
*/
#define SYSCFG_CDEN_PA1 SYSCFG_CFGR2_PA1_CDEN /*!< Enables Clamping Diode on PA1 */
#define SYSCFG_CDEN_PA3 SYSCFG_CFGR2_PA3_CDEN /*!< Enables Clamping Diode on PA3 */
#define SYSCFG_CDEN_PA5 SYSCFG_CFGR2_PA5_CDEN /*!< Enables Clamping Diode on PA5 */
#define SYSCFG_CDEN_PA6 SYSCFG_CFGR2_PA6_CDEN /*!< Enables Clamping Diode on PA6 */
#define SYSCFG_CDEN_PA13 SYSCFG_CFGR2_PA13_CDEN /*!< Enables Clamping Diode on PA13 */
#define SYSCFG_CDEN_PB0 SYSCFG_CFGR2_PB0_CDEN /*!< Enables Clamping Diode on PB0 */
#define SYSCFG_CDEN_PB1 SYSCFG_CFGR2_PB1_CDEN /*!< Enables Clamping Diode on PB1 */
#define SYSCFG_CDEN_PB2 SYSCFG_CFGR2_PB2_CDEN /*!< Enables Clamping Diode on PB2 */
/**
* @}
*/
#endif
/** @defgroup HAL_Pin_remapping Pin remapping
* @{
......@@ -107,6 +124,8 @@ extern "C" {
#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IR Modulation envelope source */
#if defined (STM32G081xx) || defined (STM32G071xx) || defined (STM32G070xx)
#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART4 is selected as IR Modulation envelope source */
#elif defined (STM32G041xx) || defined (STM32G031xx) || defined (STM32G030xx)
#define HAL_SYSCFG_IRDA_ENV_SEL_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IR Modulation envelope source */
#endif
/**
......@@ -495,6 +514,18 @@ extern "C" {
CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0U)
#if defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx)
/** @brief Clamping Diode on specific pins enable/disable macros
* @param __PIN__ This parameter can be a combination of values @ref SYSCFG_ClampingDiode
*/
#define __HAL_SYSCFG_CLAMPINGDIODE_ENABLE(__PIN__) do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\
SET_BIT(SYSCFG->CFGR2, (__PIN__));\
}while(0U)
#define __HAL_SYSCFG_CLAMPINGDIODE_DISABLE(__PIN__) do {assert_param(IS_SYSCFG_CLAMPINGDIODE((__PIN__)));\
CLEAR_BIT(SYSCFG->CFGR2, (__PIN__));\
}while(0U)
#endif
/** @brief ISR wrapper check
* @note Allow to determine interrupt source per line.
......@@ -561,11 +592,25 @@ extern "C" {
((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
#endif
#if defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx)
#define IS_SYSCFG_CLAMPINGDIODE(__PIN__) ((((__PIN__) & SYSCFG_CDEN_PA1) == SYSCFG_CDEN_PA1) || \
(((__PIN__) & SYSCFG_CDEN_PA3) == SYSCFG_CDEN_PA3) || \
(((__PIN__) & SYSCFG_CDEN_PA5) == SYSCFG_CDEN_PA5) || \
(((__PIN__) & SYSCFG_CDEN_PA6) == SYSCFG_CDEN_PA6) || \
(((__PIN__) & SYSCFG_CDEN_PA13) == SYSCFG_CDEN_PA13) || \
(((__PIN__) & SYSCFG_CDEN_PB0) == SYSCFG_CDEN_PB0) || \
(((__PIN__) & SYSCFG_CDEN_PB1) == SYSCFG_CDEN_PB1) || \
(((__PIN__) & SYSCFG_CDEN_PB2) == SYSCFG_CDEN_PB2))
#endif
#if defined (STM32G081xx) || defined (STM32G071xx) || defined (STM32G070xx)
#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
#elif defined (STM32G041xx) || defined (STM32G031xx) || defined (STM32G030xx)
#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART2))
#endif
#define IS_HAL_SYSCFG_IRDA_POL_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_POLARITY_NOT_INVERTED) || \
((SEL) == HAL_SYSCFG_IRDA_POLARITY_INVERTED))
......@@ -696,6 +741,10 @@ void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
void HAL_SYSCFG_EnableRemap(uint32_t PinRemap);
void HAL_SYSCFG_DisableRemap(uint32_t PinRemap);
#if defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx)
void HAL_SYSCFG_EnableClampingDiode(uint32_t PinConfig);
void HAL_SYSCFG_DisableClampingDiode(uint32_t PinConfig);
#endif
#if defined (SYSCFG_CFGR1_UCPD1_STROBE) || defined (SYSCFG_CFGR1_UCPD2_STROBE)
void HAL_SYSCFG_StrobeDBattpinsConfig(uint32_t ConfigDeadBattery);
#endif
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_adc.h
浏览文件 @ 804e3967
......@@ -359,7 +359,11 @@ typedef struct
/**
* @brief ADC handle Structure definition
*/
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
typedef struct __ADC_HandleTypeDef
#else
typedef struct
#endif
{
ADC_TypeDef *Instance; /*!< Register base address */
ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
......@@ -421,7 +425,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @{
*/
#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error (problem of clocking,
#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking,
enable/disable, erroneous state, ...) */
#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
......@@ -508,19 +512,19 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
*/
/* ADC group regular trigger sources for all ADC instances */
#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */
#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#if defined(TIM2)
#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
#endif
#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
#if defined(TIM6)
#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
#endif
#if defined(TIM15)
#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
#endif
#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
/**
* @}
*/
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cec.h
浏览文件 @ 804e3967
......@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
......@@ -111,8 +111,8 @@ typedef struct
} CEC_InitTypeDef;
/**
* @brief HAL CEC State structures definition
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
* @brief HAL CEC State definition
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition).
* - gState contains CEC state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
......@@ -121,14 +121,14 @@ typedef struct
* b6 Error information
* 0 : No Error
* 1 : Error
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized. HAL CEC Init function already called)
* b5 CEC peripheral initilisation status
* 0 : Reset (peripheral not initialized)
* 1 : Init done (peripheral initialized. HAL CEC Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (IP busy with some configuration or internal operations)
* 1 : Busy (peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
......@@ -138,9 +138,9 @@ typedef struct
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized)
* b5 CEC peripheral initilisation status
* 0 : Reset (peripheral not initialized)
* 1 : Init done (peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
......@@ -149,27 +149,16 @@ typedef struct
* b0 (not used)
* x : Should be set to 0.
*/
typedef enum
{
HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
Value is allowed for gState and RxState */
HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
Value is allowed for gState only */
HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
Value is allowed for RxState only */
HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
Value is allowed for gState only */
HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
Value is allowed for gState only */
HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
} HAL_CEC_StateTypeDef;
typedef uint32_t HAL_CEC_StateTypeDef;
/**
* @brief CEC handle Structure definition
*/
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
typedef struct __CEC_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
{
CEC_TypeDef *Instance; /*!< CEC registers base address */
......@@ -194,8 +183,10 @@ typedef struct __CEC_HandleTypeDef
in case error is reported */
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
void (* TxCpltCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Tx Transfer completed callback */
void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec, uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
void (* TxCpltCallback)(struct __CEC_HandleTypeDef
*hcec); /*!< CEC Tx Transfer completed callback */
void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
......@@ -221,7 +212,8 @@ typedef enum
* @brief HAL CEC Callback pointer definition
*/
typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */
typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */
typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
......@@ -231,7 +223,25 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, uint32_t RxFram
/** @defgroup CEC_Exported_Constants CEC Exported Constants
* @{
*/
/** @defgroup CEC_State_Definition CEC State Code Definition
* @{
*/
#define HAL_CEC_STATE_RESET ((uint32_t)0x00000000) /*!< Peripheral is not yet Initialized
Value is allowed for gState and RxState */
#define HAL_CEC_STATE_READY ((uint32_t)0x00000020) /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
#define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024) /*!< an internal process is ongoing
Value is allowed for gState only */
#define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022) /*!< Data Reception process is ongoing
Value is allowed for RxState only */
#define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021) /*!< Data Transmission process is ongoing
Value is allowed for gState only */
#define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023) /*!< an internal process is ongoing
Value is allowed for gState only */
#define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050) /*!< Error Value is allowed for gState only */
/**
* @}
*/
/** @defgroup CEC_Error_Code CEC Error Code
* @{
*/
......@@ -413,7 +423,7 @@ typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, uint32_t RxFram
* @{
*/
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
/**
* @}
*/
......@@ -635,7 +645,8 @@ void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, pCEC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
pCEC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback);
......@@ -649,7 +660,8 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
uint8_t *pData, uint32_t Size);
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_comp.h
浏览文件 @ 804e3967
......@@ -38,13 +38,13 @@ extern "C" {
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup COMP_Exported_Types COMP Exported Types
* @{
*/
/**
* @brief COMP Init structure definition
/**
* @brief COMP Init structure definition
*/
typedef struct
{
......@@ -80,7 +80,7 @@ typedef struct
uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI).
This parameter can be a value of @ref COMP_EXTI_TriggerMode */
}COMP_InitTypeDef;
} COMP_InitTypeDef;
/**
* @brief HAL COMP state machine: HAL COMP states definition
......@@ -94,9 +94,9 @@ typedef enum
HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */
HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */
HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */
}HAL_COMP_StateTypeDef;
} HAL_COMP_StateTypeDef;
/**
/**
* @brief COMP Handle Structure definition
*/
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
......@@ -297,10 +297,10 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @retval None
*/
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_COMP_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_COMP_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
......@@ -311,7 +311,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @param __HANDLE__ COMP handle
* @retval None
*/
#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
/**
* @brief Enable the specified comparator.
......@@ -389,7 +389,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/**
* @brief Disable the COMP1 EXTI line rising & falling edge trigger.
* @retval None
*/
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
......@@ -597,7 +597,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @{
*/
/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
* @{
*/
/**
......@@ -605,8 +605,8 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @param __INSTANCE__ specifies the COMP instance.
* @retval value of @ref COMP_ExtiLine
*/
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \
: COMP_EXTI_LINE_COMP2)
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \
: COMP_EXTI_LINE_COMP2)
/**
* @}
*/
......@@ -694,13 +694,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/* Initialization and de-initialization functions **********************************/
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
pCOMP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/**
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_conf_template.h
浏览文件 @ 804e3967
......@@ -61,7 +61,6 @@ extern "C" {
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_UCPD_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
/* ########################## Register Callbacks selection ############################## */
......@@ -109,6 +108,7 @@ extern "C" {
#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
......@@ -138,6 +138,7 @@ in voltage and temperature.*/
#define EXTERNAL_I2S1_CLOCK_VALUE (48000UL) /*!< Value of the I2S1 External clock source in Hz*/
#endif /* EXTERNAL_I2S1_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
......@@ -282,10 +283,6 @@ in voltage and temperature.*/
#include "stm32g0xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_UCPD_MODULE_ENABLED
#include "stm32g0xx_ll_ucpd.h"
#endif /* HAL_UCPD_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32g0xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_cryp.h
浏览文件 @ 804e3967
......@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
......@@ -64,9 +64,12 @@ typedef struct
uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
GCM : also known as Additional Authentication Data
CCM : named B1 composed of the associated data length and Associated Data. */
uint32_t HeaderSize; /*!< The size of header buffer in word */
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
uint32_t HeaderSize; /*!< The size of header buffer in word */
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
Vector only once and to skip configuration for consecutive processings.
This parameter can be a value of @ref CRYP_Configuration_Skip */
} CRYP_ConfigTypeDef;
......@@ -122,7 +125,7 @@ typedef struct
__IO uint16_t CrypOutCount; /*!< Counter of output data */
uint16_t Size; /*!< length of input data in word */
uint16_t Size; /*!< length of input data in words */
uint32_t Phase; /*!< CRYP peripheral phase */
......@@ -136,6 +139,13 @@ typedef struct
__IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when
configuration can be skipped */
uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored
for a single signature computation after several
messages processing */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */
void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */
......@@ -161,7 +171,7 @@ typedef struct
uint32_t CrypOutCount_saved; /*!< copy of CRYP output data counter when processing is suspended */
uint32_t Phase_saved; /*!< copy of CRYP authentication phase when processing is suspended */
__IO HAL_CRYP_STATETypeDef State_saved; /*!< copy of CRYP peripheral state when processing is suspended */
uint32_t IV_saved[4]; /*!< copy of Initialisation Vector registers */
......@@ -247,7 +257,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
*/
#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */
#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is byte */
/**
* @}
......@@ -322,6 +332,18 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point
* @}
*/
/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
* @{
*/
#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
/**
* @}
*/
/**
* @}
*/
......@@ -540,6 +562,9 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
((DATATYPE) == CRYP_DATATYPE_8B) || \
((DATATYPE) == CRYP_DATATYPE_1B))
#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
/**
* @}
*/
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac.h
浏览文件 @ 804e3967
......@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
......@@ -110,8 +110,7 @@ typedef struct
uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
}
DAC_SampleAndHoldConfTypeDef;
} DAC_SampleAndHoldConfTypeDef;
/**
* @brief DAC Configuration regular Channel structure definition
......@@ -156,8 +155,8 @@ typedef enum
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
HAL_DAC_MSP_INIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
HAL_DAC_MSP_DEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
} HAL_DAC_CallbackIDTypeDef;
......@@ -196,17 +195,18 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
/** @defgroup DAC_trigger_selection DAC trigger selection
* @{
*/
#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
#define DAC_TRIGGER_SOFTWARE (DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
#define DAC_TRIGGER_T1_TRGO (DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T6_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T7_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1_OUT selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM2_OUT selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
#define DAC_TRIGGER_SOFTWARE (DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
#define DAC_TRIGGER_T1_TRGO (DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T6_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T7_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1_OUT selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM2_OUT selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
/**
* @}
*/
......@@ -272,16 +272,14 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
*/
/** @defgroup DAC_UserTrimming DAC User Trimming
* @{
*/
* @{
*/
#define DAC_TRIMMING_FACTORY 0x00000000U /*!< Factory trimming */
#define DAC_TRIMMING_USER 0x00000001U /*!< User trimming */
/**
* @}
*/
/** @defgroup DAC_SampleAndHold DAC power mode
* @{
*/
......@@ -291,7 +289,6 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
/**
* @}
*/
/**
* @}
*/
......@@ -322,7 +319,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
* @retval None
*/
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
/** @brief Disable the DAC channel.
* @param __HANDLE__ specifies the DAC handle
......@@ -330,7 +327,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
* @retval None
*/
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
/** @brief Set DHR12R1 alignment.
* @param __ALIGNMENT__ specifies the DAC alignment
......@@ -450,12 +447,13 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
*/
/** @addtogroup DAC_Exported_Functions_Group2
* @{
*/
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
......@@ -469,7 +467,8 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* DAC callback registering/unregistering */
HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
pDAC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
......@@ -503,6 +502,16 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
* @}
*/
/** @defgroup DAC_Private_Functions DAC Private Functions
* @{
*/
void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dac_ex.h
浏览文件 @ 804e3967
......@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
......@@ -122,7 +122,7 @@ extern "C" {
((CONNECT) == DAC_CHIPCONNECT_ENABLE))
#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
((TRIMMING) == DAC_TRIMMING_USER))
((TRIMMING) == DAC_TRIMMING_USER))
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
......@@ -160,8 +160,8 @@ extern "C" {
*/
/** @addtogroup DACEx_Exported_Functions_Group2
* @{
*/
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
......@@ -186,7 +186,8 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue);
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
uint32_t NewTrimmingValue);
uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
/**
......@@ -197,7 +198,6 @@ uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
* @}
*/
/** @addtogroup DACEx_Private_Functions
* @{
*/
......@@ -209,8 +209,8 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
/**
* @}
*/
* @}
*/
/**
* @}
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_dma.h
浏览文件 @ 804e3967
......@@ -277,6 +277,7 @@ typedef struct __DMA_HandleTypeDef
#define DMA_REQUEST_UCPD2_RX 60U /*!< DMAMUX UCPD2 RX request */
#define DMA_REQUEST_UCPD2_TX 61U /*!< DMAMUX UCPD2 TX request */
#endif
/**
* @}
*/
......@@ -668,6 +669,8 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
#if defined(STM32G081xx)||defined(STM32G071xx)||defined(STM32G070xx)
#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_UCPD2_TX)
#elif defined(STM32G041xx)||defined(STM32G031xx)||defined(STM32G030xx)
#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_USART2_TX)
#endif
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_flash_ex.h
浏览文件 @ 804e3967
......@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
......@@ -44,8 +44,8 @@ extern "C" {
/** @defgroup FLASHEx_Empty_Check FLASHEx Empty Check
* @{
*/
#define FLASH_PROG_NOT_EMPTY 0x00000000u /*!< 1st location in Flash is programmed */
#define FLASH_PROG_EMPTY FLASH_ACR_PROGEMPTY /*!< 1st location in Flash is empty */
#define FLASH_PROG_NOT_EMPTY 0x00000000u /*!< 1st location in Flash is programmed */
#define FLASH_PROG_EMPTY FLASH_ACR_PROGEMPTY /*!< 1st location in Flash is empty */
/**
* @}
*/
......@@ -86,8 +86,8 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants
* @{
*/
#define FLASH_PCROP_GRANULARITY_OFFSET 9u
#define FLASH_PCROP_GRANULARITY (1u << FLASH_PCROP_GRANULARITY_OFFSET)
#define FLASH_PCROP_GRANULARITY_OFFSET 9u /*!< FLASH Code Readout Protection granularity offset */
#define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 512 Bytes */
/**
* @}
*/
......@@ -97,7 +97,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
* @{
*/
#define IS_FLASH_EMPTY_CHECK(__VALUE__) (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY))
void FLASH_PageErase(uint32_t Page);
/**
* @}
*/
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio.h
浏览文件 @ 804e3967
......@@ -251,8 +251,8 @@ typedef enum
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\
(((__PIN__) & ~GPIO_PIN_MASK) == 0x00u))
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u))
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_gpio_ex.h
浏览文件 @ 804e3967
......@@ -47,6 +47,8 @@ extern "C" {
* @{
*/
#if defined (STM32G081xx) || defined (STM32G071xx)
/*------------------------- STM32G081xx / STM32G071xx ------------------------*/
/**
......@@ -228,7 +230,152 @@ extern "C" {
#endif /* STM32G070xx */
#if defined (STM32G031xx) || defined (STM32G041xx)
/*------------------------- STM32G041xx / STM32G031xx ------------------------*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */
#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */
#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */
#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */
#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */
#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */
#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */
#define GPIO_AF1_LPUART1 ((uint8_t)0x01) /*!< LPUART1 Alternate Function mapping */
#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */
#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */
#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */
#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */
#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */
#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */
#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
/**
* @brief AF 4 selection
*/
#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */
#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
#define GPIO_AF5_LPTIM1 ((uint8_t)0x05) /*!< LPTIM1 Alternate Function mapping */
#define GPIO_AF5_LPTIM2 ((uint8_t)0x05) /*!< LPTIM2 Alternate Function mapping */
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */
#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */
#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */
#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */
#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /*!< LPUART1 Alternate Function mapping */
/**
* @brief AF 7 selection
*/
#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07)
#endif /* STM32G031xx || STM32G041xx */
#if defined (STM32G030xx)
/*------------------------- STM32G030xx --------------------------------------*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /*!< EVENTOUT Alternate Function mapping */
#define GPIO_AF0_IR ((uint8_t)0x00) /*!< IR Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_OSC ((uint8_t)0x00) /*!< OSC (By pass and Enable) Alternate Function mapping */
#define GPIO_AF0_OSC32 ((uint8_t)0x00) /*!< OSC32 (By pass and Enable) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD) Alternate Function mapping */
#define GPIO_AF0_SPI1 ((uint8_t)0x00) /*!< SPI1 Alternate Function mapping */
#define GPIO_AF0_SPI2 ((uint8_t)0x00) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF0_TIM14 ((uint8_t)0x00) /*!< TIM14 Alternate Function mapping */
#define GPIO_AF0_USART1 ((uint8_t)0x00) /*!< USART1 Alternate Function mapping */
#define GPIO_AF0_USART2 ((uint8_t)0x00) /*!< USART2 Alternate Function mapping */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */
#define GPIO_AF1_OSC ((uint8_t)0x01) /*!< OSC (By pass and Enable) Alternate Function mapping */
#define GPIO_AF1_SPI2 ((uint8_t)0x01) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM3 ((uint8_t)0x01) /*!< TIM3 Alternate Function mapping */
#define GPIO_AF1_USART1 ((uint8_t)0x01) /*!< USART1 Alternate Function mapping */
#define GPIO_AF1_USART2 ((uint8_t)0x01) /*!< USART2 Alternate Function mapping */
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */
#define GPIO_AF2_TIM14 ((uint8_t)0x02) /*!< TIM14 Alternate Function mapping */
#define GPIO_AF2_TIM16 ((uint8_t)0x02) /*!< TIM16 Alternate Function mapping */
#define GPIO_AF2_TIM17 ((uint8_t)0x02) /*!< TIM17 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
/**
* @brief AF 4 selection
*/
#define GPIO_AF4_SPI2 ((uint8_t)0x04) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF4_TIM14 ((uint8_t)0x04) /*!< TIM14 Alternate Function mapping */
#define GPIO_AF4_USART1 ((uint8_t)0x04) /*!< USART1 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */
#define GPIO_AF5_TIM1 ((uint8_t)0x05) /*!< TIM1 Alternate Function mapping */
#define GPIO_AF5_TIM16 ((uint8_t)0x05) /*!< TIM16 Alternate Function mapping */
#define GPIO_AF5_TIM17 ((uint8_t)0x05) /*!< TIM17 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_I2C1 ((uint8_t)0x06) /*!< I2C1 Alternate Function mapping */
#define GPIO_AF6_I2C2 ((uint8_t)0x06) /*!< I2C2 Alternate Function mapping */
/**
* @brief AF 7 selection
*/
#define GPIO_AF7_EVENTOUT ((uint8_t)0x07) /*!< EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x07)
#endif /* STM32G030xx */
/**
* @}
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c.h
浏览文件 @ 804e3967
......@@ -86,17 +86,17 @@ typedef struct
* 01 : Abort (Abort user request on going)\n
* 10 : Timeout\n
* 11 : Error\n
* b5 IP initilisation status\n
* 0 : Reset (IP not initialized)\n
* 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n
* b5 Peripheral initialization status\n
* 0 : Reset (peripheral not initialized)\n
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
* b4 (not used)\n
* x : Should be set to 0\n
* b3\n
* 0 : Ready or Busy (No Listen mode ongoing)\n
* 1 : Listen (IP in Address Listen Mode)\n
* 1 : Listen (peripheral in Address Listen Mode)\n
* b2 Intrinsic process state\n
* 0 : Ready\n
* 1 : Busy (IP busy with some configuration or internal operations)\n
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
* b1 Rx state\n
* 0 : Ready (no Rx operation ongoing)\n
* 1 : Busy (Rx operation ongoing)\n
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2c_ex.h
浏览文件 @ 804e3967
......@@ -117,6 +117,9 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2))
/**
* @}
*/
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_i2s.h
浏览文件 @ 804e3967
......@@ -83,7 +83,11 @@ typedef enum
/**
* @brief I2S handle Structure definition
*/
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
typedef struct __I2S_HandleTypeDef
#else
typedef struct
#endif
{
SPI_TypeDef *Instance; /*!< I2S registers base address */
......@@ -265,6 +269,8 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
#define I2S_FLAG_BSY SPI_SR_BSY
#define I2S_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
/**
* @}
*/
......@@ -459,29 +465,65 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
/** @defgroup I2S_Private_Macros I2S Private Macros
* @{
*/
#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
((MODE) == I2S_MODE_SLAVE_RX) || \
((MODE) == I2S_MODE_MASTER_TX) || \
((MODE) == I2S_MODE_MASTER_RX))
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
((STANDARD) == I2S_STANDARD_MSB) || \
((STANDARD) == I2S_STANDARD_LSB) || \
((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
((STANDARD) == I2S_STANDARD_PCM_LONG))
/** @brief Check whether the specified SPI flag is set or not.
* @param __SR__ copy of I2S SR regsiter.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
* @arg I2S_FLAG_UDR: Underrun error flag
* @arg I2S_FLAG_OVR: Overrun flag
* @arg I2S_FLAG_CHSIDE: Channel side flag
* @arg I2S_FLAG_BSY: Busy flag
* @retval SET or RESET.
*/
#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
((FORMAT) == I2S_DATAFORMAT_24B) || \
((FORMAT) == I2S_DATAFORMAT_32B))
/** @brief Check whether the specified SPI Interrupt is set or not.
* @param __CR2__ copy of I2S CR2 regsiter.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval SET or RESET.
*/
#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
/** @brief Checks if I2S Mode parameter is in allowed range.
* @param __MODE__ specifies the I2S Mode.
* This parameter can be a value of @ref I2S_Mode
* @retval None
*/
#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
((__MODE__) == I2S_MODE_SLAVE_RX) || \
((__MODE__) == I2S_MODE_MASTER_TX) || \
((__MODE__) == I2S_MODE_MASTER_RX))
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
((FREQ) <= I2S_AUDIOFREQ_192K)) || \
((FREQ) == I2S_AUDIOFREQ_DEFAULT))
#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
((__STANDARD__) == I2S_STANDARD_MSB) || \
((__STANDARD__) == I2S_STANDARD_LSB) || \
((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
((__STANDARD__) == I2S_STANDARD_PCM_LONG))
#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
((__FORMAT__) == I2S_DATAFORMAT_24B) || \
((__FORMAT__) == I2S_DATAFORMAT_32B))
#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
/** @brief Checks if I2S Serial clock steady state parameter is in allowed range.
* @param __CPOL__ specifies the I2S serial clock steady state.
* This parameter can be a value of @ref I2S_Clock_Polarity
* @retval None
*/
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
((CPOL) == I2S_CPOL_HIGH))
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_irda.h
浏览文件 @ 804e3967
......@@ -169,7 +169,7 @@ typedef struct
__IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
uint32_t ErrorCode; /*!< IRDA Error code */
__IO uint32_t ErrorCode; /*!< IRDA Error code */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */
......@@ -302,7 +302,7 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @}
*/
/** @defgroup IRDA_ClockPrescaler Clock Prescaler
/** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler
* @{
*/
#define IRDA_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
......@@ -456,8 +456,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
*/
/**
* @}
*/
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
......@@ -487,10 +487,10 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @retval None
*/
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
} while(0U)
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
} while(0U)
/** @brief Clear the specified IRDA pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
......@@ -605,7 +605,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (SET or RESET).
*/
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
* @param __HANDLE__ specifies the IRDA Handle.
......@@ -620,8 +621,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @retval The new state of __IT__ (SET or RESET).
*/
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the IRDA Handle.
......@@ -659,7 +660,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
&= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
/** @brief Enable UART/USART associated to IRDA Handle.
* @param __HANDLE__ specifies the IRDA Handle.
......@@ -706,7 +708,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @param __MODE__ IRDA communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
& (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
/** @brief Ensure that IRDA power mode is valid.
* @param __MODE__ IRDA power mode.
......@@ -720,17 +723,17 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
* @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
*/
#define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))
/** @brief Ensure that IRDA state is valid.
* @param __STATE__ IRDA state mode.
......@@ -775,8 +778,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer
((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
/**
* @}
*/
* @}
*/
/* Include IRDA HAL Extended module */
#include "stm32g0xx_hal_irda_ex.h"
......@@ -798,7 +801,8 @@ void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
pIRDA_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_irda_ex.h
浏览文件 @ 804e3967
......@@ -33,6 +33,7 @@ extern "C" {
*/
/** @defgroup IRDAEx IRDAEx
* @brief IRDA Extended HAL module driver
* @{
*/
......@@ -74,8 +75,8 @@ extern "C" {
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
......@@ -91,12 +92,12 @@ extern "C" {
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
......@@ -112,14 +113,47 @@ extern "C" {
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif
#elif defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
} \
else \
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif /* STM32G081xx || STM32G071xx || STM32G070xx */
/** @brief Compute the mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
......@@ -128,44 +162,44 @@ extern "C" {
*/
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU ; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
/** @brief Ensure that IRDA frame length is valid.
* @param __LENGTH__ IRDA frame length.
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_iwdg.h
浏览文件 @ 804e3967
......@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
......@@ -119,7 +119,7 @@ typedef struct
/**
* @brief Reload IWDG counter with value defined in the reload register
* (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
* (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
* @param __HANDLE__ IWDG handle
* @retval None
*/
......@@ -219,6 +219,7 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
*/
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
/**
* @}
*/
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc.h
浏览文件 @ 804e3967
......@@ -27,6 +27,7 @@ extern "C" {
/* Includes ------------------------------------------------------------------*/
#include "stm32g0xx_hal_def.h"
#include "stm32g0xx_ll_rcc.h"
/** @addtogroup STM32G0xx_HAL_Driver
* @{
......@@ -2126,19 +2127,32 @@ typedef struct
*/
#if defined(RCC_PLLQ_SUPPORT)
#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
(RCC->PLLCFGR = ((uint32_t) (__PLLR__) | \
(uint32_t) (__PLLQ__) | \
(uint32_t) (__PLLP__) | \
(uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
(uint32_t) (__PLLM__) | \
(uint32_t) (__PLLSOURCE__)))
MODIFY_REG( RCC->PLLCFGR, \
(RCC_PLLCFGR_PLLSRC | \
RCC_PLLCFGR_PLLM | \
RCC_PLLCFGR_PLLN | \
RCC_PLLCFGR_PLLP | \
RCC_PLLCFGR_PLLQ | \
RCC_PLLCFGR_PLLR), \
((uint32_t) (__PLLSOURCE__) | \
(uint32_t) (__PLLM__) | \
(uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
(uint32_t) (__PLLP__) | \
(uint32_t) (__PLLQ__) | \
(uint32_t) (__PLLR__)))
#else
#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLR__ ) \
(RCC->PLLCFGR = ((uint32_t) (__PLLR__) | \
(uint32_t) (__PLLP__) | \
(uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
(uint32_t) (__PLLM__) | \
(uint32_t) (__PLLSOURCE__)))
MODIFY_REG( RCC->PLLCFGR, \
(RCC_PLLCFGR_PLLSRC | \
RCC_PLLCFGR_PLLM | \
RCC_PLLCFGR_PLLN | \
RCC_PLLCFGR_PLLP | \
RCC_PLLCFGR_PLLR), \
((uint32_t) (__PLLSOURCE__) | \
(uint32_t) (__PLLM__) | \
(uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
(uint32_t) (__PLLP__) | \
(uint32_t) (__PLLR__)))
#endif
/** @brief Macro to get the oscillator used as PLL clock source.
* @retval The oscillator used as PLL clock source. The returned value can be one
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rcc_ex.h
浏览文件 @ 804e3967
......@@ -683,6 +683,36 @@ void HAL_RCCEx_DisableLSCO(void);
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
#elif defined(STM32G041xx)
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1))
#elif defined(STM32G031xx)
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
(((__SELECTION__) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1))
#elif defined(STM32G030xx)
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
#endif /* STM32G081xx */
#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rng.h
浏览文件 @ 804e3967
......@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
......@@ -22,10 +22,9 @@
#define STM32G0xx_HAL_RNG_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if defined(STM32G081xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32g0xx_hal_def.h"
......@@ -33,6 +32,8 @@ extern "C" {
* @{
*/
#if defined (RNG)
/** @defgroup RNG RNG
* @brief RNG HAL module driver
* @{
......@@ -76,7 +77,11 @@ typedef enum
/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
* @{
*/
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
typedef struct __RNG_HandleTypeDef
#else
typedef struct
#endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */
{
RNG_TypeDef *Instance; /*!< Register base address */
......@@ -166,12 +171,14 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t
/** @defgroup RNG_Error_Definition RNG Error Definition
* @{
*/
#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */
#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */
#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */
#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */
/**
* @}
*/
......@@ -341,6 +348,7 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
((FLAG) == RNG_FLAG_CECS) || \
((FLAG) == RNG_FLAG_SECS))
/**
* @brief Verify the RNG Clock Error Detection mode.
* @param __MODE__ RNG Clock Error Detection mode
......@@ -356,15 +364,17 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
* @}
*/
#endif /* RNG */
/**
* @}
*/
#endif
#ifdef __cplusplus
}
#endif
#endif /* STM32G0xx_HAL_RNG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc.h
浏览文件 @ 804e3967
......@@ -467,10 +467,10 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
* @}
*/
/** @defgroup RTC_Interruption_Mask RTC Interruptions Flag Mask
/** @defgroup RTC_Flag_Mask RTC Flag Mask (5bits) describe in RTC_Flags_Definitions
* @{
*/
#define RTC_IT_MASK 0x001Fu /*!< RTC interruptions flags mask */
#define RTC_FLAG_MASK 0x001Fu /*!< RTC flags mask (5bits) */
/**
* @}
*/
......@@ -480,23 +480,23 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
* - YYYYY : Interrupt flag position in the XX register (5bits)
* - XX : Interrupt status register (2bits)
* - 01: ICSR register
* - 10: SR register
* - 10: SR or SCR or MISR or SMISR registers
* @{
*/
#define RTC_FLAG_RECALPF 0x00000110u /*!< Recalibration pending Flag */
#define RTC_FLAG_INITF 0x00000106u /*!< Initialization flag */
#define RTC_FLAG_RSF 0x00000105u /*!< Registers synchronization flag */
#define RTC_FLAG_INITS 0x00000104u /*!< Initialization status flag */
#define RTC_FLAG_SHPF 0x00000103u /*!< Shift operation pending flag */
#define RTC_FLAG_WUTWF 0x00000102u /*!< Wakeup timer write flag */
#define RTC_FLAG_ALRBWF 0x00000101u /*!< Alarm B write flag */
#define RTC_FLAG_ALRAWF 0x00000100u /*!< Alarm A write flag */
#define RTC_FLAG_ITSF 0x00000205u /*!< Internal Time-stamp flag */
#define RTC_FLAG_TSOVF 0x00000204u /*!< Time-stamp overflow flag */
#define RTC_FLAG_TSF 0x00000203u /*!< Time-stamp flag */
#define RTC_FLAG_WUTF 0x00000202u /*!< Wakeup timer flag */
#define RTC_FLAG_ALRBF 0x00000201u /*!< Alarm B flag */
#define RTC_FLAG_ALRAF 0x00000200u /*!< Alarm A flag */
#define RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos) /*!< Recalibration pending Flag */
#define RTC_FLAG_INITF (0x00000100U | RTC_ICSR_INITF_Pos) /*!< Initialization flag */
#define RTC_FLAG_RSF (0x00000100U | RTC_ICSR_RSF_Pos) /*!< Registers synchronization flag */
#define RTC_FLAG_INITS (0x00000100U | RTC_ICSR_INITS_Pos) /*!< Initialization status flag */
#define RTC_FLAG_SHPF (0x00000100U | RTC_ICSR_SHPF_Pos) /*!< Shift operation pending flag */
#define RTC_FLAG_WUTWF (0x00000100U | RTC_ICSR_WUTWF_Pos) /*!< Wakeup timer write flag */
#define RTC_FLAG_ALRBWF (0x00000100U | RTC_ICSR_ALRBWF_Pos) /*!< Alarm B write flag */
#define RTC_FLAG_ALRAWF (0x00000100U | RTC_ICSR_ALRAWF_Pos) /*!< Alarm A write flag */
#define RTC_FLAG_ITSF (0x00000200U | RTC_SR_ITSF_Pos) /*!< Internal Time-stamp flag */
#define RTC_FLAG_TSOVF (0x00000200U | RTC_SR_TSOVF_Pos) /*!< Time-stamp overflow flag */
#define RTC_FLAG_TSF (0x00000200U | RTC_SR_TSF_Pos) /*!< Time-stamp flag */
#define RTC_FLAG_WUTF (0x00000200U | RTC_SR_WUTF_Pos) /*!< Wakeup timer flag */
#define RTC_FLAG_ALRBF (0x00000200U | RTC_SR_ALRBF_Pos) /*!< Alarm B flag */
#define RTC_FLAG_ALRAF (0x00000200U | RTC_SR_ALRAF_Pos) /*!< Alarm A flag */
/**
* @}
*/
......@@ -936,6 +936,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
* @{
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc);
uint8_t RTC_ByteToBcd2(uint8_t Value);
uint8_t RTC_Bcd2ToByte(uint8_t Value);
/**
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_rtc_ex.h
浏览文件 @ 804e3967
......@@ -6,11 +6,11 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
......@@ -391,8 +391,8 @@ typedef struct
* @arg @ref RTC_FLAG_ALRAF Alarm A flag
* @retval None
*/
#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? ((((__HANDLE__)->Instance->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_IT_MASK))) != 0U) ? 1U : 0U) :\
((((__HANDLE__)->Instance->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_IT_MASK))) != 0U) ? 1U : 0U))
#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? ((((__HANDLE__)->Instance->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) != 0U) ? 1U : 0U) :\
((((__HANDLE__)->Instance->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) != 0U) ? 1U : 0U))
/* ---------------------------------WAKEUPTIMER---------------------------------*/
/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
......@@ -581,8 +581,7 @@ typedef struct
* @arg @ref RTC_FLAG_TSOVF
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_TSF) ? (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSF)) : \
(__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_TSOVF)))
#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__)))
/**
* @brief Enable interrupt on the RTC Timestamp associated Exti line.
......@@ -961,12 +960,10 @@ HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc,
void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_InternalTamper7EventCallback(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard.h
浏览文件 @ 804e3967
......@@ -234,7 +234,7 @@ typedef struct __SMARTCARD_HandleTypeDef
__IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
uint32_t ErrorCode; /*!< SmartCard Error code */
__IO uint32_t ErrorCode; /*!< SmartCard Error code */
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Complete Callback */
......@@ -557,15 +557,15 @@ typedef enum
*/
#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
} while(0U)
#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
......@@ -573,11 +573,11 @@ typedef enum
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
} while(0U)
#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
} while(0U)
/** @brief Clear the specified SMARTCARD pending flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
......@@ -726,7 +726,8 @@ typedef enum
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
......@@ -750,8 +751,8 @@ typedef enum
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
(((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET)
(((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
......@@ -792,7 +793,8 @@ typedef enum
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
&= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
/** @brief Enable the USART associated to the SMARTCARD Handle.
* @param __HANDLE__ specifies the SMARTCARD Handle.
......@@ -825,8 +827,8 @@ typedef enum
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
......@@ -842,12 +844,12 @@ typedef enum
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
......@@ -863,14 +865,47 @@ typedef enum
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif
#elif defined(STM32G041xx) || defined(STM32G031xx) || defined(STM32G030xx)
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else \
{ \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif /* STM32G081xx || STM32G071xx || STM32G070xx */
/** @brief Check the Baud rate range.
* @note The maximum Baud Rate is derived from the maximum clock on G0 (64 MHz)
......@@ -931,7 +966,8 @@ typedef enum
* @param __CPOL__ SMARTCARD frame polarity.
* @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
*/
#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\
|| ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
/** @brief Ensure that SMARTCARD frame phase is valid.
* @param __CPHA__ SMARTCARD frame phase.
......@@ -971,18 +1007,18 @@ typedef enum
* @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value.
* @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
*/
#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256))
#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256))
/** @brief Ensure that SMARTCARD advanced features initialization is valid.
* @param __INIT__ SMARTCARD advanced features initialization.
......@@ -1077,8 +1113,10 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
......@@ -1090,8 +1128,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma
* @{
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_smartcard_ex.h
浏览文件 @ 804e3967
......@@ -207,7 +207,7 @@ extern "C" {
do { \
if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \
{ \
(__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
(__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
} \
else \
{ \
......@@ -238,29 +238,29 @@ extern "C" {
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
*/
#define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
/** @brief Ensure that SMARTCARD TXFIFO threshold level is valid.
* @param __THRESHOLD__ SMARTCARD TXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
/** @brief Ensure that SMARTCARD RXFIFO threshold level is valid.
* @param __THRESHOLD__ SMARTCARD RXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
/**
* @}
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_spi.h
浏览文件 @ 804e3967
......@@ -673,7 +673,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
((__CPHA__) == SPI_PHASE_2EDGE))
/** @brief Checks if SPI Slave Select parameter is in allowed range.
* @param __NSS__ specifies the SPI Slave Slelect management parameter.
* @param __NSS__ specifies the SPI Slave Select management parameter.
* This parameter can be a value of @ref SPI_Slave_Select_management
* @retval None
*/
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_tim_ex.h
浏览文件 @ 804e3967
......@@ -6,23 +6,23 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G0xx_HAL_TIM_EX_H
#define STM32G0xx_HAL_TIM_EX_H
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
......@@ -34,34 +34,34 @@
/** @addtogroup TIMEx
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
* @{
*/
/**
* @brief TIM Hall sensor Configuration Structure definition
/**
* @brief TIM Hall sensor Configuration Structure definition
*/
typedef struct
{
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t IC1Filter; /*!< Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
} TIM_HallSensor_InitTypeDef;
/**
* @brief TIM Break/Break2 input configuration
/**
* @brief TIM Break/Break2 input configuration
*/
typedef struct
{
......@@ -77,14 +77,14 @@ TIMEx_BreakInputConfigTypeDef;
/**
* @}
*/
/* End of exported types -----------------------------------------------------*/
/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
* @{
*/
/** @defgroup TIMEx_Remap TIM Extended Remapping
/** @defgroup TIMEx_Remap TIM Extended Remapping
* @{
*/
#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is connected to GPIO */
......@@ -110,18 +110,18 @@ TIMEx_BreakInputConfigTypeDef;
#endif /* TIM3 */
/**
* @}
*/
*/
/** @defgroup TIMEx_Break_Input TIM Extended Break input
/** @defgroup TIMEx_Break_Input TIM Extended Break input
* @{
*/
#define TIM_BREAKINPUT_BRK 0x00000001U /* !< Timer break input */
#define TIM_BREAKINPUT_BRK2 0x00000002U /* !< Timer break2 input */
/**
* @}
*/
*/
/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
* @{
*/
#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
......@@ -140,18 +140,18 @@ TIMEx_BreakInputConfigTypeDef;
#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */
/**
* @}
*/
*/
/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
* @{
*/
#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /* !< Break input source is active low */
#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /* !< Break input source is active_high */
/**
* @}
*/
/** @defgroup TIMEx_Timer_Input_Selection TIM Timer input selection
*/
/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection
* @{
*/
#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1_TI1 is connected to GPIO */
......@@ -159,7 +159,7 @@ TIMEx_BreakInputConfigTypeDef;
#define TIM_TIM1_TI1_COMP1 0x00000001U /* !< TIM1_TI1 is connected to COMP1 OUT */
#endif /* COMP1 */
#define TIM_TIM1_TI2_GPIO 0x00000000U /* !< TIM1_TI2 is connected to GPIO */
#define TIM_TIM1_TI2_GPIO 0x00000000U /* !< TIM1_TI2 is connected to GPIO */
#if defined(COMP2)
#define TIM_TIM1_TI2_COMP2 0x00000100U /* !< TIM1_TI2 is connected to COMP2 OUT */
#endif /* COMP2 */
......@@ -211,24 +211,24 @@ TIMEx_BreakInputConfigTypeDef;
/**
* @}
*/
*/
/* End of exported constants -------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
* @{
*/
*/
/**
* @}
*/
*/
/* End of exported macro -----------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
* @{
*/
#define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U))
*/
#define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U))
#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
......@@ -247,11 +247,11 @@ TIMEx_BreakInputConfigTypeDef;
#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U))
#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U))
/**
* @}
*/
*/
/* End of private macro ------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
......@@ -260,17 +260,17 @@ TIMEx_BreakInputConfigTypeDef;
*/
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
* @brief Timer Hall Sensor functions
* @{
*/
* @brief Timer Hall Sensor functions
* @{
*/
/* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: Interrupt */
......@@ -284,9 +284,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
*/
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
* @brief Timer Complementary Output Compare functions
* @{
*/
* @brief Timer Complementary Output Compare functions
* @{
*/
/* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
......@@ -304,9 +304,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
*/
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
* @brief Timer Complementary PWM functions
* @{
*/
* @brief Timer Complementary PWM functions
* @{
*/
/* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
......@@ -323,9 +323,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
*/
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
* @brief Timer Complementary One Pulse functions
* @{
*/
* @brief Timer Complementary One Pulse functions
* @{
*/
/* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
......@@ -339,19 +339,25 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
*/
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
* @brief Peripheral Control functions
* @{
*/
* @brief Peripheral Control functions
* @{
*/
/* Extended Control functions ************************************************/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection , uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
......@@ -384,28 +390,28 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
/**
* @}
*/
*/
/* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/
/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
* @{
*/
/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
* @{
*/
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
/**
* @}
*/
* @}
*/
/* End of private functions --------------------------------------------------*/
/**
* @}
*/
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart.h
浏览文件 @ 804e3967
......@@ -806,9 +806,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
*/
#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
} while(0U)
SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
} while(0U)
/** @brief Clear the specified UART pending flag.
* @param __HANDLE__ specifies the UART Handle.
......@@ -973,7 +973,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
/** @brief Check whether the specified UART interrupt source is enabled or not.
* @param __HANDLE__ specifies the UART Handle.
......@@ -998,8 +999,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET)
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET)
/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the UART Handle.
......@@ -1161,7 +1162,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U) + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))
#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\
+ (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ UART clock.
......@@ -1169,7 +1171,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U) + ((__BAUD__)/2U)) / (__BAUD__))
#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\
+ ((__BAUD__)/2U)) / (__BAUD__))
/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
* @param __PCLK__ UART clock.
......@@ -1177,7 +1180,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__))) + ((__BAUD__)/2U)) / (__BAUD__))
#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\
+ ((__BAUD__)/2U)) / (__BAUD__))
/** @brief Check whether or not UART instance is Low Power UART.
* @param __HANDLE__ specifies the UART Handle.
......@@ -1238,10 +1242,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
*/
#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
(((__CONTROL__) == UART_HWCONTROL_NONE) || \
((__CONTROL__) == UART_HWCONTROL_RTS) || \
((__CONTROL__) == UART_HWCONTROL_CTS) || \
((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
(((__CONTROL__) == UART_HWCONTROL_NONE) || \
((__CONTROL__) == UART_HWCONTROL_RTS) || \
((__CONTROL__) == UART_HWCONTROL_CTS) || \
((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
/**
* @brief Ensure that UART communication mode is valid.
......@@ -1509,7 +1513,8 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
pUART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
......@@ -1589,10 +1594,13 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
/** @addtogroup UART_Private_Functions UART Private Functions
* @{
*/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout);
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
/**
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_uart_ex.h
浏览文件 @ 804e3967
......@@ -138,7 +138,8 @@ typedef struct
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
uint32_t DeassertionTime);
/**
* @}
......@@ -194,8 +195,8 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
......@@ -211,12 +212,12 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
......@@ -232,20 +233,20 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == USART4) \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
{ \
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
{ \
case RCC_LPUART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
......@@ -261,7 +262,7 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else \
{ \
......@@ -278,8 +279,8 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
......@@ -295,12 +296,12 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
......@@ -316,15 +317,112 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == USART4) \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
} \
else \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#elif defined(STM32G041xx) || defined(STM32G031xx)
/** @brief Report the UART clock source.
* @param __HANDLE__ specifies the UART Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
{ \
case RCC_LPUART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_LPUART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_LPUART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_LPUART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#elif defined(STM32G030xx)
/** @brief Report the UART clock source.
* @param __HANDLE__ specifies the UART Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
} \
else \
{ \
......@@ -344,44 +442,44 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
*/
#define UART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU ; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
/**
* @brief Ensure that UART frame length is valid.
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_usart_ex.h
浏览文件 @ 804e3967
......@@ -130,44 +130,44 @@ extern "C" {
*/
#define USART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU; \
} \
else \
{ \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
/**
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_hal_wwdg.h
浏览文件 @ 804e3967
......@@ -64,7 +64,11 @@ typedef struct
/**
* @brief WWDG handle Structure definition
*/
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
typedef struct __WWDG_HandleTypeDef
#else
typedef struct
#endif
{
WWDG_TypeDef *Instance; /*!< Register base address */
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Inc/stm32g0xx_ll_crc.h
浏览文件 @ 804e3967
......@@ -338,7 +338,7 @@ __STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
{
__IO uint16_t *pReg;
pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR);
pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); /* Derogation MisraC2012 R.11.5 */
*pReg = InData;
}
......
bsp/stm32/libraries/STM32G0xx_HAL/STM32G0xx_HAL_Driver/Src/stm32g0xx_hal_adc_ex.c
浏览文件 @ 804e3967
......@@ -61,6 +61,7 @@
/* Calibration time max = 116 / fADC (refer to datasheet) */
/* = 193 024 CPU cycles */
#define ADC_CALIBRATION_TIMEOUT (193024UL) /*!< ADC calibration time-out value (unit: CPU cycles) */
/**
* @}
*/
......
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