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提交 1d6c38f4 编写于 作者: T tanek liang
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[bsp] remove RT_ASSERT() because UART not work now

上级 df40819b
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Showing with 2 addition and 8 deletion
bsp/stm32l072/board/board.c
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...@@ -68,10 +68,7 @@ static void RCC_Configuration(void) ...@@ -68,10 +68,7 @@ static void RCC_Configuration(void)
OscInit.PLL.PLLDIV = RCC_PLLDIV_2; OscInit.PLL.PLLDIV = RCC_PLLDIV_2;
OscInit.PLL.PLLMUL = RCC_PLLMUL_4; OscInit.PLL.PLLMUL = RCC_PLLMUL_4;
OscInit.PLL.PLLSource = RCC_PLLSOURCE_HSI; OscInit.PLL.PLLSource = RCC_PLLSOURCE_HSI;
if (HAL_RCC_OscConfig(&OscInit) != HAL_OK) HAL_RCC_OscConfig(&OscInit);
{
RT_ASSERT(RT_NULL);
}
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
clocks dividers */ clocks dividers */
...@@ -84,10 +81,7 @@ static void RCC_Configuration(void) ...@@ -84,10 +81,7 @@ static void RCC_Configuration(void)
ClkInit.AHBCLKDivider = RCC_SYSCLK_DIV1; ClkInit.AHBCLKDivider = RCC_SYSCLK_DIV1;
ClkInit.APB1CLKDivider = RCC_HCLK_DIV1; ClkInit.APB1CLKDivider = RCC_HCLK_DIV1;
ClkInit.APB2CLKDivider = RCC_HCLK_DIV1; ClkInit.APB2CLKDivider = RCC_HCLK_DIV1;
if (HAL_RCC_ClockConfig(&ClkInit, FLASH_LATENCY_1) != HAL_OK) HAL_RCC_ClockConfig(&ClkInit, FLASH_LATENCY_1);
{
RT_ASSERT(RT_NULL);
}
} }
#ifdef PRINT_RCC_FREQ_INFO #ifdef PRINT_RCC_FREQ_INFO
......
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