提交 fd9619bb 编写于 作者: M mindspore-ci-bot 提交者: Gitee

!3158 Add akg op registers abs/exp for Gelu/GeluGrad.

Merge pull request !3158 from DeshiChen/0717_regop_gelu
......@@ -14,9 +14,11 @@
"""__init__"""
from .abs import _abs_akg
from .add import _add_akg
from .batchmatmul import _batchmatmul_akg
from .cast import _cast_akg
from .exp import _exp_akg
from .expand_dims import _expand_dims_akg
from .greater import _greater_akg
from .inplace_assign import _inplace_assign_akg
......
# Copyright 2020 Huawei Technologies Co., Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# ============================================================================
"""Abs op"""
from mindspore.ops.op_info_register import op_info_register, AkgAscendRegOp, DataType as DT
op_info = AkgAscendRegOp("Abs") \
.fusion_type("ELEMWISE") \
.input(0, "x") \
.output(0, "output") \
.dtype_format(DT.F16_Default, DT.F16_Default) \
.dtype_format(DT.F32_Default, DT.F32_Default) \
.dtype_format(DT.F16_5HD, DT.F16_5HD) \
.dtype_format(DT.F32_5HD, DT.F32_5HD) \
.dtype_format(DT.F16_FracNZ, DT.F16_FracNZ) \
.dtype_format(DT.F32_FracNZ, DT.F32_FracNZ) \
.get_op_info()
@op_info_register(op_info)
def _abs_akg():
"""Abs Akg register"""
return
# Copyright 2020 Huawei Technologies Co., Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# ============================================================================
"""Exp op"""
from mindspore.ops.op_info_register import op_info_register, AkgAscendRegOp, DataType as DT
op_info = AkgAscendRegOp("Exp") \
.fusion_type("ELEMWISE") \
.input(0, "x") \
.output(0, "output") \
.dtype_format(DT.F16_Default, DT.F16_Default) \
.dtype_format(DT.F32_Default, DT.F32_Default) \
.dtype_format(DT.F16_5HD, DT.F16_5HD) \
.dtype_format(DT.F32_5HD, DT.F32_5HD) \
.dtype_format(DT.F16_FracNZ, DT.F16_FracNZ) \
.dtype_format(DT.F32_FracNZ, DT.F32_FracNZ) \
.get_op_info()
@op_info_register(op_info)
def _exp_akg():
"""Exp Akg register"""
return
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