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magicwindyyd
mindspore
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5b5a5658
M
mindspore
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5b5a5658
编写于
4月 21, 2020
作者:
V
VectorSL
浏览文件
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电子邮件补丁
差异文件
gpu add akg logical_and and logical_or
上级
f746caf5
变更
6
隐藏空白更改
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并排
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6 changed file
with
220 addition
and
0 deletion
+220
-0
mindspore/_akg/gpu/logical_and.py
mindspore/_akg/gpu/logical_and.py
+40
-0
mindspore/_akg/gpu/logical_or.py
mindspore/_akg/gpu/logical_or.py
+40
-0
mindspore/_akg/ops/math/logical_and.py
mindspore/_akg/ops/math/logical_and.py
+41
-0
mindspore/_akg/ops/math/logical_or.py
mindspore/_akg/ops/math/logical_or.py
+41
-0
mindspore/ops/_op_impl/akg/gpu/logical_and.py
mindspore/ops/_op_impl/akg/gpu/logical_and.py
+29
-0
mindspore/ops/_op_impl/akg/gpu/logical_or.py
mindspore/ops/_op_impl/akg/gpu/logical_or.py
+29
-0
未找到文件。
mindspore/_akg/gpu/logical_and.py
0 → 100644
浏览文件 @
5b5a5658
# Copyright 2020 Huawei Technologies Co., Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
"""logical_and"""
import
_akg.tvm
from
_akg.ops.math
import
logical_and
from
_akg.topi.generic
import
schedule_elemwise
def
LogicalAnd
(
x
,
y
):
"""LogicalAnd."""
return
logical_and
.
logical_and
(
x
,
y
)
def
gpu_schedule_LogicalAnd
(
outs
):
"""
GPU schedule for LogicalAnd.
Args:
outs (tvm.tensor.Tensor): outputs of compute.
Returns:
sch (schedule.Schedule): The created schedule.
"""
device
=
'cuda'
ctx
=
_akg
.
tvm
.
context
(
device
,
0
)
if
not
ctx
.
exist
:
raise
SystemError
(
"Skip because %s is not enabled"
%
device
)
with
_akg
.
tvm
.
target
.
create
(
device
):
sch
=
schedule_elemwise
(
outs
)
return
sch
mindspore/_akg/gpu/logical_or.py
0 → 100644
浏览文件 @
5b5a5658
# Copyright 2020 Huawei Technologies Co., Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
"""logical_or"""
import
_akg.tvm
from
_akg.ops.math
import
logical_or
from
_akg.topi.generic
import
schedule_elemwise
def
LogicalOr
(
x
,
y
):
"""LogicalOr."""
return
logical_or
.
logical_or
(
x
,
y
)
def
gpu_schedule_LogicalOr
(
outs
):
"""
GPU schedule for LogicalOr.
Args:
outs (tvm.tensor.Tensor): outputs of compute.
Returns:
sch (schedule.Schedule): The created schedule.
"""
device
=
'cuda'
ctx
=
_akg
.
tvm
.
context
(
device
,
0
)
if
not
ctx
.
exist
:
raise
SystemError
(
"Skip because %s is not enabled"
%
device
)
with
_akg
.
tvm
.
target
.
create
(
device
):
sch
=
schedule_elemwise
(
outs
)
return
sch
mindspore/_akg/ops/math/logical_and.py
0 → 100644
浏览文件 @
5b5a5658
# Copyright 2020 Huawei Technologies Co., Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
"""operator dsl function: logical_and"""
import
_akg.tvm
import
_akg.topi
from
_akg.utils
import
validation_check
as
vc_util
@
vc_util
.
check_input_type
(
_akg
.
tvm
.
tensor
.
Tensor
,
_akg
.
tvm
.
tensor
.
Tensor
)
def
logical_and
(
input1
,
input2
):
"""
Compute logical_and of input1 and input2.
Args:
input1 (tvm.tensor.Tensor): Tensor.
input2 (tvm.tensor.Tensor): Tensor.
Returns:
tvm.tensor.Tensor. LogicalAnd of input1 and input2.
"""
vc_util
.
elemwise_dtype_check
(
input1
.
dtype
,
input2
.
dtype
)
shape1
=
[
x
.
value
for
x
in
input1
.
shape
]
shape2
=
[
x
.
value
for
x
in
input2
.
shape
]
vc_util
.
check_shape
(
shape1
)
vc_util
.
check_shape
(
shape2
)
res
=
_akg
.
topi
.
logical_and
(
input1
,
input2
)
return
res
mindspore/_akg/ops/math/logical_or.py
0 → 100644
浏览文件 @
5b5a5658
# Copyright 2020 Huawei Technologies Co., Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
"""operator dsl function: logical_or"""
import
_akg.tvm
import
_akg.topi
from
_akg.utils
import
validation_check
as
vc_util
@
vc_util
.
check_input_type
(
_akg
.
tvm
.
tensor
.
Tensor
,
_akg
.
tvm
.
tensor
.
Tensor
)
def
logical_or
(
input1
,
input2
):
"""
Compute logical_or of input1 and input2.
Args:
input1 (tvm.tensor.Tensor): Tensor.
input2 (tvm.tensor.Tensor): Tensor.
Returns:
tvm.tensor.Tensor. LogicalOr of input1 and input2.
"""
vc_util
.
elemwise_dtype_check
(
input1
.
dtype
,
input2
.
dtype
)
shape1
=
[
x
.
value
for
x
in
input1
.
shape
]
shape2
=
[
x
.
value
for
x
in
input2
.
shape
]
vc_util
.
check_shape
(
shape1
)
vc_util
.
check_shape
(
shape2
)
res
=
_akg
.
topi
.
logical_or
(
input1
,
input2
)
return
res
mindspore/ops/_op_impl/akg/gpu/logical_and.py
0 → 100644
浏览文件 @
5b5a5658
# Copyright 2020 Huawei Technologies Co., Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
"""LogicalAnd op"""
from
mindspore.ops.op_info_register
import
op_info_register
,
AkgRegOp
,
DataType
logicaland_op_info
=
AkgRegOp
(
"LogicalAnd"
)
\
.
fusion_type
(
"OPAQUE"
)
\
.
input
(
0
,
"x"
)
\
.
input
(
1
,
"y"
)
\
.
output
(
0
,
"output"
)
\
.
dtype_format
(
DataType
.
BOOL_Default
,
DataType
.
BOOL_Default
,
DataType
.
BOOL_Default
)
\
.
get_op_info
()
@
op_info_register
(
logicaland_op_info
)
def
_logical_and_akg
():
"""LogicalAnd register"""
return
mindspore/ops/_op_impl/akg/gpu/logical_or.py
0 → 100644
浏览文件 @
5b5a5658
# Copyright 2020 Huawei Technologies Co., Ltd
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
"""LogicalOr op"""
from
mindspore.ops.op_info_register
import
op_info_register
,
AkgRegOp
,
DataType
logicalor_op_info
=
AkgRegOp
(
"LogicalOr"
)
\
.
fusion_type
(
"OPAQUE"
)
\
.
input
(
0
,
"x"
)
\
.
input
(
1
,
"y"
)
\
.
output
(
0
,
"output"
)
\
.
dtype_format
(
DataType
.
BOOL_Default
,
DataType
.
BOOL_Default
,
DataType
.
BOOL_Default
)
\
.
get_op_info
()
@
op_info_register
(
logicalor_op_info
)
def
_logical_or_akg
():
"""LogicalOr register"""
return
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