Skip to content

R
rt-thread

BaiXuePrincess / rt-thread
与 Fork 源项目一致

Fork自 RT-Thread / rt-thread

通知 1
Star 0
Fork 0
R
rt-thread
未验证 提交 fe691c2a 编写于 作者: B Bernard Xiong 提交者： GitHub
浏览文件
操作

Merge pull request #1484 from TanekLiang/riscv-update 

remove hifive1 bsp and risc-v/e310 porting
上级 385ee9af be278621
展开全部 隐藏空白更改
内联 并排
Showing with 0 addition and 4262 deletion
bsp/hifive1/SConscript 已删除 100644 → 0
浏览文件 @ 385ee9af
# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = str(Dir('#'))
src = Glob('*.c')
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
group = DefineGroup('', src, depend = [''], CPPPATH = [])
#objs += group
Return('objs')
bsp/hifive1/SConstruct 已删除 100644 → 0
浏览文件 @ 385ee9af
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT)
# make a building
DoBuilding(TARGET, objs)
bsp/hifive1/applications/SConscript 已删除 100644 → 0
浏览文件 @ 385ee9af
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'applications')
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/hifive1/applications/applications.c 已删除 100644 → 0
浏览文件 @ 385ee9af
#include <rtthread.h>
static void rt_init_thread_entry(void* parameter)
{
#ifdef RT_USING_COMPONENTS_INIT
/* initialization RT-Thread Components */
rt_components_init();
#endif
rt_thread_delay( RT_TIMER_TICK_PER_SECOND*2 ); /* sleep 0.5 second and switch to other thread */
}
#include <encoding.h>
#include <platform.h>
static void led_thread_entry(void* parameter)
{
unsigned int count=0;
rt_hw_led_init();
while (0)
{
/* rt_hw_led_on(0);*/
rt_thread_delay( RT_TIMER_TICK_PER_SECOND/2 ); /* sleep 0.5 second and switch to other thread */
/* led1 off */
rt_hw_led_off(0);
rt_thread_delay( RT_TIMER_TICK_PER_SECOND*2);
}
}
static rt_uint8_t led_stack[ 1024];
static struct rt_thread led_thread;
void rt_application_init()
{
rt_thread_t init_thread;
rt_err_t result;
/* init led thread */
result = rt_thread_init(&led_thread,
"led",
led_thread_entry,
RT_NULL,
(rt_uint8_t*)&led_stack[0],
sizeof(led_stack),
20,
5);
if (result == RT_EOK)
{
rt_thread_startup(&led_thread);
}
init_thread = rt_thread_create("init",
rt_init_thread_entry,
RT_NULL,
512,
8,
20);
if (init_thread != RT_NULL)
rt_thread_startup(init_thread);
return;
}
bsp/hifive1/applications/startup.c 已删除 100644 → 0
浏览文件 @ 385ee9af
#include <rtthread.h>
extern void *__bss_end__;
extern void *_heap_end;
#define HEAP_BEGIN &__bss_end__
#define HEAP_END &_heap_end
static void rtthread_startup(void)
{
/* initialize board */
rt_hw_board_init();
/* show version */
rt_show_version();
#ifdef RT_USING_HEAP
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
/* initialize scheduler system */
rt_system_scheduler_init();
/* initialize system timer*/
rt_system_timer_init();
/* initialize application */
rt_application_init();
/* initialize timer thread */
rt_system_timer_thread_init();
/* initialize idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return;
}
#include "encoding.h"
#include <platform.h>
int main(void)
{
rtthread_startup();
return 0;
}
bsp/hifive1/drivers/SConscript 已删除 100644 → 0
浏览文件 @ 385ee9af
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'drivers')
# add the general drvers.
src = Glob("*.c")
# add Ethernet drvers.
#if GetDepend('RT_USING_LED'):
# src += ['led.c']
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/hifive1/drivers/board.c 已删除 100644 → 0
浏览文件 @ 385ee9af
#include <interrupt.h>
#include <rthw.h>
#include <platform.h>
#if 0
static struct mem_desc hw_mem_desc[] =
{
{ 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB },/* None cached for 4G memory */
// visual start, visual end, phy start , props
{ 0x00000000, 0x000FFFFF, 0x20000000, RW_CB }, /* ISR Vector table */
{ 0x00200000, 0x00001FFF, 0x40000000, RW_CB }, /* 8K cached SRAM 0/1 */
{ 0x20000000, 0x21FFFFFF, 0x20000000, RW_CB }, /* 32M cached SDRAM */
{ 0x90000000, 0x90001FFF, 0x40000000, RW_NCNB },/* 4K SRAM0 + 4k SRAM1 */
{ 0xA0000000, 0xA1FFFFFF, 0x20000000, RW_NCNB },/* 32M none-cached SDRAM */
};
#endif
#include <encoding.h>
static void rt_hw_timer_init(void)
{
GPIO_REG(GPIO_INPUT_EN) &= ~((0x1<< RED_LED_OFFSET) | (0x1<< GREEN_LED_OFFSET) | (0x1 << BLUE_LED_OFFSET)) ;
GPIO_REG(GPIO_OUTPUT_EN) |= ((0x1<< RED_LED_OFFSET)| (0x1<< GREEN_LED_OFFSET) | (0x1 << BLUE_LED_OFFSET)) ;
GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << BLUE_LED_OFFSET) ;
GPIO_REG(GPIO_OUTPUT_VAL) &= ~((0x1<< RED_LED_OFFSET) | (0x1<< GREEN_LED_OFFSET)) ;
/* enable timer interrupt*/
set_csr(mie, MIP_MTIP);
volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP);
CLINT_REG(CLINT_MTIME) = 0x0;
/* CLINT_REG(CLINT_MTIMECMP) = 0x10000;*/
*mtimecmp = 0x20000;
return;
}
void rt_hw_board_init(void)
{
/* initialize mmu */
/* rt_hw_mmu_init(hw_mem_desc, sizeof(hw_mem_desc)/sizeof(hw_mem_desc[0]));*/
/* initialize hardware interrupt */
rt_hw_interrupt_init();
/* initialize the system clock */
//rt_hw_clock_init(); //set each pll etc.
/* initialize uart */
rt_hw_uart_init();
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
/* initialize timer0 */
rt_hw_timer_init();
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
return;
}
bsp/hifive1/drivers/led.c 已删除 100644 → 0
浏览文件 @ 385ee9af
void rt_hw_led_init(void)
{
return;
}
#include <stdint.h>
#include "platform.h"
void rt_hw_led_on(int led)
{
uint16_t r=0xFF;
uint16_t g=0;
uint16_t b=0;
char c = 0;
// Set up RGB PWM
/*
PWM1_REG(PWM_CFG) = 0;
// To balance the power consumption, make one left, one right, and one center aligned.
PWM1_REG(PWM_CFG) = (PWM_CFG_ENALWAYS) | (PWM_CFG_CMP2CENTER);
PWM1_REG(PWM_COUNT) = 0;
// Period is approximately 244 Hz
// the LEDs are intentionally left somewhat dim,
// as the full brightness can be painful to look at.
PWM1_REG(PWM_CMP0) = 0;
*/
if(r > 0 && b == 0){
r--;
g++;
}
if(g > 0 && r == 0){
g--;
b++;
}
if(b > 0 && g == 0){
r++;
b--;
}
uint32_t G = g;
uint32_t R = r;
uint32_t B = b;
PWM1_REG(PWM_CMP1) = G << 4; // PWM is low on the left, GPIO is low on the left side, LED is ON on the left.
PWM1_REG(PWM_CMP2) = (B << 1) << 4; // PWM is high on the middle, GPIO is low in the middle, LED is ON in the middle.
PWM1_REG(PWM_CMP3) = 0xFFFF - (R << 4); // PWM is low on the left, GPIO is low on the right, LED is on on the right.
return;
}
void rt_hw_led_off(int led)
{
return;
}
bsp/hifive1/drivers/usart.c 已删除 100644 → 0
浏览文件 @ 385ee9af
#include <rtdevice.h>
#include "usart.h"
#include <encoding.h>
#include <platform.h>
/**
* @brief set uartdbg buard
*
* @param buard
*/
static void usart_init(int buard)
{
GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
UART0_REG(UART_REG_DIV) = get_cpu_freq() / buard - 1;
UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
}
static void usart_handler(int vector, void *param)
{
rt_hw_serial_isr((struct rt_serial_device*)param, RT_SERIAL_EVENT_RX_IND);
return;
}
static rt_err_t usart_configure(struct rt_serial_device *serial,
struct serial_configure *cfg)
{
GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
UART0_REG(UART_REG_DIV) = get_cpu_freq() / 115200 - 1;
UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
UART0_REG(UART_REG_RXCTRL) |= UART_RXEN;
UART0_REG(UART_REG_IE) = UART_IP_RXWM;
return RT_EOK;
}
static rt_err_t usart_control(struct rt_serial_device *serial,
int cmd, void *arg)
{
RT_ASSERT(serial != RT_NULL);
switch(cmd){
case RT_DEVICE_CTRL_CLR_INT:
break;
case RT_DEVICE_CTRL_SET_INT:
break;
}
return RT_EOK;
}
static int usart_putc(struct rt_serial_device *serial, char c)
{
while (UART0_REG(UART_REG_TXFIFO) & 0x80000000) ;
UART0_REG(UART_REG_TXFIFO) = c;
return 0;
}
static int usart_getc(struct rt_serial_device *serial)
{
rt_int32_t val = UART0_REG(UART_REG_RXFIFO);
if (val > 0)
return (rt_uint8_t)val;
else
return -1;
}
static struct rt_uart_ops ops = {
usart_configure,
usart_control,
usart_putc,
usart_getc,
};
static struct rt_serial_device serial = {
.ops = &ops,
.config.baud_rate = BAUD_RATE_115200,
.config.bit_order = BIT_ORDER_LSB,
.config.data_bits = DATA_BITS_8,
.config.parity = PARITY_NONE,
.config.stop_bits = STOP_BITS_1,
.config.invert = NRZ_NORMAL,
.config.bufsz = RT_SERIAL_RB_BUFSZ,
};
void rt_hw_uart_init(void)
{
rt_hw_serial_register(
&serial,
"dusart",
RT_DEVICE_FLAG_STREAM
| RT_DEVICE_FLAG_RDWR
| RT_DEVICE_FLAG_INT_RX, RT_NULL);
rt_hw_interrupt_install(
INT_UART0_BASE,
usart_handler,
(void*)&(serial.parent),
"uart interrupt");
rt_hw_interrupt_unmask(INT_UART0_BASE);
return;
}
bsp/hifive1/openocd.cfg 已删除 100644 → 0
浏览文件 @ 385ee9af
adapter_khz 10000
interface ftdi
ftdi_device_desc "Dual RS232-HS"
ftdi_vid_pid 0x0403 0x6010
ftdi_layout_init 0x0008 0x001b
ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
#Reset Stretcher logic on FE310 is ~1 second long
#This doesn't apply if you use
# ftdi_set_signal, but still good to document
#adapter_nsrst_delay 1500
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME
init
#reset -- This type of reset is not implemented yet
if {[ info exists pulse_srst]} {
ftdi_set_signal nSRST 0
ftdi_set_signal nSRST z
#Wait for the reset stretcher
#It will work without this, but
#will incur lots of delays for later commands.
sleep 1500
}
halt
flash protect 0 64 last off
bsp/hifive1/platform/SConscript 已删除 100644 → 0
浏览文件 @ 385ee9af
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
CPPPATH = [cwd]
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
# The set of source files associated with this SConscript file.
src = Glob('*.c')
group = DefineGroup('platform', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/hifive1/platform/interrupt.c 已删除 100644 → 0
浏览文件 @ 385ee9af
#include <rthw.h>
#include "plic_driver.h"
#include "platform.h"
#define MAX_HANDLERS PLIC_NUM_INTERRUPTS
extern rt_uint32_t rt_interrupt_nest;
/* exception and interrupt handler table */
struct rt_irq_desc irq_desc[MAX_HANDLERS];
rt_uint32_t rt_interrupt_from_thread;
rt_uint32_t rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
volatile plic_instance_t g_plic;
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_mask(int irq)
{
PLIC_disable_interrupt(&g_plic, irq);
return;
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_unmask(int irq)
{
PLIC_enable_interrupt(&g_plic, irq);
PLIC_set_priority(&g_plic, irq, 1);
return;
}
rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
{
rt_kprintf("UN-handled interrupt %d occurred!!!\n", vector);
return RT_NULL;
}
void rt_hw_interrupt_init(void)
{
int idx;
/* config interrupt vector*/
asm volatile(
"la t0, trap_entry\n"
"csrw mtvec, t0"
);
/* enable global interrupt*/
PLIC_init(&g_plic,
PLIC_CTRL_ADDR,
PLIC_NUM_INTERRUPTS,
PLIC_NUM_PRIORITIES);
/* init exceptions table */
for(idx=0; idx < MAX_HANDLERS; idx++)
{
rt_hw_interrupt_mask(idx);
irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
irq_desc[idx].param = RT_NULL;
#ifdef RT_USING_INTERRUPT_INFO
rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
irq_desc[idx].counter = 0;
#endif
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq)
{
//volatile rt_uint32_t irqstat;
rt_uint32_t id = PLIC_claim_interrupt(&g_plic);
return id;
}
void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id)
{
PLIC_complete_interrupt(&g_plic, id);
return;
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param handler the interrupt service routine to be installed
* @param param the interrupt service function parameter
* @param name the interrupt name
* @return old handler
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if(vector < MAX_HANDLERS)
{
old_handler = irq_desc[vector].handler;
if (handler != RT_NULL)
{
irq_desc[vector].handler = (rt_isr_handler_t)handler;
irq_desc[vector].param = param;
#ifdef RT_USING_INTERRUPT_INFO
rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
irq_desc[vector].counter = 0;
#endif
}
}
return old_handler;
}
bsp/hifive1/platform/interrupt.h 已删除 100644 → 0
浏览文件 @ 385ee9af
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
#include <rthw.h>
void rt_hw_interrupt_mask(int irq);
void rt_hw_interrupt_unmask(int irq);
rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param);
void rt_hw_interrupt_init(void);
rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq);
void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id);
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, char *name);
#endif
bsp/hifive1/platform/plic_driver.c 已删除 100644 → 0
浏览文件 @ 385ee9af
#include "sifive/devices/plic.h"
#include "plic_driver.h"
#include "platform.h"
#include "encoding.h"
#include <string.h>
void volatile_memzero(uint8_t * base, unsigned int size)
{
volatile uint8_t * ptr;
for (ptr = base; ptr < (base + size); ptr++){
*ptr = 0;
}
}
void PLIC_init (
plic_instance_t * this_plic,
uintptr_t base_addr,
uint32_t num_sources,
uint32_t num_priorities
)
{
this_plic->base_addr = base_addr;
this_plic->num_sources = num_sources;
this_plic->num_priorities = num_priorities;
// Disable all interrupts (don't assume that these registers are reset).
unsigned long hart_id = read_csr(mhartid);
volatile_memzero((uint8_t*) (this_plic->base_addr +
PLIC_ENABLE_OFFSET +
(hart_id << PLIC_ENABLE_SHIFT_PER_TARGET)),
(num_sources + 8) / 8);
// Set all priorities to 0 (equal priority -- don't assume that these are reset).
volatile_memzero ((uint8_t *)(this_plic->base_addr +
PLIC_PRIORITY_OFFSET),
(num_sources + 1) << PLIC_PRIORITY_SHIFT_PER_SOURCE);
// Set the threshold to 0.
volatile plic_threshold* threshold = (plic_threshold*)
(this_plic->base_addr +
PLIC_THRESHOLD_OFFSET +
(hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET));
*threshold = 0;
}
void PLIC_set_threshold (plic_instance_t * this_plic,
plic_threshold threshold){
unsigned long hart_id = read_csr(mhartid);
volatile plic_threshold* threshold_ptr = (plic_threshold*) (this_plic->base_addr +
PLIC_THRESHOLD_OFFSET +
(hart_id << PLIC_THRESHOLD_SHIFT_PER_TARGET));
*threshold_ptr = threshold;
}
void PLIC_enable_interrupt (plic_instance_t * this_plic, plic_source source){
unsigned long hart_id = read_csr(mhartid);
volatile uint8_t * current_ptr = (volatile uint8_t *)(this_plic->base_addr +
PLIC_ENABLE_OFFSET +
(hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) +
(source >> 3));
uint8_t current = *current_ptr;
current = current | ( 1 << (source & 0x7));
*current_ptr = current;
}
void PLIC_disable_interrupt (plic_instance_t * this_plic, plic_source source){
unsigned long hart_id = read_csr(mhartid);
volatile uint8_t * current_ptr = (volatile uint8_t *) (this_plic->base_addr +
PLIC_ENABLE_OFFSET +
(hart_id << PLIC_ENABLE_SHIFT_PER_TARGET) +
(source >> 3));
uint8_t current = *current_ptr;
current = current & ~(( 1 << (source & 0x7)));
*current_ptr = current;
}
void PLIC_set_priority (plic_instance_t * this_plic, plic_source source, plic_priority priority){
if (this_plic->num_priorities > 0) {
volatile plic_priority * priority_ptr = (volatile plic_priority *)
(this_plic->base_addr +
PLIC_PRIORITY_OFFSET +
(source << PLIC_PRIORITY_SHIFT_PER_SOURCE));
*priority_ptr = priority;
}
}
plic_source PLIC_claim_interrupt(plic_instance_t * this_plic){
unsigned long hart_id = read_csr(mhartid);
volatile plic_source * claim_addr = (volatile plic_source * )
(this_plic->base_addr +
PLIC_CLAIM_OFFSET +
(hart_id << PLIC_CLAIM_SHIFT_PER_TARGET));
return *claim_addr;
}
void PLIC_complete_interrupt(plic_instance_t * this_plic, plic_source source){
unsigned long hart_id = read_csr(mhartid);
volatile plic_source * claim_addr = (volatile plic_source *) (this_plic->base_addr +
PLIC_CLAIM_OFFSET +
(hart_id << PLIC_CLAIM_SHIFT_PER_TARGET));
*claim_addr = source;
}
bsp/hifive1/platform/plic_driver.h 已删除 100644 → 0
浏览文件 @ 385ee9af
// See LICENSE file for licence details
#ifndef PLIC_DRIVER_H
#define PLIC_DRIVER_H
#include "platform.h"
typedef struct __plic_instance_t
{
uintptr_t base_addr;
uint32_t num_sources;
uint32_t num_priorities;
} plic_instance_t;
typedef uint32_t plic_source;
typedef uint32_t plic_priority;
typedef uint32_t plic_threshold;
void PLIC_init (
plic_instance_t * this_plic,
uintptr_t base_addr,
uint32_t num_sources,
uint32_t num_priorities
);
void PLIC_set_threshold (plic_instance_t * this_plic,
plic_threshold threshold);
void PLIC_enable_interrupt (plic_instance_t * this_plic,
plic_source source);
void PLIC_disable_interrupt (plic_instance_t * this_plic,
plic_source source);
void PLIC_set_priority (plic_instance_t * this_plic,
plic_source source,
plic_priority priority);
plic_source PLIC_claim_interrupt(plic_instance_t * this_plic);
void PLIC_complete_interrupt(plic_instance_t * this_plic,
plic_source source);
#endif
bsp/hifive1/platform/rt_low_level_gcc.inc 已删除 100644 → 0
浏览文件 @ 385ee9af
/*
* File : rt_low_level_gcc.inc
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2015-04-14 ArdaFu first version
*/
/*--------- Stack size of CPU modes ------------------------------------------*/
.equ UND_STK_SIZE, 2048
.equ SVC_STK_SIZE, 4096
.equ ABT_STK_SIZE, 2048
.equ IRQ_STK_SIZE, 4096
.equ FIQ_STK_SIZE, 4096
.equ SYS_STK_SIZE, 2048
bsp/hifive1/platform/rt_low_level_init.c 已删除 100644 → 0
浏览文件 @ 385ee9af
/*
* File : rt_low_level_init.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2015-04-14 ArdaFu first version
* 2015-04-27 ArdaFu Port bsp from at91sam9260 to asm9260t
*/
void rt_low_level_init(void)
{
}
void machine_reset(void)
{
return;
}
void machine_shutdown(void)
{
return;
}
bsp/hifive1/rtconfig.h 已删除 100644 → 0
浏览文件 @ 385ee9af
/* RT-Thread config file */
#ifndef __RTTHREAD_CFG_H__
#define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/
#define RT_NAME_MAX 32
/* RT_ALIGN_SIZE*/
#define RT_ALIGN_SIZE 4
/* PRIORITY_MAX */
#define RT_THREAD_PRIORITY_MAX 255
/* Tick per Second */
#define RT_TICK_PER_SECOND 100
/* SECTION: RT_DEBUG */
/* Thread Debug */
#define RT_DEBUG
#define RT_DEBUG_TIMER 0
/*#define RT_DEBUG_IRQ 1*/
#define RT_DEBUG_SCHEDULER 0
#define RT_DEBUG_THREAD 0
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_INTERRUPT_INFO
/* Using Hook */
#define RT_USING_HOOK
/* Using Software Timer */
#define RT_USING_TIMER_SOFT
#define RT_TIMER_THREAD_PRIO 8
#define RT_TIMER_THREAD_STACK_SIZE 512
#define RT_TIMER_TICK_PER_SECOND 50
/* SECTION: IPC */
/* Using Semaphore */
#define RT_USING_SEMAPHORE
/* Using Mutex */
#define RT_USING_MUTEX
/* Using Event */
#define RT_USING_EVENT
/* Using MailBox */
#define RT_USING_MAILBOX
/* Using Message Queue */
#define RT_USING_MESSAGEQUEUE
/* SECTION: Memory Management */
/* Using Memory Pool Management*/
#define RT_USING_MEMPOOL
/* Using Dynamic Heap Management */
#define RT_USING_HEAP
/* Using Small MM */
#define RT_USING_SMALL_MEM
/* Using SLAB Allocator */
/*#define RT_USING_SLAB*/
/* SECTION: the runtime libc library */
/* the runtime libc library */
#define RT_USING_LIBC
//#define RT_USING_PTHREADS
/* Using Module System */
//#define RT_USING_MODULE
//#define RT_USING_LIBDL
/* SECTION: Device System */
/* Using Device System */
#define RT_USING_DEVICE
#define RT_USING_DEVICE_IPC
#define RT_USING_SERIAL
/* SECTION: Console options */
#define RT_USING_CONSOLE
/* the buffer size of console */
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "dusart"
/* SECTION: finsh, a C-Express shell */
/* Using FinSH as Shell*/
#define RT_USING_FINSH
/* Using symbol table */
#define FINSH_USING_SYMTAB
#define FINSH_USING_DESCRIPTION
#define FINSH_THREAD_STACK_SIZE 1024
#define FINSH_USING_MSH
#define FINSH_USING_MSH_ONLY
/* SECTION: C++ support */
/* Using C++ support */
/* #define RT_USING_CPLUSPLUS */
/* SECTION: Device filesystem support */
/* using DFS support */
//#define RT_USING_DFS
#define RT_USING_DFS_ELMFAT
/* use long file name feature */
#define RT_DFS_ELM_USE_LFN 2
#define RT_DFS_ELM_REENTRANT
/* define OEM code page */
#define RT_DFS_ELM_CODE_PAGE 936
/* Using OEM code page file */
// #define RT_DFS_ELM_CODE_PAGE_FILE
/* the max number of file length */
#define RT_DFS_ELM_MAX_LFN 128
/* #define RT_USING_DFS_YAFFS2 */
//#define RT_USING_DFS_DEVFS
#define RT_USING_DFS_NFS
#define RT_NFS_HOST_EXPORT "192.168.1.5:/"
#define DFS_USING_WORKDIR
/* the max number of mounted filesystem */
#define DFS_FILESYSTEMS_MAX 4
/* the max number of opened files */
#define DFS_FD_MAX 16
/* the max number of cached sector */
#define DFS_CACHE_MAX_NUM 4
/* Enable freemodbus protocol stack*/
/* #define RT_USING_MODBUS */
/*#define RT_USING_LED*/
/*#define RT_USING_SPI*/
/*#define RT_USING_SDIO*/
/*#define RT_USING_I2C*/
#define RT_USING_I2C_BITOPS
/*#define RT_USING_DBGU*/
#define RT_USING_UART0
/* #define RT_USING_UART1 */
/* SECTION: lwip, a lightweight TCP/IP protocol stack */
/* Using lightweight TCP/IP protocol stack */
//#define RT_USING_LWIP
#define RT_LWIP_DNS
/* Trace LwIP protocol */
// #define RT_LWIP_DEBUG
/* Enable ICMP protocol */
#define RT_LWIP_ICMP
/* Enable IGMP protocol */
#define RT_LWIP_IGMP
/* Enable UDP protocol */
#define RT_LWIP_UDP
/* Enable TCP protocol */
#define RT_LWIP_TCP
/* the number of simulatenously active TCP connections*/
#define RT_LWIP_TCP_PCB_NUM 5
/* TCP sender buffer space */
#define RT_LWIP_TCP_SND_BUF 1024*10
/* TCP receive window. */
#define RT_LWIP_TCP_WND 1024*8
/* Enable SNMP protocol */
/* #define RT_LWIP_SNMP */
/* Using DHCP */
/* #define RT_LWIP_DHCP */
/* ip address of target */
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 1
#define RT_LWIP_IPADDR3 30
/* gateway address of target */
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 1
#define RT_LWIP_GWADDR3 1
/* mask address of target */
#define RT_LWIP_MSKADDR0 255
#define RT_LWIP_MSKADDR1 255
#define RT_LWIP_MSKADDR2 255
#define RT_LWIP_MSKADDR3 0
/* the number of blocks for pbuf */
#define RT_LWIP_PBUF_NUM 16
/* the number of simultaneously queued TCP */
#define RT_LWIP_TCP_SEG_NUM 40
/* thread priority of tcpip thread */
#define RT_LWIP_TCPTHREAD_PRIORITY 128
/* mail box size of tcpip thread to wait for */
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 32
/* thread stack size of tcpip thread */
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
/* thread priority of ethnetif thread */
#define RT_LWIP_ETHTHREAD_PRIORITY 144
/* mail box size of ethnetif thread to wait for */
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32
/* thread stack size of ethnetif thread */
#define RT_LWIP_ETHTHREAD_STACKSIZE 1024
/* SECTION: RTGUI support */
/* using RTGUI support */
/* #define RT_USING_RTGUI */
/* name length of RTGUI object */
//#define RTGUI_NAME_MAX 16
/* support 16 weight font */
//#define RTGUI_USING_FONT16
/* support 16 weight font */
//#define RTGUI_USING_FONT12
/* support Chinese font */
//#define RTGUI_USING_FONTHZ
/* use DFS as file interface */
//#define RTGUI_USING_DFS_FILERW
/* use font file as Chinese font */
/* #define RTGUI_USING_HZ_FILE */
/* use Chinese bitmap font */
//#define RTGUI_USING_HZ_BMP
/* use small size in RTGUI */
/* #define RTGUI_USING_SMALL_SIZE */
/* use mouse cursor */
/* #define RTGUI_USING_MOUSE_CURSOR */
/* SECTION: FTK support */
/* using FTK support */
/* #define RT_USING_FTK */
/*
* Note on FTK:
*
* FTK depends :
* #define RT_USING_NEWLIB
* #define DFS_USING_WORKDIR
*
* And the maximal length must great than 64
* #define RT_DFS_ELM_MAX_LFN 128
*/
//#define RT_USING_CPU_FFS
#define RT_USING_COMPONENTS_INIT
#define IDLE_THREAD_STACK_SIZE 1024
#endif
bsp/hifive1/rtconfig.py 已删除 100644 → 0
浏览文件 @ 385ee9af
import os
ARCH = 'risc-v'
CPU = 'e310'
# toolchains options
CROSS_TOOL = 'gcc'
#------- toolchains path -------------------------------------------------------
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = '/home/zj/risc-v/riscv64-unknown-elf-gcc-20170612-x86_64-linux-centos6/bin'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
#BUILD = 'release'
CORE = 'risc-v'
MAP_FILE = 'rtthread.map'
LINK_FILE = 'sdram'
TARGET_NAME = 'rtthread.bin'
#------- GCC settings ----------------------------------------------------------
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'riscv64-unknown-elf-'
CC = PREFIX + 'gcc'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -march=rv32imac -mabi=ilp32 -DUSE_PLIC -DUSE_M_TIME -mcmodel=medany -msmall-data-limit=8 -g -L. -nostartfiles -lc '
CFLAGS = DEVICE
CFLAGS += ''
AFLAGS = '-c'+ DEVICE + ' -x assembler-with-cpp'
AFLAGS += ' -Iplatform'
LFLAGS = DEVICE
LFLAGS += ' -Wl,--gc-sections,-cref,-Map=' + MAP_FILE
LFLAGS += ' -T ' + LINK_FILE + '.ld'
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n'
POST_ACTION += SIZE + ' $TARGET\n'
bsp/hifive1/sdram.ld 已删除 100644 → 0
浏览文件 @ 385ee9af
OUTPUT_ARCH( "riscv" )
ENTRY( _start )
MEMORY
{
flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 16M
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
}
PHDRS
{
flash PT_LOAD;
ram_init PT_LOAD;
ram PT_NULL;
}
SECTIONS
{
__stack_size = DEFINED(__stack_size) ? __stack_size : 512;
. = 0x20400000;
. = ALIGN(4);
.init :
{
KEEP (*(SORT_NONE(.init)))
} >flash AT>flash :flash
.text :
{
*(.init)
__init_end__ = .;
*(.text)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
/* section information for modules */
. = ALIGN(4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
}>flash AT>flash :flash
.fini :
{
KEEP (*(SORT_NONE(.fini)))
} >flash AT>flash :flash
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
. = ALIGN(4);
.rodata : {
*(.rodata) ;
*(.rodata.*) ;
*(.gnu.linkonce.r*) ;
*(.eh_frame)
}>flash AT>flash :flash
. = ALIGN(4);
.ctors :
{
PROVIDE(__ctors_start__ = .);
KEEP(*(SORT(.ctors.*)))
KEEP(*(.ctors))
PROVIDE(__ctors_end__ = .);
}>flash AT>flash :flash
.dtors :
{
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
}>flash AT>flash :flash
.lalign :
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
} >flash AT>flash :flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
} >ram AT>flash :ram_init
. = ALIGN(4);
.data :
{
*(.data)
*(.data.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
*(.gnu.linkonce.d*)
}>ram AT>flash :ram_init
. = ALIGN(4);
.nobss : { *(.nobss) }
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );
PROVIDE( _fbss = . );
PROVIDE( __bss_start = . );
__bss_start__ = .;
.bss : {
*(.bss)
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
}>ram AT>flash :ram
_end = .;
__bss_end__ = .;
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
} >ram AT>ram :ram
/* stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}
bsp/hifive1/wrap_exit.c 已删除 100644 → 0
浏览文件 @ 385ee9af
#include <reent.h>
#include <sys/errno.h>
#include <sys/time.h>
#include <rtthread.h>
#ifdef RT_USING_DFS
#include <dfs_posix.h>
#endif
#ifdef RT_USING_PTHREADS
#include <pthread.h>
#endif
void
__wrap__exit (int status)
{
#ifdef RT_USING_MODULE
rt_module_t module;
module = rt_module_self();
if (module != RT_NULL)
{
struct rt_list_node *list;
struct rt_object *object;
rt_enter_critical();
/* delete all threads in the module */
list = &module->module_object[RT_Object_Class_Thread].object_list;
while (list->next != list)
{
object = rt_list_entry(list->next, struct rt_object, list);
if (rt_object_is_systemobject(object) == RT_TRUE)
{
/* detach static object */
rt_thread_detach((rt_thread_t)object);
}
else
{
/* delete dynamic object */
rt_thread_delete((rt_thread_t)object);
}
}
/* delete main thread */
rt_thread_delete(module->module_thread);
rt_exit_critical();
/* re-schedule */
rt_schedule();
}
#endif
rt_kprintf("thread:%s exit with %d\n", rt_thread_self()->name, status);
RT_ASSERT(0);
while (1);
}
libcpu/risc-v/e310/context_gcc.S 已删除 100644 → 0
浏览文件 @ 385ee9af
;/*
; * File : context_gcc.S
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2006, RT-Thread Development Team
; *
; * This program is free software; you can redistribute it and/or modify
; * it under the terms of the GNU General Public License as published by
; * the Free Software Foundation; either version 2 of the License, or
; * (at your option) any later version.
; *
; * This program is distributed in the hope that it will be useful,
; * but WITHOUT ANY WARRANTY; without even the implied warranty of
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; * GNU General Public License for more details.
; *
; * You should have received a copy of the GNU General Public License along
; * with this program; if not, write to the Free Software Foundation, Inc.,
; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
; *
; * Change Logs:
; * Date Author Notes
; * 2017-07-16 zhangjun for hifive1
; */
#include "encoding.h"
#include "sifive/bits.h"
/*
* rt_base_t rt_hw_interrupt_disable();
*/
.globl rt_hw_interrupt_disable
rt_hw_interrupt_disable:
addi sp, sp, -12
sw a5, (sp)
li a5, 0x800
csrr a0, mie
blt a0, a5, 1f
/* interrupt is enable before disable it*/
addi a0, a0, 1
li a5, 0x1
addi a5, a5, -2048
csrrc a5, mie, a5
/* csrrc a5, mie, 128*/
j 2f
/* interrupt is disabled before disable it*/
1:
li a0, 0
2:
lw a5, (sp)
addi sp, sp, 12
ret
/*
* void rt_hw_interrupt_enable(rt_base_t level);
*/
.globl rt_hw_interrupt_enable
rt_hw_interrupt_enable:
addi sp, sp, -12
sw a5, (sp)
beqz a0, 1f
li a5, 0x1
addi a5, a5, -2048
csrrs a5, mie, a5
/* csrrs a5, mie, 128*/
1:
lw a5, (sp)
addi sp, sp, 12
ret
/*
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
* a0 --> from
* a1 --> to
*/
.globl rt_hw_context_switch
rt_hw_context_switch:
addi sp, sp, -32*REGBYTES
STORE sp, (a0)
STORE x30, 1*REGBYTES(sp)
STORE x31, 2*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp)
STORE x10, 29*REGBYTES(sp)
STORE x1, 30*REGBYTES(sp)
STORE x1, 31*REGBYTES(sp)
csrr x10, mie
STORE x10, 0*REGBYTES(sp)
/*
*Remain in M-mode after mret
*enable interrupt in M-mode
*/
li t0, 136
csrrs t0, mstatus, t0
LOAD sp, (a1)
LOAD x30, 1*REGBYTES(sp)
LOAD x31, 2*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x29, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x10, 31*REGBYTES(sp)
csrw mepc,x10
LOAD x10, 0*REGBYTES(sp)
csrw mie, x10
LOAD x10, 29*REGBYTES(sp)
LOAD x1, 30*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret
/*
* void rt_hw_context_switch_to(rt_uint32 to);
* a0 --> to
*/
.globl rt_hw_context_switch_to
rt_hw_context_switch_to:
LOAD sp, (a0)
LOAD x30, 1*REGBYTES(sp)
LOAD x31, 2*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x29, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x10, 31*REGBYTES(sp)
csrw mepc,a0
LOAD x10, 29*REGBYTES(sp)
LOAD x1, 30*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret
/*
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
*/
.globl rt_thread_switch_interrupt_flag
.globl rt_interrupt_from_thread
.globl rt_interrupt_to_thread
.globl rt_hw_context_switch_interrupt
rt_hw_context_switch_interrupt:
addi sp, sp, -16
sw s0, 12(sp)
sw a0, 8(sp)
sw a5, 4(sp)
la a0, rt_thread_switch_interrupt_flag
lw a5, (a0)
bnez a5, _reswitch
li a5, 1
sw a5, (a0)
la a5, rt_interrupt_from_thread
lw a0, 8(sp)
sw a0, (a5)
_reswitch:
la a5, rt_interrupt_to_thread
sw a1, (a5)
lw a5, 4(sp)
lw a0, 8(sp)
lw s0, 12(sp)
addi sp, sp, 16
ret
libcpu/risc-v/e310/encoding.h 已删除 100644 → 0
浏览文件 @ 385ee9af
此差异已折叠。
libcpu/risc-v/e310/hifive1.h 已删除 100644 → 0
浏览文件 @ 385ee9af
// See LICENSE for license details.
#ifndef _SIFIVE_HIFIVE1_H
#define _SIFIVE_HIFIVE1_H
#include <stdint.h>
/****************************************************************************
* GPIO Connections
*****************************************************************************/
// These are the GPIO bit offsets for the RGB LED on HiFive1 Board.
// These are also mapped to RGB LEDs on the Freedom E300 Arty
// FPGA
// Dev Kit.
#define RED_LED_OFFSET 22
#define GREEN_LED_OFFSET 19
#define BLUE_LED_OFFSET 21
// These are the GPIO bit offsets for the differen digital pins
// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit.
#define PIN_0_OFFSET 16
#define PIN_1_OFFSET 17
#define PIN_2_OFFSET 18
#define PIN_3_OFFSET 19
#define PIN_4_OFFSET 20
#define PIN_5_OFFSET 21
#define PIN_6_OFFSET 22
#define PIN_7_OFFSET 23
#define PIN_8_OFFSET 0
#define PIN_9_OFFSET 1
#define PIN_10_OFFSET 2
#define PIN_11_OFFSET 3
#define PIN_12_OFFSET 4
#define PIN_13_OFFSET 5
//#define PIN_14_OFFSET 8 //This pin is not connected on either board.
#define PIN_15_OFFSET 9
#define PIN_16_OFFSET 10
#define PIN_17_OFFSET 11
#define PIN_18_OFFSET 12
#define PIN_19_OFFSET 13
// These are *PIN* numbers, not
// GPIO Offset Numbers.
#define PIN_SPI1_SCK (13u)
#define PIN_SPI1_MISO (12u)
#define PIN_SPI1_MOSI (11u)
#define PIN_SPI1_SS0 (10u)
#define PIN_SPI1_SS1 (14u)
#define PIN_SPI1_SS2 (15u)
#define PIN_SPI1_SS3 (16u)
#define SS_PIN_TO_CS_ID(x) \
((x==PIN_SPI1_SS0 ? 0 : \
(x==PIN_SPI1_SS1 ? 1 : \
(x==PIN_SPI1_SS2 ? 2 : \
(x==PIN_SPI1_SS3 ? 3 : \
-1)))))
// These buttons are present only on the Freedom E300 Arty Dev Kit.
#ifdef HAS_BOARD_BUTTONS
#define BUTTON_0_OFFSET 15
#define BUTTON_1_OFFSET 30
#define BUTTON_2_OFFSET 31
#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET)
#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_1_OFFSET)
#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_2_OFFSET)
#endif
#define HAS_HFXOSC 1
#define HAS_LFROSC_BYPASS 1
#define RTC_FREQ 32768
void write_hex(int fd, unsigned long int hex);
#endif /* _SIFIVE_HIFIVE1_H */
libcpu/risc-v/e310/init.c 已删除 100644 → 0
浏览文件 @ 385ee9af
#include <stdint.h>
#include <stdio.h>
#include <unistd.h>
#include "platform.h"
#include "encoding.h"
extern int main(int argc, char** argv);
extern void trap_entry();
static unsigned long mtime_lo(void)
{
return *(volatile unsigned long *)(CLINT_CTRL_ADDR + CLINT_MTIME);
}
#ifdef __riscv32
static uint32_t mtime_hi(void)
{
return *(volatile uint32_t *)(CLINT_CTRL_ADDR + CLINT_MTIME + 4);
}
uint64_t get_timer_value()
{
while (1) {
uint32_t hi = mtime_hi();
uint32_t lo = mtime_lo();
if (hi == mtime_hi())
return ((uint64_t)hi << 32) | lo;
}
}
#else /* __riscv32 */
uint64_t get_timer_value()
{
return mtime_lo();
}
#endif
unsigned long get_timer_freq()
{
return 32768;
}
static void use_hfrosc(int div, int trim)
{
// Make sure the HFROSC is running at its default setting
PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ;
PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
}
static void use_pll(int refsel, int bypass, int r, int f, int q)
{
// Ensure that we aren't running off the PLL before we mess with it.
if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
// Make sure the HFROSC is running at its default setting
use_hfrosc(4, 16);
}
// Set PLL Source to be HFXOSC if available.
uint32_t config_value = 0;
config_value |= PLL_REFSEL(refsel);
if (bypass) {
// Bypass
config_value |= PLL_BYPASS(1);
PRCI_REG(PRCI_PLLCFG) = config_value;
// If we don't have an HFXTAL, this doesn't really matter.
// Set our Final output divide to divide-by-1:
PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
} else {
// In case we are executing from QSPI,
// (which is quite likely) we need to
// set the QSPI clock divider appropriately
// before boosting the clock frequency.
// Div = f_sck/2
SPI0_REG(SPI_REG_SCKDIV) = 8;
// Set DIV Settings for PLL
// Both HFROSC and HFXOSC are modeled as ideal
// 16MHz sources (assuming dividers are set properly for
// HFROSC).
// (Legal values of f_REF are 6-48MHz)
// Set DIVR to divide-by-2 to get 8MHz frequency
// (legal values of f_R are 6-12 MHz)
config_value |= PLL_BYPASS(1);
config_value |= PLL_R(r);
// Set DIVF to get 512Mhz frequncy
// There is an implied multiply-by-2, 16Mhz.
// So need to write 32-1
// (legal values of f_F are 384-768 MHz)
config_value |= PLL_F(f);
// Set DIVQ to divide-by-2 to get 256 MHz frequency
// (legal values of f_Q are 50-400Mhz)
config_value |= PLL_Q(q);
// Set our Final output divide to divide-by-1:
PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
PRCI_REG(PRCI_PLLCFG) = config_value;
// Un-Bypass the PLL.
PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
// Wait for PLL Lock
// Note that the Lock signal can be glitchy.
// Need to wait 100 us
// RTC is running at 32kHz.
// So wait 4 ticks of RTC.
uint32_t now = mtime_lo();
while (mtime_lo() - now < 4) ;
// Now it is safe to check for PLL Lock
while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ;
}
// Switch over to PLL Clock source
PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
}
static void use_default_clocks()
{
// Turn off the LFROSC
AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
// Use HFROSC
use_hfrosc(4, 16);
}
static unsigned long __attribute__((noinline)) measure_cpu_freq(size_t n)
{
unsigned long start_mtime, delta_mtime;
unsigned long mtime_freq = get_timer_freq();
// Don't start measuruing until we see an mtime tick
unsigned long tmp = mtime_lo();
do {
start_mtime = mtime_lo();
} while (start_mtime == tmp);
unsigned long start_mcycle = read_csr(mcycle);
do {
delta_mtime = mtime_lo() - start_mtime;
} while (delta_mtime < n);
unsigned long delta_mcycle = read_csr(mcycle) - start_mcycle;
return (delta_mcycle / delta_mtime) * mtime_freq
+ ((delta_mcycle % delta_mtime) * mtime_freq) / delta_mtime;
}
unsigned long get_cpu_freq()
{
static uint32_t cpu_freq;
if (!cpu_freq) {
// warm up I$
measure_cpu_freq(1);
// measure for real
cpu_freq = measure_cpu_freq(10);
}
return cpu_freq;
}
#ifdef USE_PLIC
extern void handle_m_ext_interrupt();
#endif
#ifdef USE_M_TIME
extern void handle_m_time_interrupt();
#endif
void _init()
{
#ifndef NO_INIT
use_default_clocks();
use_pll(0, 0, 1, 31, 1);
write_csr(mtvec, &trap_entry);
if (read_csr(misa) & (1 << ('F' - 'A'))) { // if F extension is present
write_csr(mstatus, MSTATUS_FS); // allow FPU instructions without trapping
write_csr(fcsr, 0); // initialize rounding mode, undefined at reset
}
#endif
}
void _fini()
{
}
libcpu/risc-v/e310/platform.h 已删除 100644 → 0
浏览文件 @ 385ee9af
// See LICENSE for license details.
#ifndef _SIFIVE_PLATFORM_H
#define _SIFIVE_PLATFORM_H
// Some things missing from the official encoding.h
#define MCAUSE_INT 0x80000000
#define MCAUSE_CAUSE 0x7FFFFFFF
#include "sifive/const.h"
#include "sifive/devices/aon.h"
#include "sifive/devices/clint.h"
#include "sifive/devices/gpio.h"
#include "sifive/devices/otp.h"
#include "sifive/devices/plic.h"
#include "sifive/devices/prci.h"
#include "sifive/devices/pwm.h"
#include "sifive/devices/spi.h"
#include "sifive/devices/uart.h"
/****************************************************************************
* Platform definitions
*****************************************************************************/
// Memory map
#define MASKROM_MEM_ADDR _AC(0x00001000,UL)
#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
#define OTP_MEM_ADDR _AC(0x00020000,UL)
#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
#define PLIC_CTRL_ADDR _AC(0x0C000000,UL)
#define AON_CTRL_ADDR _AC(0x10000000,UL)
#define PRCI_CTRL_ADDR _AC(0x10008000,UL)
#define OTP_CTRL_ADDR _AC(0x10010000,UL)
#define GPIO_CTRL_ADDR _AC(0x10012000,UL)
#define UART0_CTRL_ADDR _AC(0x10013000,UL)
#define SPI0_CTRL_ADDR _AC(0x10014000,UL)
#define PWM0_CTRL_ADDR _AC(0x10015000,UL)
#define UART1_CTRL_ADDR _AC(0x10023000,UL)
#define SPI1_CTRL_ADDR _AC(0x10024000,UL)
#define PWM1_CTRL_ADDR _AC(0x10025000,UL)
#define SPI2_CTRL_ADDR _AC(0x10034000,UL)
#define PWM2_CTRL_ADDR _AC(0x10035000,UL)
#define SPI0_MEM_ADDR _AC(0x20000000,UL)
#define MEM_CTRL_ADDR _AC(0x80000000,UL)
// IOF masks
#define IOF0_SPI1_MASK _AC(0x000007FC,UL)
#define SPI11_NUM_SS (4)
#define IOF_SPI1_SS0 (2u)
#define IOF_SPI1_SS1 (8u)
#define IOF_SPI1_SS2 (9u)
#define IOF_SPI1_SS3 (10u)
#define IOF_SPI1_MOSI (3u)
#define IOF_SPI1_MISO (4u)
#define IOF_SPI1_SCK (5u)
#define IOF_SPI1_DQ0 (3u)
#define IOF_SPI1_DQ1 (4u)
#define IOF_SPI1_DQ2 (6u)
#define IOF_SPI1_DQ3 (7u)
#define IOF0_SPI2_MASK _AC(0xFC000000,UL)
#define SPI2_NUM_SS (1)
#define IOF_SPI2_SS0 (26u)
#define IOF_SPI2_MOSI (27u)
#define IOF_SPI2_MISO (28u)
#define IOF_SPI2_SCK (29u)
#define IOF_SPI2_DQ0 (27u)
#define IOF_SPI2_DQ1 (28u)
#define IOF_SPI2_DQ2 (30u)
#define IOF_SPI2_DQ3 (31u)
//#define IOF0_I2C_MASK _AC(0x00003000,UL)
#define IOF0_UART0_MASK _AC(0x00030000, UL)
#define IOF_UART0_RX (16u)
#define IOF_UART0_TX (17u)
#define IOF0_UART1_MASK _AC(0x03000000, UL)
#define IOF_UART1_RX (24u)
#define IOF_UART1_TX (25u)
#define IOF1_PWM0_MASK _AC(0x0000000F, UL)
#define IOF1_PWM1_MASK _AC(0x00780000, UL)
#define IOF1_PWM2_MASK _AC(0x00003C00, UL)
// Interrupt numbers
#define INT_RESERVED 0
#define INT_WDOGCMP 1
#define INT_RTCCMP 2
#define INT_UART0_BASE 3
#define INT_UART1_BASE 4
#define INT_SPI0_BASE 5
#define INT_SPI1_BASE 6
#define INT_SPI2_BASE 7
#define INT_GPIO_BASE 8
#define INT_PWM0_BASE 40
#define INT_PWM1_BASE 44
#define INT_PWM2_BASE 48
// Helper functions
#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i)))
#define AON_REG(offset) _REG32(AON_CTRL_ADDR, offset)
#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
#define OTP_REG(offset) _REG32(OTP_CTRL_ADDR, offset)
#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
#define PRCI_REG(offset) _REG32(PRCI_CTRL_ADDR, offset)
#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
#define PWM1_REG(offset) _REG32(PWM1_CTRL_ADDR, offset)
#define PWM2_REG(offset) _REG32(PWM2_CTRL_ADDR, offset)
#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
#define SPI1_REG(offset) _REG32(SPI1_CTRL_ADDR, offset)
#define SPI2_REG(offset) _REG32(SPI2_CTRL_ADDR, offset)
#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
#define UART1_REG(offset) _REG32(UART1_CTRL_ADDR, offset)
// Misc
#include <stdint.h>
#define NUM_GPIO 32
#define PLIC_NUM_INTERRUPTS 52
#define PLIC_NUM_PRIORITIES 7
#include "hifive1.h"
unsigned long get_cpu_freq(void);
unsigned long get_timer_freq(void);
uint64_t get_timer_value(void);
#endif /* _SIFIVE_PLATFORM_H */
libcpu/risc-v/e310/sifive/bits.h 已删除 100644 → 0
浏览文件 @ 385ee9af
// See LICENSE for license details.
#ifndef _RISCV_BITS_H
#define _RISCV_BITS_H
#define likely(x) __builtin_expect((x), 1)
#define unlikely(x) __builtin_expect((x), 0)
#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
#define ROUNDDOWN(a, b) ((a)/(b)*(b))
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
#define STR(x) XSTR(x)
#define XSTR(x) #x
#if __riscv_xlen == 64
# define SLL32 sllw
# define STORE sd
# define LOAD ld
# define LWU lwu
# define LOG_REGBYTES 3
#else
# define SLL32 sll
# define STORE sw
# define LOAD lw
# define LWU lw
# define LOG_REGBYTES 2
#endif
#define REGBYTES (1 << LOG_REGBYTES)
#endif
libcpu/risc-v/e310/sifive/const.h 已删除 100644 → 0
浏览文件 @ 385ee9af
// See LICENSE for license details.
/* Derived from <linux/const.h> */
#ifndef _SIFIVE_CONST_H
#define _SIFIVE_CONST_H
#ifdef __ASSEMBLER__
#define _AC(X,Y) X
#define _AT(T,X) X
#else
#define _AC(X,Y) (X##Y)
#define _AT(T,X) ((T)(X))
#endif /* !__ASSEMBLER__*/
#define _BITUL(x) (_AC(1,UL) << (x))
#define _BITULL(x) (_AC(1,ULL) << (x))
#endif /* _SIFIVE_CONST_H */
libcpu/risc-v/e310/sifive/devices/aon.h 已删除 100644 → 0
浏览文件 @ 385ee9af
// See LICENSE for license details.
#ifndef _SIFIVE_AON_H
#define _SIFIVE_AON_H
/* Register offsets */
#define AON_WDOGCFG 0x000
#define AON_WDOGCOUNT 0x008
#define AON_WDOGS 0x010
#define AON_WDOGFEED 0x018
#define AON_WDOGKEY 0x01C
#define AON_WDOGCMP 0x020
#define AON_RTCCFG 0x040
#define AON_RTCLO 0x048
#define AON_RTCHI 0x04C
#define AON_RTCS 0x050
#define AON_RTCCMP 0x060
#define AON_BACKUP0 0x080
#define AON_BACKUP1 0x084
#define AON_BACKUP2 0x088
#define AON_BACKUP3 0x08C
#define AON_BACKUP4 0x090
#define AON_BACKUP5 0x094
#define AON_BACKUP6 0x098
#define AON_BACKUP7 0x09C
#define AON_BACKUP8 0x0A0
#define AON_BACKUP9 0x0A4
#define AON_BACKUP10 0x0A8
#define AON_BACKUP11 0x0AC
#define AON_BACKUP12 0x0B0
#define AON_BACKUP13 0x0B4
#define AON_BACKUP14 0x0B8
#define AON_BACKUP15 0x0BC
#define AON_PMUWAKEUPI0 0x100
#define AON_PMUWAKEUPI1 0x104
#define AON_PMUWAKEUPI2 0x108
#define AON_PMUWAKEUPI3 0x10C
#define AON_PMUWAKEUPI4 0x110
#define AON_PMUWAKEUPI5 0x114
#define AON_PMUWAKEUPI6 0x118
#define AON_PMUWAKEUPI7 0x11C
#define AON_PMUSLEEPI0 0x120
#define AON_PMUSLEEPI1 0x124
#define AON_PMUSLEEPI2 0x128
#define AON_PMUSLEEPI3 0x12C
#define AON_PMUSLEEPI4 0x130
#define AON_PMUSLEEPI5 0x134
#define AON_PMUSLEEPI6 0x138
#define AON_PMUSLEEPI7 0x13C
#define AON_PMUIE 0x140
#define AON_PMUCAUSE 0x144
#define AON_PMUSLEEP 0x148
#define AON_PMUKEY 0x14C
#define AON_LFROSC 0x070
/* Constants */
#define AON_WDOGKEY_VALUE 0x51F15E
#define AON_WDOGFEED_VALUE 0xD09F00D
#define AON_WDOGCFG_SCALE 0x0000000F
#define AON_WDOGCFG_RSTEN 0x00000100
#define AON_WDOGCFG_ZEROCMP 0x00000200
#define AON_WDOGCFG_ENALWAYS 0x00001000
#define AON_WDOGCFG_ENCOREAWAKE 0x00002000
#define AON_WDOGCFG_CMPIP 0x10000000
#define AON_RTCCFG_SCALE 0x0000000F
#define AON_RTCCFG_ENALWAYS 0x00001000
#define AON_RTCCFG_CMPIP 0x10000000
#define AON_WAKEUPCAUSE_RESET 0x00
#define AON_WAKEUPCAUSE_RTC 0x01
#define AON_WAKEUPCAUSE_DWAKEUP 0x02
#define AON_WAKEUPCAUSE_AWAKEUP 0x03
#define AON_RESETCAUSE_POWERON 0x0000
#define AON_RESETCAUSE_EXTERNAL 0x0100
#define AON_RESETCAUSE_WATCHDOG 0x0200
#define AON_PMUCAUSE_WAKEUPCAUSE 0x00FF
#define AON_PMUCAUSE_RESETCAUSE 0xFF00
#endif /* _SIFIVE_AON_H */
libcpu/risc-v/e310/sifive/devices/clint.h 已删除 100644 → 0
浏览文件 @ 385ee9af
// See LICENSE for license details
#ifndef _SIFIVE_CLINT_H
#define _SIFIVE_CLINT_H
#define CLINT_MSIP 0x0000
#define CLINT_MSIP_size 0x4
#define CLINT_MTIMECMP 0x4000
#define CLINT_MTIMECMP_size 0x8
#define CLINT_MTIME 0xBFF8
#define CLINT_MTIME_size 0x8
#endif /* _SIFIVE_CLINT_H */
libcpu/risc-v/e310/sifive/devices/gpio.h 已删除 100644 → 0
浏览文件 @ 385ee9af
// See LICENSE for license details.
#ifndef _SIFIVE_GPIO_H
#define _SIFIVE_GPIO_H
#define GPIO_INPUT_VAL (0x00)
#define GPIO_INPUT_EN (0x04)
#define GPIO_OUTPUT_EN (0x08)
#define GPIO_OUTPUT_VAL (0x0C)
#define GPIO_PULLUP_EN (0x10)
#define GPIO_DRIVE (0x14)
#define GPIO_RISE_IE (0x18)
#define GPIO_RISE_IP (0x1C)
#define GPIO_FALL_IE (0x20)
#define GPIO_FALL_IP (0x24)
#define GPIO_HIGH_IE (0x28)
#define GPIO_HIGH_IP (0x2C)
#define GPIO_LOW_IE (0x30)
#define GPIO_LOW_IP (0x34)
#define GPIO_IOF_EN (0x38)
#define GPIO_IOF_SEL (0x3C)
#define GPIO_OUTPUT_XOR (0x40)
#endif /* _SIFIVE_GPIO_H */
libcpu/risc-v/e310/sifive/devices/otp.h 已删除 100644 → 0
浏览文件 @ 385ee9af
// See LICENSE for license details.
#ifndef _SIFIVE_OTP_H
#define _SIFIVE_OTP_H
/* Register offsets */
#define OTP_LOCK 0x00
#define OTP_CK 0x04
#define OTP_OE 0x08
#define OTP_SEL 0x0C
#define OTP_WE 0x10
#define OTP_MR 0x14
#define OTP_MRR 0x18
#define OTP_MPP 0x1C
#define OTP_VRREN 0x20
#define OTP_VPPEN 0x24
#define OTP_A 0x28
#define OTP_D 0x2C
#define OTP_Q 0x30
#define OTP_READ_TIMINGS 0x34
#endif
libcpu/risc-v/e310/sifive/devices/plic.h 已删除 100644 → 0
浏览文件 @ 385ee9af
// See LICENSE for license details.
#ifndef PLIC_H
#define PLIC_H
#include <sifive/const.h>
// 32 bits per source
#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL)
#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2
// 1 bit per source (1 address)
#define PLIC_PENDING_OFFSET _AC(0x1000,UL)
#define PLIC_PENDING_SHIFT_PER_SOURCE 0
//0x80 per target
#define PLIC_ENABLE_OFFSET _AC(0x2000,UL)
#define PLIC_ENABLE_SHIFT_PER_TARGET 7
#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL)
#define PLIC_CLAIM_OFFSET _AC(0x200004,UL)
#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12
#define PLIC_CLAIM_SHIFT_PER_TARGET 12
#define PLIC_MAX_SOURCE 1023
#define PLIC_SOURCE_MASK 0x3FF
#define PLIC_MAX_TARGET 15871
#define PLIC_TARGET_MASK 0x3FFF
#endif /* PLIC_H */
libcpu/risc-v/e310/sifive/devices/prci.h 已删除 100644 → 0
浏览文件 @ 385ee9af
// See LICENSE for license details.
#ifndef _SIFIVE_PRCI_H
#define _SIFIVE_PRCI_H
/* Register offsets */
#define PRCI_HFROSCCFG (0x0000)
#define PRCI_HFXOSCCFG (0x0004)
#define PRCI_PLLCFG (0x0008)
#define PRCI_PLLDIV (0x000C)
#define PRCI_PROCMONCFG (0x00F0)
/* Fields */
#define ROSC_DIV(x) (((x) & 0x2F) << 0 )
#define ROSC_TRIM(x) (((x) & 0x1F) << 16)
#define ROSC_EN(x) (((x) & 0x1 ) << 30)
#define ROSC_RDY(x) (((x) & 0x1 ) << 31)
#define XOSC_EN(x) (((x) & 0x1) << 30)
#define XOSC_RDY(x) (((x) & 0x1) << 31)
#define PLL_R(x) (((x) & 0x7) << 0)
// single reserved bit for F LSB.
#define PLL_F(x) (((x) & 0x3F) << 4)
#define PLL_Q(x) (((x) & 0x3) << 10)
#define PLL_SEL(x) (((x) & 0x1) << 16)
#define PLL_REFSEL(x) (((x) & 0x1) << 17)
#define PLL_BYPASS(x) (((x) & 0x1) << 18)
#define PLL_LOCK(x) (((x) & 0x1) << 31)
#define PLL_R_default 0x1
#define PLL_F_default 0x1F
#define PLL_Q_default 0x3
#define PLL_REFSEL_HFROSC 0x0
#define PLL_REFSEL_HFXOSC 0x1
#define PLL_SEL_HFROSC 0x0
#define PLL_SEL_PLL 0x1
#define PLL_FINAL_DIV(x) (((x) & 0x3F) << 0)
#define PLL_FINAL_DIV_BY_1(x) (((x) & 0x1 ) << 8)
#define PROCMON_DIV(x) (((x) & 0x1F) << 0)
#define PROCMON_TRIM(x) (((x) & 0x1F) << 8)
#define PROCMON_EN(x) (((x) & 0x1) << 16)
#define PROCMON_SEL(x) (((x) & 0x3) << 24)
#define PROCMON_NT_EN(x) (((x) & 0x1) << 28)
#define PROCMON_SEL_HFCLK 0
#define PROCMON_SEL_HFXOSCIN 1
#define PROCMON_SEL_PLLOUTDIV 2
#define PROCMON_SEL_PROCMON 3
#endif // _SIFIVE_PRCI_H
libcpu/risc-v/e310/sifive/devices/pwm.h 已删除 100644 → 0
浏览文件 @ 385ee9af
// See LICENSE for license details.
#ifndef _SIFIVE_PWM_H
#define _SIFIVE_PWM_H
/* Register offsets */
#define PWM_CFG 0x00
#define PWM_COUNT 0x08
#define PWM_S 0x10
#define PWM_CMP0 0x20
#define PWM_CMP1 0x24
#define PWM_CMP2 0x28
#define PWM_CMP3 0x2C
/* Constants */
#define PWM_CFG_SCALE 0x0000000F
#define PWM_CFG_STICKY 0x00000100
#define PWM_CFG_ZEROCMP 0x00000200
#define PWM_CFG_DEGLITCH 0x00000400
#define PWM_CFG_ENALWAYS 0x00001000
#define PWM_CFG_ONESHOT 0x00002000
#define PWM_CFG_CMP0CENTER 0x00010000
#define PWM_CFG_CMP1CENTER 0x00020000
#define PWM_CFG_CMP2CENTER 0x00040000
#define PWM_CFG_CMP3CENTER 0x00080000
#define PWM_CFG_CMP0GANG 0x01000000
#define PWM_CFG_CMP1GANG 0x02000000
#define PWM_CFG_CMP2GANG 0x04000000
#define PWM_CFG_CMP3GANG 0x08000000
#define PWM_CFG_CMP0IP 0x10000000
#define PWM_CFG_CMP1IP 0x20000000
#define PWM_CFG_CMP2IP 0x40000000
#define PWM_CFG_CMP3IP 0x80000000
#endif /* _SIFIVE_PWM_H */
libcpu/risc-v/e310/sifive/devices/spi.h 已删除 100644 → 0
浏览文件 @ 385ee9af
// See LICENSE for license details.
#ifndef _SIFIVE_SPI_H
#define _SIFIVE_SPI_H
/* Register offsets */
#define SPI_REG_SCKDIV 0x00
#define SPI_REG_SCKMODE 0x04
#define SPI_REG_CSID 0x10
#define SPI_REG_CSDEF 0x14
#define SPI_REG_CSMODE 0x18
#define SPI_REG_DCSSCK 0x28
#define SPI_REG_DSCKCS 0x2a
#define SPI_REG_DINTERCS 0x2c
#define SPI_REG_DINTERXFR 0x2e
#define SPI_REG_FMT 0x40
#define SPI_REG_TXFIFO 0x48
#define SPI_REG_RXFIFO 0x4c
#define SPI_REG_TXCTRL 0x50
#define SPI_REG_RXCTRL 0x54
#define SPI_REG_FCTRL 0x60
#define SPI_REG_FFMT 0x64
#define SPI_REG_IE 0x70
#define SPI_REG_IP 0x74
/* Fields */
#define SPI_SCK_POL 0x1
#define SPI_SCK_PHA 0x2
#define SPI_FMT_PROTO(x) ((x) & 0x3)
#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2)
#define SPI_FMT_DIR(x) (((x) & 0x1) << 3)
#define SPI_FMT_LEN(x) (((x) & 0xf) << 16)
/* TXCTRL register */
#define SPI_TXWM(x) ((x) & 0xffff)
/* RXCTRL register */
#define SPI_RXWM(x) ((x) & 0xffff)
#define SPI_IP_TXWM 0x1
#define SPI_IP_RXWM 0x2
#define SPI_FCTRL_EN 0x1
#define SPI_INSN_CMD_EN 0x1
#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1)
#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4)
#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8)
#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10)
#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12)
#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16)
#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24)
#define SPI_TXFIFO_FULL (1 << 31)
#define SPI_RXFIFO_EMPTY (1 << 31)
/* Values */
#define SPI_CSMODE_AUTO 0
#define SPI_CSMODE_HOLD 2
#define SPI_CSMODE_OFF 3
#define SPI_DIR_RX 0
#define SPI_DIR_TX 1
#define SPI_PROTO_S 0
#define SPI_PROTO_D 1
#define SPI_PROTO_Q 2
#define SPI_ENDIAN_MSB 0
#define SPI_ENDIAN_LSB 1
#endif /* _SIFIVE_SPI_H */
libcpu/risc-v/e310/sifive/devices/uart.h 已删除 100644 → 0
浏览文件 @ 385ee9af
// See LICENSE for license details.
#ifndef _SIFIVE_UART_H
#define _SIFIVE_UART_H
/* Register offsets */
#define UART_REG_TXFIFO 0x00
#define UART_REG_RXFIFO 0x04
#define UART_REG_TXCTRL 0x08
#define UART_REG_RXCTRL 0x0c
#define UART_REG_IE 0x10
#define UART_REG_IP 0x14
#define UART_REG_DIV 0x18
/* TXCTRL register */
#define UART_TXEN 0x1
#define UART_TXWM(x) (((x) & 0xffff) << 16)
/* RXCTRL register */
#define UART_RXEN 0x1
#define UART_RXWM(x) (((x) & 0xffff) << 16)
/* IP register */
#define UART_IP_TXWM 0x1
#define UART_IP_RXWM 0x2
#endif /* _SIFIVE_UART_H */
libcpu/risc-v/e310/sifive/sections.h 已删除 100644 → 0
浏览文件 @ 385ee9af
// See LICENSE for license details.
#ifndef _SECTIONS_H
#define _SECTIONS_H
extern unsigned char _rom[];
extern unsigned char _rom_end[];
extern unsigned char _ram[];
extern unsigned char _ram_end[];
extern unsigned char _ftext[];
extern unsigned char _etext[];
extern unsigned char _fbss[];
extern unsigned char _ebss[];
extern unsigned char _end[];
#endif /* _SECTIONS_H */
libcpu/risc-v/e310/sifive/smp.h 已删除 100644 → 0
浏览文件 @ 385ee9af
#ifndef SIFIVE_SMP
#define SIFIVE_SMP
// The maximum number of HARTs this code supports
#ifndef MAX_HARTS
#define MAX_HARTS 32
#endif
#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4)
// The hart that non-SMP tests should run on
#ifndef NONSMP_HART
#define NONSMP_HART 0
#endif
/* If your test cannot handle multiple-threads, use this:
* smp_disable(reg1)
*/
#define smp_disable(reg1, reg2) \
csrr reg1, mhartid ;\
li reg2, NONSMP_HART ;\
beq reg1, reg2, hart0_entry ;\
42: ;\
wfi ;\
j 42b ;\
hart0_entry:
/* If your test needs to temporarily block multiple-threads, do this:
* smp_pause(reg1, reg2)
* ... single-threaded work ...
* smp_resume(reg1, reg2)
* ... multi-threaded work ...
*/
#define smp_pause(reg1, reg2) \
li reg2, 0x8 ;\
csrw mie, reg2 ;\
csrr reg2, mhartid ;\
bnez reg2, 42f
#define smp_resume(reg1, reg2) \
li reg1, CLINT_CTRL_ADDR ;\
41: ;\
li reg2, 1 ;\
sw reg2, 0(reg1) ;\
addi reg1, reg1, 4 ;\
li reg2, CLINT_END_HART_IPI ;\
blt reg1, reg2, 41b ;\
42: ;\
wfi ;\
csrr reg2, mip ;\
andi reg2, reg2, 0x8 ;\
beqz reg2, 42b ;\
li reg1, CLINT_CTRL_ADDR ;\
csrr reg2, mhartid ;\
slli reg2, reg2, 2 ;\
add reg2, reg2, reg1 ;\
sw zero, 0(reg2) ;\
41: ;\
lw reg2, 0(reg1) ;\
bnez reg2, 41b ;\
addi reg1, reg1, 4 ;\
li reg2, CLINT_END_HART_IPI ;\
blt reg1, reg2, 41b
#endif
libcpu/risc-v/e310/stack.c 已删除 100644 → 0
浏览文件 @ 385ee9af
/*
* File : stack.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2017-07-31 zhangjun copy from mini2440
*/
#include <rtthread.h>
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
//stk = (rt_uint32_t*)stack_addr;
stack_addr += sizeof(rt_uint32_t);
stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
stk = (rt_uint32_t *)stack_addr;
*(--stk) = (rt_uint32_t)tentry; /* entry point */
*(--stk) = (rt_uint32_t)texit; /* ra */
*(--stk) = (rt_uint32_t)parameter; /* a0 */
*(--stk) = 0xffffffff; /* a1 */
*(--stk) = 0xffffffff; /* a2 */
*(--stk) = 0xffffffff; /* a3 */
*(--stk) = 0xffffffff; /* a4 */
*(--stk) = 0xffffffff; /* a5 */
*(--stk) = 0xffffffff; /* a6 */
*(--stk) = 0xffffffff; /* a7 */
*(--stk) = 0xffffffff; /* s0/fp */
*(--stk) = 0xffffffff; /* s1 */
*(--stk) = 0xffffffff; /* s2 */
*(--stk) = 0xffffffff; /* s3 */
*(--stk) = 0xffffffff; /* s4 */
*(--stk) = 0xffffffff; /* s5 */
*(--stk) = 0xffffffff; /* s6 */
*(--stk) = 0xffffffff; /* s7 */
*(--stk) = 0xffffffff; /* s8 */
*(--stk) = 0xffffffff; /* s9 */
*(--stk) = 0xffffffff; /* s10*/
*(--stk) = 0xffffffff; /* s11*/
*(--stk) = 0xffffffff; /* t0 */
*(--stk) = 0xffffffff; /* t1 */
*(--stk) = 0xffffffff; /* t2 */
*(--stk) = 0xffffffff; /* t3 */
*(--stk) = 0xffffffff; /* t4 */
*(--stk) = 0xffffffff; /* t5 */
*(--stk) = 0xffffffff; /* t6 */
*(--stk) = 0xffffffff; /* tp */
*(--stk) = 0xffffffff; /* gp */
*(--stk) = 0x880; /* mie */
// *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
libcpu/risc-v/e310/start_gcc.S 已删除 100644 → 0
浏览文件 @ 385ee9af
;/*
; * File : start_gcc.S
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2006, RT-Thread Development Team
; *
; * This program is free software; you can redistribute it and/or modify
; * it under the terms of the GNU General Public License as published by
; * the Free Software Foundation; either version 2 of the License, or
; * (at your option) any later version.
; *
; * This program is distributed in the hope that it will be useful,
; * but WITHOUT ANY WARRANTY; without even the implied warranty of
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; * GNU General Public License for more details.
; *
; * You should have received a copy of the GNU General Public License along
; * with this program; if not, write to the Free Software Foundation, Inc.,
; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
; *
; * Change Logs:
; * Date Author Notes
; * 2017-07-16 zhangjun for hifive1
; */
#include "sifive/smp.h"
#define CLINT_CTRL_ADDR 0x02000000
.section .init
.globl _start
.type _start,@function
_start:
.cfi_startproc
.cfi_undefined ra
.option push
.option norelax
la gp, __global_pointer$
.option pop
la sp, _sp
/*
*disable all interrupt at startup
*/
csrrc a5, mstatus, 0xb
#if defined(ENABLE_SMP)
smp_pause(t0, t1)
#endif
/* Load data section */
la a0, _data_lma
la a1, _data
la a2, _edata
bgeu a1, a2, 2f
1:
lw t0, (a0)
sw t0, (a1)
addi a0, a0, 4
addi a1, a1, 4
bltu a1, a2, 1b
2:
/* Clear bss section */
la a0, __bss_start
la a1, _end
bgeu a0, a1, 2f
1:
sw zero, (a0)
addi a0, a0, 4
bltu a0, a1, 1b
2:
/* Call global constructors */
la a0, __libc_fini_array
call atexit
call __libc_init_array
/*call _init directly in rt-thread*/
call _init
#ifndef __riscv_float_abi_soft
/* Enable FPU */
li t0, MSTATUS_FS
csrs mstatus, t0
csrr t1, mstatus
and t1, t1, t0
beqz t1, 1f
fssr x0
1:
#endif
#if defined(ENABLE_SMP)
smp_resume(t0, t1)
csrr a0, mhartid
bnez a0, 2f
#endif
auipc ra, 0
addi sp, sp, -16
#if __riscv_xlen == 32
sw ra, 8(sp)
#else
sd ra, 8(sp)
#endif
/* argc = argv = 0 */
li a0, 0
li a1, 0
call main
tail exit
1:
j 1b
#if defined(ENABLE_SMP)
2:
la t0, trap_entry
csrw mtvec, t0
csrr a0, mhartid
la t1, _sp
slli t0, a0, 10
sub sp, t1, t0
auipc ra, 0
addi sp, sp, -16
#if __riscv_xlen == 32
sw ra, 8(sp)
#else
sd ra, 8(sp)
#endif
call secondary_main
tail exit
1:
j 1b
#endif
.cfi_endproc
#include "encoding.h"
#include "sifive/bits.h"
.section .text.entry
.align 2
.global trap_entry
trap_entry:
addi sp, sp, -32*REGBYTES
STORE x30, 1*REGBYTES(sp)
STORE x31, 2*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp)
STORE x10, 29*REGBYTES(sp)
STORE x1, 30*REGBYTES(sp)
csrr x10, mepc
STORE x10, 31*REGBYTES(sp)
csrr x10, mie
STORE x10, 0*REGBYTES(sp)
/*
*Remain in M-mode after mret
*enable interrupt in M-mode
*/
li t0, MSTATUS_MPP
csrrs t0, mstatus, t0
call rt_interrupt_enter
csrr a0, mcause
lui a5, 0x80000
not a5, a5
and a5, a5, a0
li a4, 11
mv s1, a1
/*Machine external interrupt*/
bne a5, a4, 1f
call rt_hw_trap_irq
1:
/*Machine timer interrupt*/
li a4, 7
bne a5, a4, 2f
call rt_systick_handler
2:
call rt_interrupt_leave
la a0, rt_thread_switch_interrupt_flag
lw a1, (a0)
bnez a1, rt_hw_context_switch_interrupt_do
LOAD x30, 1*REGBYTES(sp)
LOAD x31, 2*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x29, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x10, 31*REGBYTES(sp)
csrw mepc,x10
LOAD x10, 0*REGBYTES(sp)
csrw mie, x10
LOAD x10, 29*REGBYTES(sp)
LOAD x1, 30*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret
rt_hw_context_switch_interrupt_do:
/*clear rt_thread_switch_interrupt_flag*/
la a0, rt_thread_switch_interrupt_flag
li a5, 0
sw a5, (a0)
LOAD a0, rt_interrupt_from_thread
STORE sp, (a0)
LOAD a0, rt_interrupt_to_thread
LOAD sp, (a0)
LOAD x30, 1*REGBYTES(sp)
LOAD x31, 2*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x29, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x10, 31*REGBYTES(sp)
csrw mepc,x10
LOAD x10, 0*REGBYTES(sp)
csrw mie, x10
LOAD x10, 29*REGBYTES(sp)
LOAD x1, 30*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret
libcpu/risc-v/e310/trap.c 已删除 100644 → 0
浏览文件 @ 385ee9af
#include <rtthread.h>
#include <rthw.h>
#include <platform.h>
#include <encoding.h>
#include "interrupt.h"
extern struct rt_irq_desc irq_desc[];
extern rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq);
void rt_hw_trap_irq()
{
rt_isr_handler_t isr_func;
rt_uint32_t irq;
void *param;
/* get irq number */
irq = rt_hw_interrupt_get_active(0);
/* get interrupt service routine */
isr_func = irq_desc[irq].handler;
param = irq_desc[irq].param;
/* turn to interrupt service routine */
isr_func(irq, param);
rt_hw_interrupt_ack(0, irq);
#ifdef RT_USING_INTERRUPT_INFO
irq_desc[irq].counter ++;
#endif
}
void handle_m_ext_interrupt()
{
}
void rt_systick_handler(void)
{
clear_csr(mie, MIP_MTIP);
// Reset the timer for 3s in the future.
// This also clears the existing timer interrupt.
volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME);
volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP);
uint64_t now = *mtime;
uint64_t then = now + 2 * RTC_FREQ/RT_TICK_PER_SECOND;
*mtimecmp = then;
rt_tick_increase();
// read the current value of the LEDS and invert them.
/*
GPIO_REG(GPIO_OUTPUT_VAL) ^= ((0x1 << RED_LED_OFFSET) |
(0x1 << GREEN_LED_OFFSET) |
(0x1 << BLUE_LED_OFFSET));
*/
// Re-enable the timer interrupt.
set_csr(mie, MIP_MTIP);
}
Markdown is supported
0% 或 .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑！
想要评论请 注册 或