[bsp] add es32f0334 bsp

bsp/es32f0334/.config

+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40001
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_MTD is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+
+#
+# Using WiFi
+#
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+# CONFIG_RT_USING_PTHREADS is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# Modbus master and slave stack
+#
+# CONFIG_RT_USING_MODBUS is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_LOGTRACE is not set
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_STM32F4_HAL is not set
+# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+
+#
+# sample package
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# example package: hello
+#
+# CONFIG_PKG_USING_HELLO is not set
+CONFIG_SOC_ES32F0334LT=y
+
+#
+# Hardware Drivers Config
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+
+#
+# UART Drivers
+#
+# CONFIG_BSP_USING_UART0 is not set
+CONFIG_BSP_USING_UART1=y
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# Offboard Peripheral Drivers
+#

bsp/es32f0334/Kconfig

+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_ES32F0334LT
+    bool
+    default y
+
+source "drivers/Kconfig"

bsp/es32f0334/README.md

+# ES-PDS-ES32F0334 开发板 BSP 说明
+标签： EastSoft、国产MCU、Cortex-M0、ES32F0334LT
+
+## 1. 简介
+
+本文档为上海东软载波微电子开发团队为 ES-PDS-ES32F0334 开发板提供的 BSP (板级支持包) 说明。
+通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
+
+### 1.1  开发板介绍
+
+主要内容如下：
+ES-PDS-ES32F0334 是东软载波微电子官方推出的一款基于 ARM Cortex-M0 内核的开发板，最高主频为 48MHz，可满足基础功能测试及高端功能扩展等开发需求。
+
+开发板外观如下图所示：
+
+ES-PDS-ES32F0334-V1.1
+
+![ES32F0334](figures/ES-PDS-ES32F0334-V1.1.jpg)
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：ES32F0334LT，主频 48MHz，32KB SRAM，256KB FLASH，54 GPIOs
+- 外部 FLASH：MX25L64（SPI，16MB）、EEPROM（24c04）
+- 常用外设
+  - LED：2个，(PA12/PC12)
+  - 液晶屏：1个
+  - 可调电阻：1个
+  - 按键：3个，K1(PF00)，K2（PF01)，RESET(MRST)
+- 常用接口：GPIO、UART、SPI、I2C
+- 调试接口，ESLinkⅡ(EastSoft 官方推出的开发工具，有标准版和mini版两种版本，均自带 CDC 串口功能) SWD 下载
+
+外设支持:
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设**      | **支持情况** | **备注**                             |
+| :---------------- | :----------: | :------------------------------------|
+
+| **片上外设**      | **支持情况** | **备注**                             |
+| :---------------- | :----------: | :------------------------------------|
+| GPIO              |     支持     | 54 GPIOs                             |
+| UART              |     支持     | UART0/1                              |
+
+| **扩展模块**      | **支持情况** | **备注**                             |
+
+更多详细信息请咨询[上海东软载波微电子技术支持](http://www.essemi.com/)
+
+## 2. 快速上手
+
+本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+### 硬件连接
+
+使用 ESLinkⅡ (自带 CDC 串口)或 Jlink 等调试工具连接开发板到 PC，拨动开关选择使用调试工具供电或使用外部电源供电。若使用 Jlink 等调试工具，还需要将 UART1_TX(PC10)、UART1_RX(PC11)、GND 接到串口工具上。
+
+使用ESlinkⅡ(mini)连接开发板如下图所示：
+
+ESLinkⅡ(mini) + ES-PDS-ES32F0334-V1.1
+
+![ESLinkII](figures/ESLinkII-mini.jpg)
+
+### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，工程默认配置使用 JLink 下载程序，在通过 JLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板，如果使用 ESLinkⅡ，则选择 "CMSIS-DAP Debugger"，连接正常后即可编译并下载程序到开发板。
+
+### 运行结果
+
+下载程序成功之后，系统会自动运行，观察串口输出的信息，同时开发板LED闪烁。
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.0 build Jan 28 2019
+ 2006 - 2018 Copyright by rt-thread team
+msh >
+```
+## 3. 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 uart1 的功能，如果需使用 Flash 等更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
+
+更多 Env 工具的详细介绍请参考 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/)
+
+## 4. 联系人信息
+
+- [wangyongquan](https://github.com/wangyq2018) 
+
+## 5. 参考
+
+- [ EastSoft 官网](http://www.essemi.com)
+

bsp/es32f0334/SConscript

+# for module compiling
+import os
+Import('RTT_ROOT')
+
+objs = []
+cwd = str(Dir('#'))
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/es32f0334/SConstruct

+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/es32f0334/applications/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+
+CPPPATH = [cwd, str(Dir('#'))]
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/es32f0334/applications/main.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-03-01     wangyq        the first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define LED_PIN 53
+
+int main(void)
+{
+    int count = 1;
+    /* set PC12 pin mode to output */
+    rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
+
+    while (count++)
+    {
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+    return RT_EOK;
+}

bsp/es32f0334/drivers/Kconfig

+menu "Hardware Drivers Config"
+
+    menu "On-chip Peripheral Drivers"
+        config BSP_USING_GPIO
+            bool "Enable GPIO"
+            select RT_USING_PIN
+            default y
+
+        menu "UART Drivers"
+            config BSP_USING_UART0
+                bool "Enable UART0 PB10/PB11(T/R)"
+                select RT_USING_SERIAL
+                default n
+
+            config BSP_USING_UART1
+                bool "Enable UART1 PC10/PC11(T/R)"
+                select RT_USING_SERIAL
+                default y
+
+        endmenu
+
+    endmenu
+
+    menu "Onboard Peripheral Drivers"
+
+    endmenu
+
+    menu "Offboard Peripheral Drivers"
+
+    endmenu
+
+endmenu

bsp/es32f0334/drivers/SConscript

+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split('''
+board.c
+''')
+
+# add gpio code
+if GetDepend('RT_USING_PIN'):
+    src += ['drv_gpio.c']
+
+# add serial driver code
+if  GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1'):
+    src += ['drv_uart.c']
+
+CPPPATH = [cwd]
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/es32f0334/drivers/board.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-03-01     wangyq        the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "board.h"
+#include "drv_uart.h"
+#include "drv_gpio.h"
+#include <ald_cmu.h>
+#include <ald_gpio.h>
+
+/**
+ * @addtogroup es32f0
+ */
+
+/*@{*/
+
+/*******************************************************************************
+* Function Name  : NVIC_Configuration
+* Description    : Configures Vector Table base location.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_Configuration(void)
+{
+}
+
+/*******************************************************************************
+ * Function Name  : SystemClock_Configuration
+ * Description    : Configures the System Clock.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void  SystemClock_Config(void)
+{
+    /* hosc 12MHz, from hosc/3 pll to 48MHz */
+    cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_48M);
+
+    /*  MCLK 48MHz*/
+    cmu_clock_config(CMU_CLOCK_PLL1, 48000000);
+}
+
+/*******************************************************************************
+ * Function Name  : SysTick_Configuration
+ * Description    : Configures the SysTick for OS tick.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void  SysTick_Configuration(void)
+{
+    rt_uint32_t _mclk;
+    rt_uint32_t _sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS);
+
+    /* get hrc clock*/
+    _mclk = cmu_get_clock();
+
+    /* SYSCLK = MCLK/SYSDIV */
+    SysTick_Config(_mclk / (RT_TICK_PER_SECOND << _sys_div));
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void systick_irq_cbk(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/*@}*/
+/**
+ * This function will initial ES32F0 board.
+ */
+void rt_hw_board_init(void)
+{
+    /* NVIC Configuration */
+    NVIC_Configuration();
+
+    /*System Clock Configuration */
+    SystemClock_Config();
+
+    /* Configure the SysTick */
+    SysTick_Configuration();
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+}

bsp/es32f0334/drivers/board.h

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-03-01     wangyq        the first version
+ */
+
+// <<< Use Configuration Wizard in Context Menu >>>
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <es32f033x.h>
+
+#define ES32F0_SRAM_SIZE    0x8000
+#define ES32F0_SRAM_END     (0x20000000 + ES32F0_SRAM_SIZE)
+
+#ifdef __CC_ARM
+    extern int Image$$RW_IRAM1$$ZI$$Limit;
+    #define HEAP_BEGIN  ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+    #pragma section="HEAP"
+    #define HEAP_BEGIN  (__segment_end("HEAP"))
+#else
+    extern int __bss_end;
+    #define HEAP_BEGIN  ((void *)&__bss_end)
+#endif
+
+#define HEAP_END    ES32F0_SRAM_END
+
+void rt_hw_board_init(void);
+
+#endif

bsp/es32f0334/drivers/drv_gpio.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-03-01     wangyq        the first version
+ */
+
+#include <rthw.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "drv_gpio.h"
+#include <ald_cmu.h>
+#include <ald_gpio.h>
+
+#ifdef RT_USING_PIN
+
+#define __ES32F0_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index}
+#define __ES32F0_PIN_DEFAULT {-1, 0, 0}
+
+/* ES32F0 GPIO driver */
+struct pin_index
+{
+    int index;
+    GPIO_TypeDef *gpio;
+    uint32_t pin;
+};
+
+static const struct pin_index pins[] =
+{
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN(2, C, 13),
+    __ES32F0_PIN(3, C, 14),
+    __ES32F0_PIN(4, C, 15),
+    __ES32F0_PIN(5, H, 0),
+    __ES32F0_PIN(6, H, 1),
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN(8, C, 0),
+    __ES32F0_PIN(9, C, 1),
+    __ES32F0_PIN(10, C, 2),
+    __ES32F0_PIN(11, C, 3),
+    __ES32F0_PIN(12, H, 3),
+    __ES32F0_PIN(13, H, 4),
+    __ES32F0_PIN(14, A, 0),
+    __ES32F0_PIN(15, A, 1),
+    __ES32F0_PIN(16, A, 2),
+    __ES32F0_PIN(17, A, 3),
+    __ES32F0_PIN(18, F, 0),
+    __ES32F0_PIN(19, F, 1),
+    __ES32F0_PIN(20, A, 4),
+    __ES32F0_PIN(21, A, 5),
+    __ES32F0_PIN(22, A, 6),
+    __ES32F0_PIN(23, A, 7),
+    __ES32F0_PIN(24, C, 4),
+    __ES32F0_PIN(25, C, 5),
+    __ES32F0_PIN(26, B, 0),
+    __ES32F0_PIN(27, B, 1),
+    __ES32F0_PIN(28, B, 2),
+    __ES32F0_PIN(29, B, 10),
+    __ES32F0_PIN(30, B, 11),
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN(33, B, 12),
+    __ES32F0_PIN(34, B, 13),
+    __ES32F0_PIN(35, B, 14),
+    __ES32F0_PIN(36, B, 15),
+    __ES32F0_PIN(37, C, 6),
+    __ES32F0_PIN(38, C, 7),
+    __ES32F0_PIN(39, C, 8),
+    __ES32F0_PIN(40, C, 9),
+    __ES32F0_PIN(41, A, 8),
+    __ES32F0_PIN(42, A, 9),
+    __ES32F0_PIN(43, A, 10),
+    __ES32F0_PIN(44, A, 11),
+    __ES32F0_PIN(45, A, 12),
+    __ES32F0_PIN(46, A, 13),
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN(49, A, 14),
+    __ES32F0_PIN(50, A, 15),
+    __ES32F0_PIN(51, C, 10),
+    __ES32F0_PIN(52, C, 11),
+    __ES32F0_PIN(53, C, 12),
+    __ES32F0_PIN(54, D, 2),
+    __ES32F0_PIN(55, B, 3),
+    __ES32F0_PIN(56, B, 4),
+    __ES32F0_PIN(57, B, 5),
+    __ES32F0_PIN(58, B, 6),
+    __ES32F0_PIN(59, B, 7),
+    __ES32F0_PIN(60, H, 2),
+    __ES32F0_PIN(61, B, 8),
+    __ES32F0_PIN(62, E, 1),
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN_DEFAULT,
+};
+
+struct pin_irq_map
+{
+    rt_uint16_t pinbit;
+    IRQn_Type irqno;
+};
+static const struct pin_irq_map pin_irq_map[] =
+{
+    {GPIO_PIN_0, EXTI0_3_IRQn},
+    {GPIO_PIN_1, EXTI0_3_IRQn},
+    {GPIO_PIN_2, EXTI0_3_IRQn},
+    {GPIO_PIN_3, EXTI0_3_IRQn},
+    {GPIO_PIN_4, EXTI4_7_IRQn},
+    {GPIO_PIN_5, EXTI4_7_IRQn},
+    {GPIO_PIN_6, EXTI4_7_IRQn},
+    {GPIO_PIN_7, EXTI4_7_IRQn},
+    {GPIO_PIN_8, EXTI8_11_IRQn},
+    {GPIO_PIN_9, EXTI8_11_IRQn},
+    {GPIO_PIN_10, EXTI8_11_IRQn},
+    {GPIO_PIN_11, EXTI8_11_IRQn},
+    {GPIO_PIN_12, EXTI12_15_IRQn},
+    {GPIO_PIN_13, EXTI12_15_IRQn},
+    {GPIO_PIN_14, EXTI12_15_IRQn},
+    {GPIO_PIN_15, EXTI12_15_IRQn},
+};
+
+struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+};
+
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+const struct pin_index *get_pin(uint8_t pin)
+{
+    const struct pin_index *index;
+    if (pin < ITEM_NUM(pins))
+    {
+        index = &pins[pin];
+        if (index->index == -1)
+            index = RT_NULL;
+    }
+    else
+    {
+        index = RT_NULL;
+    }
+    return index;
+};
+
+void es32f0_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    const struct pin_index *index;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+    gpio_write_pin(index->gpio, index->pin, value);
+}
+
+int es32f0_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    int value;
+    const struct pin_index *index;
+    value = PIN_LOW;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return value;
+    }
+    value = gpio_read_pin(index->gpio, index->pin);
+    return value;
+}
+
+void es32f0_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    const struct pin_index *index;
+    gpio_init_t gpio_initstruct;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    /* Configure GPIO_InitStructure */
+    gpio_initstruct.mode = GPIO_MODE_OUTPUT;
+    gpio_initstruct.func = GPIO_FUNC_1;
+    gpio_initstruct.odrv = GPIO_OUT_DRIVE_NORMAL;
+    gpio_initstruct.type = GPIO_TYPE_CMOS;
+    gpio_initstruct.pupd = GPIO_FLOATING;
+    gpio_initstruct.odos = GPIO_PUSH_PULL;
+
+    if (mode == PIN_MODE_OUTPUT)
+    {
+        /* output setting */
+        gpio_initstruct.mode = GPIO_MODE_OUTPUT;
+        gpio_initstruct.pupd = GPIO_FLOATING;
+    }
+    else if (mode == PIN_MODE_INPUT)
+    {
+        /* input setting: not pull. */
+        gpio_initstruct.mode = GPIO_MODE_INPUT;
+        gpio_initstruct.pupd = GPIO_FLOATING;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLUP)
+    {
+        /* input setting: pull up. */
+        gpio_initstruct.mode = GPIO_MODE_INPUT;
+        gpio_initstruct.pupd = GPIO_PUSH_UP;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLDOWN)
+    {
+        /* input setting: pull down. */
+        gpio_initstruct.mode = GPIO_MODE_INPUT;
+        gpio_initstruct.pupd = GPIO_PUSH_DOWN;
+    }
+    else if (mode == PIN_MODE_OUTPUT_OD)
+    {
+        /* output setting: od. */
+        gpio_initstruct.mode = GPIO_MODE_OUTPUT;
+        gpio_initstruct.pupd = GPIO_FLOATING;
+        gpio_initstruct.odos = GPIO_OPEN_DRAIN;
+    }
+    gpio_init(index->gpio, index->pin, &gpio_initstruct);
+}
+
+rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin)
+{
+    rt_int32_t mapindex = gpio_pin & 0x00FF;
+    if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_NULL;
+    }
+    return &pin_irq_map[mapindex];
+};
+
+rt_err_t es32f0_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                               rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+    /**pin no. convert to dec no.**/
+    for (irqindex = 0; irqindex < 16; irqindex++)
+    {
+        if ((0x01 << irqindex) == index->pin)
+        {
+            break;
+        }
+    }
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_ENOSYS;
+    }
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == pin &&
+            pin_irq_hdr_tab[irqindex].hdr == hdr &&
+            pin_irq_hdr_tab[irqindex].mode == mode &&
+            pin_irq_hdr_tab[irqindex].args == args)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    if (pin_irq_hdr_tab[irqindex].pin != -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EBUSY;
+    }
+    pin_irq_hdr_tab[irqindex].pin = pin;
+    pin_irq_hdr_tab[irqindex].hdr = hdr;
+    pin_irq_hdr_tab[irqindex].mode = mode;
+    pin_irq_hdr_tab[irqindex].args = args;
+    rt_hw_interrupt_enable(level);
+    return RT_EOK;
+}
+
+rt_err_t es32f0_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+    irqindex = index->pin & 0x00FF;
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_ENOSYS;
+    }
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    pin_irq_hdr_tab[irqindex].pin = -1;
+    pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+    pin_irq_hdr_tab[irqindex].mode = 0;
+    pin_irq_hdr_tab[irqindex].args = RT_NULL;
+    rt_hw_interrupt_enable(level);
+    return RT_EOK;
+}
+
+rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                               rt_uint32_t enabled)
+{
+    const struct pin_index *index;
+    const struct pin_irq_map *irqmap;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    /*Configure GPIO_InitStructure & EXTI_InitStructure*/
+    gpio_init_t gpio_initstruct;
+    exti_init_t exti_initstruct;
+    exti_initstruct.filter = DISABLE;
+    exti_initstruct.cks = EXTI_FILTER_CLOCK_10K;
+    exti_initstruct.filter_time = 0x0;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        /**pin no. convert to dec no.**/
+        for (irqindex = 0; irqindex < 16; irqindex++)
+        {
+            if ((0x01 << irqindex) == index->pin)
+            {
+                break;
+            }
+        }
+        if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+        {
+            return RT_ENOSYS;
+        }
+        level = rt_hw_interrupt_disable();
+        if (pin_irq_hdr_tab[irqindex].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_ENOSYS;
+        }
+        irqmap = &pin_irq_map[irqindex];
+        gpio_exti_init(index->gpio, index->pin, &exti_initstruct);
+        /* Configure GPIO_InitStructure */
+        gpio_initstruct.mode = GPIO_MODE_INPUT;
+        gpio_initstruct.func = GPIO_FUNC_1;
+        switch (pin_irq_hdr_tab[irqindex].mode)
+        {
+        case PIN_IRQ_MODE_RISING:
+            gpio_initstruct.pupd = GPIO_PUSH_DOWN;
+            gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_RISING_EDGE, ENABLE);
+            break;
+        case PIN_IRQ_MODE_FALLING:
+            gpio_initstruct.pupd = GPIO_PUSH_UP;
+            gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_TRAILING_EDGE, ENABLE);
+            break;
+        case PIN_IRQ_MODE_RISING_FALLING:
+            gpio_initstruct.pupd = GPIO_FLOATING;
+            gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_BOTH_EDGE, ENABLE);
+            break;
+        }
+        gpio_init(index->gpio, index->pin, &gpio_initstruct);
+        NVIC_EnableIRQ(irqmap->irqno);
+        rt_hw_interrupt_enable(level);
+    }
+    else if (enabled == PIN_IRQ_DISABLE)
+    {
+        irqmap = get_pin_irq_map(index->pin);
+        if (irqmap == RT_NULL)
+        {
+            return RT_ENOSYS;
+        }
+        NVIC_DisableIRQ(irqmap->irqno);
+    }
+    else
+    {
+        return RT_ENOSYS;
+    }
+    return RT_EOK;
+}
+
+const static struct rt_pin_ops _es32f0_pin_ops =
+{
+    es32f0_pin_mode,
+    es32f0_pin_write,
+    es32f0_pin_read,
+    es32f0_pin_attach_irq,
+    es32f0_pin_detach_irq,
+    es32f0_pin_irq_enable,
+};
+
+int rt_hw_pin_init(void)
+{
+    int result;
+    cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE);
+    result = rt_device_pin_register("pin", &_es32f0_pin_ops, RT_NULL);
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+rt_inline void pin_irq_hdr(uint16_t GPIO_Pin)
+{
+    uint16_t irqno;
+    /**pin no. convert to dec no.**/
+    for (irqno = 0; irqno < 16; irqno++)
+    {
+        if ((0x01 << irqno) == GPIO_Pin)
+        {
+            break;
+        }
+    }
+    if (irqno == 16)
+        return;
+    if (pin_irq_hdr_tab[irqno].hdr)
+    {
+        pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
+    }
+}
+
+void GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+    if (gpio_exti_get_flag_status(GPIO_Pin) != RESET)
+    {
+        gpio_exti_clear_flag_status(GPIO_Pin);
+        pin_irq_hdr(GPIO_Pin);
+    }
+}
+
+void EXTI0_3_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_0);
+    GPIO_EXTI_Callback(GPIO_PIN_1);
+    GPIO_EXTI_Callback(GPIO_PIN_2);
+    GPIO_EXTI_Callback(GPIO_PIN_3);
+    rt_interrupt_leave();
+}
+
+void EXTI4_7_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_4);
+    GPIO_EXTI_Callback(GPIO_PIN_5);
+    GPIO_EXTI_Callback(GPIO_PIN_6);
+    GPIO_EXTI_Callback(GPIO_PIN_7);
+    rt_interrupt_leave();
+}
+
+void EXTI8_11_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_8);
+    GPIO_EXTI_Callback(GPIO_PIN_9);
+    GPIO_EXTI_Callback(GPIO_PIN_10);
+    GPIO_EXTI_Callback(GPIO_PIN_11);
+    rt_interrupt_leave();
+}
+
+void EXTI12_15_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_12);
+    GPIO_EXTI_Callback(GPIO_PIN_13);
+    GPIO_EXTI_Callback(GPIO_PIN_14);
+    GPIO_EXTI_Callback(GPIO_PIN_15);
+    rt_interrupt_leave();
+}
+
+#endif

bsp/es32f0334/drivers/drv_gpio.h

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-03-01     wangyq        the first version
+ */
+
+#ifndef DRV_GPIO_H__
+#define DRV_GPIO_H__
+
+int rt_hw_pin_init(void);
+
+#endif

bsp/es32f0334/drivers/drv_uart.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-03-01     wangyq        the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "drv_uart.h"
+#include <ald_gpio.h>
+#include <ald_uart.h>
+
+#ifdef RT_USING_SERIAL
+
+/* es32 uart driver */
+struct es32_uart
+{
+    uart_handle_t huart;
+    IRQn_Type irq;
+};
+
+static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    gpio_init_t gpio_init_initstructure;
+    struct es32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+    uart = (struct es32_uart *)serial->parent.user_data;
+
+    /* Initialize tx pin */
+    gpio_init_initstructure.mode = GPIO_MODE_OUTPUT;
+    gpio_init_initstructure.odos = GPIO_PUSH_PULL;
+    gpio_init_initstructure.pupd = GPIO_PUSH_UP;
+    gpio_init_initstructure.odrv = GPIO_OUT_DRIVE_NORMAL;
+    gpio_init_initstructure.flt  = GPIO_FILTER_DISABLE;
+    gpio_init_initstructure.type = GPIO_TYPE_TTL;
+
+#ifdef BSP_USING_UART0
+    gpio_init_initstructure.func = GPIO_FUNC_3;
+    gpio_init(GPIOB, GPIO_PIN_10, &gpio_init_initstructure);
+
+    /* Initialize rx pin ,the same as txpin except mode*/
+    gpio_init_initstructure.mode = GPIO_MODE_INPUT;
+    gpio_init(GPIOB, GPIO_PIN_11, &gpio_init_initstructure);
+
+    NVIC_EnableIRQ(UART0_IRQn);
+
+#endif /* uart0 gpio init */
+
+#ifdef BSP_USING_UART1
+    /* Initialize tx pin */
+    gpio_init_initstructure.func = GPIO_FUNC_3;
+    gpio_init(GPIOC, GPIO_PIN_10, &gpio_init_initstructure);
+
+    /* Initialize rx pin ,the same as txpin except mode*/
+    gpio_init_initstructure.mode = GPIO_MODE_INPUT;
+    gpio_init(GPIOC, GPIO_PIN_11, &gpio_init_initstructure);
+
+    NVIC_EnableIRQ(UART1_IRQn);
+#endif /* uart1 gpio init */
+
+    uart->huart.init.mode        = UART_MODE_UART;
+    uart->huart.init.baud        = cfg->baud_rate;
+    uart->huart.init.word_length = (uart_word_length_t)(cfg->data_bits - 5);
+    uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity);
+    uart->huart.init.fctl        = UART_HW_FLOW_CTL_DISABLE;
+    uart_init(&uart->huart);
+
+    if (cfg->bit_order == BIT_ORDER_MSB)
+    {
+        UART_MSB_FIRST_ENABLE(&uart->huart);
+    }
+    else
+    {
+        UART_MSB_FIRST_DISABLE(&uart->huart);
+    }
+
+    if (cfg->invert == NRZ_INVERTED)
+    {
+        UART_DATA_INV_ENABLE(&uart->huart);
+    }
+    else
+    {
+        UART_DATA_INV_DISABLE(&uart->huart);
+    }
+
+    /*enable rx int*/
+    uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE);
+
+    return RT_EOK;
+}
+
+static rt_err_t es32f0x_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct es32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = (struct es32_uart *)serial->parent.user_data;
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        NVIC_DisableIRQ(uart->irq);
+        /* disable interrupt */
+        uart_interrupt_config(&uart->huart, UART_IT_RXRD, DISABLE);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        NVIC_EnableIRQ(uart->irq);
+        /* enable interrupt */
+        uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int es32f0x_putc(struct rt_serial_device *serial, char c)
+{
+    struct es32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct es32_uart *)serial->parent.user_data;
+
+    while (!(uart->huart.perh->SR & 0x40)) ;
+    WRITE_REG(uart->huart.perh->TBR, c);
+
+    return 1;
+}
+
+static int es32f0x_getc(struct rt_serial_device *serial)
+{
+    int ch = -1;
+    struct es32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct es32_uart *)serial->parent.user_data;
+
+    if (uart->huart.perh->SR & 0x01)
+    {
+        ch = (uint8_t)(uart->huart.perh->RBR & 0xFF);
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops es32f0x_uart_ops =
+{
+    es32f0x_configure,
+    es32f0x_control,
+    es32f0x_putc,
+    es32f0x_getc,
+};
+
+#ifdef BSP_USING_UART0
+/* UART0 device driver structure */
+struct es32_uart uart0 =
+{
+    {UART0},
+    UART0_IRQn
+};
+
+struct rt_serial_device serial0;
+
+void UART0_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if (UART0->RIF & 0x01)
+    {
+        rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART0 */
+
+#ifdef BSP_USING_UART1
+/* UART1 device driver structure */
+struct es32_uart uart1 =
+{
+    {UART1},
+    UART1_IRQn
+};
+
+struct rt_serial_device serial1;
+
+void UART1_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if (UART1->RIF & 0x01)
+    {
+        rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART1 */
+
+int rt_hw_uart_init(void)
+{
+    struct es32_uart *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef BSP_USING_UART0
+    uart = &uart0;
+    serial0.ops = &es32f0x_uart_ops;
+    serial0.config = config;
+
+    /* register UART0 device */
+    rt_hw_serial_register(&serial0, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART0 */
+
+#ifdef BSP_USING_UART1
+    uart = &uart1;
+    serial1.ops = &es32f0x_uart_ops;
+    serial1.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&serial1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART1 */
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_uart_init);
+
+#endif

bsp/es32f0334/drivers/drv_uart.h

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2019-03-01     wangyq        the first version
+ */
+
+#ifndef DRV_UART_H__
+#define DRV_UART_H__
+
+int rt_hw_uart_init(void);
+
+#endif

bsp/es32f0334/drivers/linker_scripts/link.sct

+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00040000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00040000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x00008000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

bsp/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Startup/iar/startup_es32f033x.s

+;*******************************************************************************
+; file       : startup_es32f033x.s
+; description: es32f033x Device Startup File
+; author     : AE Team
+; data       : 10 Dec 2018
+; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+;*******************************************************************************
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)				;0,  load top of stack
+        DCD     Reset_Handler				;1,  reset handler
+        DCD     NMI_Handler				;2,  nmi handler
+        DCD     HardFault_Handler			;3,  hard fault handler
+        DCD     0					;4,  MPU Fault Handler
+        DCD     0					;5,  Bus Fault Handler
+        DCD     0					;6,  Usage Fault Handler
+        DCD     0					;7,  Reserved
+        DCD     0					;8,  Reserved
+        DCD     0					;9,  Reserved
+        DCD     0					;10, Reserved
+        DCD     SVC_Handler				;11, svcall handler
+        DCD     DebugMon_Handler			;12, Debug Monitor Handler
+        DCD     0					;13, Reserved
+        DCD     PendSV_Handler				;14, pendsv handler
+        DCD     SysTick_Handler				;15, systick handler
+        DCD     WWDG_IWDG_Handler			;16, irq0    WWDG_IWDG handler
+        DCD     LVD_Handler				;17, irq1    LVD handler
+        DCD     RTC_TEMP_Handler			;18, irq2    RTC handler
+        DCD     CRYPT_TRNG_Handler			;19, irq3    CRYPT handler
+        DCD     CMU_Handler				;20, irq4    CMU handler
+        DCD     EXTI0_3_Handler				;21, irq5    EXTI0_3 handler
+        DCD     EXTI4_7_Handler				;22, irq6    EXTI4_7 handler
+        DCD     EXTI8_11_Handler			;23, irq7    EXTI8_11 handler
+        DCD     EXTI12_15_Handler			;24, irq8    EXTI12_15 handler
+        DCD     DMA_Handler				;25, irq9    DMA handler
+        DCD     CAN0_Handler				;26, irq10   CAN0_CRYPT_TRNG handler
+        DCD     LPTIM0_SPI2_Handler			;27, irq11   LPTIM0_SPI2 handler
+        DCD     ADC_ACMP_Handler			;28, irq12   ADC_ACMP handler
+        DCD     AD16C4T0_BRK_UP_TRIG_COM_Handler	;29, irq13   AD16C4T0_BRK_UP_TRIG_COM handler
+        DCD     AD16C4T0_CC_Handler			;30, irq14   AD16C4T0_CC handler
+        DCD     BS16T0_Handler				;31, irq15   BS16T0 handler
+        DCD     0					;32, irq16   Reserved
+        DCD     GP16C2T0_Handler			;33, irq17   GP16C2T0 handler
+        DCD     GP16C2T1_Handler			;34, irq18   GP16C2T1 handler
+        DCD     BS16T1_UART2_Handler			;35, irq19   BS16T1_UART2 handler
+        DCD     BS16T2_UART3_Handler			;36, irq20   BS16T2_UART3 handler
+        DCD     GP16C4T0_LCD_Handler			;37, irq21   GP16C4T0_LCD handler
+        DCD     BS16T3_DAC0_Handler			;38, irq22   BS16T3_DAC0  handler
+        DCD     I2C0_Handler				;39, irq23   I2C0 handler
+        DCD     I2C1_Handler				;40, irq24   I2C1 handler
+        DCD     SPI0_Handler				;41, irq25   SPI0 handler
+        DCD     SPI1_Handler				;42, irq26   SPI1 handler
+        DCD     UART0_Handler				;43, irq27   UART0 handler
+        DCD     UART1_Handler				;44, irq28   UART1 handler
+        DCD     USART0_Handler				;45, irq29   USART0 handler
+        DCD     USART1_Handler				;46, irq30   USART1 handler
+        DCD     LPUART0_Handler				;47, irq31   LPUART0 handler
+        
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =__iar_program_start
+        BX      R0
+        
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+		
+	PUBWEAK DebugMon_Handler
+	SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+	B DebugMon_Handler
+
+    	PUBWEAK PendSV_Handler
+    	SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+    	B PendSV_Handler
+
+   	PUBWEAK SysTick_Handler
+    	SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+    	B SysTick_Handler
+
+        PUBWEAK WWDG_IWDG_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IWDG_Handler
+        B WWDG_IWDG_Handler
+
+	PUBWEAK LVD_Handler
+	SECTION .text:CODE:NOROOT:REORDER(1)
+LVD_Handler
+	B LVD_Handler
+		
+	PUBWEAK RTC_TEMP_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_TEMP_Handler
+        B RTC_TEMP_Handler
+
+        PUBWEAK CRYPT_TRNG_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRYPT_TRNG_Handler
+        B CRYPT_TRNG_Handler
+
+        PUBWEAK CMU_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CMU_Handler
+        B CMU_Handler
+
+        PUBWEAK EXTI0_3_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_3_Handler
+        B EXTI0_3_Handler
+
+        PUBWEAK EXTI4_7_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_7_Handler
+        B EXTI4_7_Handler
+
+        PUBWEAK EXTI8_11_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI8_11_Handler
+        B EXTI8_11_Handler
+
+ 	PUBWEAK EXTI12_15_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI12_15_Handler
+        B EXTI12_15_Handler
+
+        PUBWEAK DMA_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA_Handler
+        B DMA_Handler
+
+        PUBWEAK CAN0_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_Handler
+        B CAN0_Handler
+
+        PUBWEAK LPTIM0_SPI2_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM0_SPI2_Handler
+        B LPTIM0_SPI2_Handler
+
+        PUBWEAK ADC_ACMP_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_ACMP_Handler
+        B ADC_ACMP_Handler
+
+        PUBWEAK AD16C4T0_BRK_UP_TRIG_COM_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AD16C4T0_BRK_UP_TRIG_COM_Handler
+        B AD16C4T0_BRK_UP_TRIG_COM_Handler
+
+        PUBWEAK AD16C4T0_CC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AD16C4T0_CC_Handler
+        B AD16C4T0_CC_Handler
+
+        PUBWEAK BS16T0_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BS16T0_Handler
+        B BS16T0_Handler
+
+        PUBWEAK GP16C2T0_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GP16C2T0_Handler
+        B GP16C2T0_Handler
+
+        PUBWEAK GP16C2T1_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GP16C2T1_Handler
+        B GP16C2T1_Handler
+
+        PUBWEAK BS16T1_UART2_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BS16T1_UART2_Handler
+        B BS16T1_UART2_Handler
+
+        PUBWEAK BS16T2_UART3_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BS16T2_UART3_Handler
+        B BS16T2_UART3_Handler
+
+        PUBWEAK GP16C4T0_LCD_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GP16C4T0_LCD_Handler
+        B GP16C4T0_LCD_Handler
+
+        PUBWEAK BS16T3_DAC0_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BS16T3_DAC0_Handler
+        B BS16T3_DAC0_Handler
+
+	PUBWEAK I2C0_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_Handler
+        B I2C0_Handler
+
+	PUBWEAK I2C1_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_Handler
+        B I2C1_Handler
+
+	PUBWEAK SPI0_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI0_Handler
+        B SPI0_Handler
+
+	PUBWEAK SPI1_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_Handler
+        B SPI1_Handler
+
+	PUBWEAK UART0_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART0_Handler
+        B UART0_Handler
+
+	PUBWEAK UART1_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART1_Handler
+        B UART1_Handler
+
+	PUBWEAK USART0_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART0_Handler
+        B USART0_Handler
+
+	PUBWEAK USART1_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_Handler
+        B USART1_Handler
+
+	PUBWEAK LPUART0_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART0_Handler
+        B LPUART0_Handler
+
+        END

bsp/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Startup/keil/startup_es32f033x.s

+;*******************************************************************************
+; file       : startup_es32f033x.s
+; description: es32f033x Device Startup File
+; author     : AE Team
+; data       : 29 Aug 2017
+; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+;*******************************************************************************
+
+;Stack Configuration------------------------------------------------------------
+Stack_Size      EQU     0x00000400
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+;-------------------------------------------------------------------------------
+
+;Heap Configuration-------------------------------------------------------------
+Heap_Size       EQU     0x00000000
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+;-------------------------------------------------------------------------------
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset-------------------------------------
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp                      ;0,  load top of stack
+                DCD     Reset_Handler                     ;1,  reset handler
+                DCD     NMI_Handler                       ;2,  nmi handler
+                DCD     HardFault_Handler                 ;3,  hard fault handler
+                DCD     0                                 ;4,  MPU Fault Handler
+                DCD     0                                 ;5,  Bus Fault Handler
+                DCD     0                                 ;6,  Usage Fault Handler
+                DCD     0                                 ;7,  Reserved
+                DCD     0                                 ;8,  Reserved
+                DCD     0                                 ;9,  Reserved
+                DCD     0                                 ;10, Reserved
+                DCD     SVC_Handler                       ;11, svcall handler
+                DCD     DebugMon_Handler                  ;12, Debug Monitor Handler
+                DCD     0                                 ;13, Reserved
+                DCD     PendSV_Handler                    ;14, pendsv handler
+                DCD     SysTick_Handler                   ;15, systick handler
+                DCD     WWDG_IWDG_Handler                 ;16, irq0    WWDG_IWDG handler
+                DCD     LVD_Handler                       ;17, irq1    LVD handler
+                DCD     RTC_TEMP_Handler                  ;18, irq2    RTC handler
+                DCD     CRYPT_TRNG_Handler                ;19, irq3    CRYPT handler
+                DCD     CMU_Handler                       ;20, irq4    CMU handler
+                DCD     EXTI0_3_Handler                   ;21, irq5    EXTI0_3 handler
+                DCD     EXTI4_7_Handler                   ;22, irq6    EXTI4_7 handler
+                DCD     EXTI8_11_Handler                  ;23, irq7    EXTI8_11 handler
+                DCD     EXTI12_15_Handler                 ;24, irq8    EXTI12_15 handler
+                DCD     DMA_Handler                       ;25, irq9    DMA handler
+                DCD     CAN0_Handler                      ;26, irq10   CAN0_CRYPT_TRNG handler
+                DCD     LPTIM0_SPI2_Handler               ;27, irq11   LPTIM0_SPI2 handler
+                DCD     ADC_ACMP_Handler                  ;28, irq12   ADC_ACMP handler
+                DCD     AD16C4T0_BRK_UP_TRIG_COM_Handler  ;29, irq13   AD16C4T0_BRK_UP_TRIG_COM handler
+                DCD     AD16C4T0_CC_Handler               ;30, irq14   AD16C4T0_CC handler
+                DCD     BS16T0_Handler		          ;31, irq15   BS16T0 handler
+                DCD     0             			  ;32, irq16   Reserved
+                DCD     GP16C2T0_Handler                  ;33, irq17   GP16C2T0 handler
+                DCD     GP16C2T1_Handler                  ;34, irq18   GP16C2T1 handler
+                DCD     BS16T1_UART2_Handler              ;35, irq19   BS16T1_UART2 handler
+                DCD     BS16T2_UART3_Handler              ;36, irq20   BS16T2_UART3 handler
+                DCD     GP16C4T0_LCD_Handler              ;37, irq21   GP16C4T0_LCD handler
+                DCD     BS16T3_DAC0_Handler               ;38, irq22   BS16T3_DAC0  handler
+                DCD     I2C0_Handler                      ;39, irq23   I2C0 handler
+                DCD     I2C1_Handler                      ;40, irq24   I2C1 handler
+                DCD     SPI0_Handler                      ;41, irq25   SPI0 handler
+                DCD     SPI1_Handler                      ;42, irq26   SPI1 handler
+                DCD     UART0_Handler                     ;43, irq27   UART0 handler
+                DCD     UART1_Handler                     ;44, irq28   UART1 handler
+                DCD     USART0_Handler                    ;45, irq29   USART0 handler
+                DCD     USART1_Handler                    ;46, irq30   USART1 handler
+                DCD     LPUART0_Handler                   ;47, irq31   LPUART0 handler
+
+;-------------------------------------------------------------------------------
+                AREA    INT, CODE, READONLY             ;code begin
+
+;Reset Handler----------------------------------------------
+Reset_Handler   PROC
+	EXPORT  Reset_Handler                  [WEAK]
+	IMPORT  __main
+	LDR     R0, =__main
+	BX      R0
+	NOP
+	ALIGN
+	ENDP
+
+;system int-------------------------------------------------
+NMI_Handler     PROC                           ;int 2
+	EXPORT  NMI_Handler                    [WEAK]
+	B       .
+	ENDP
+
+HardFault_Handler \
+	PROC                                   ;int3
+	EXPORT  HardFault_Handler              [WEAK]
+	B       .
+	ENDP
+
+SVC_Handler \
+	PROC                                   ;int11
+	EXPORT  SVC_Handler                    [WEAK]
+	B       .
+	ENDP
+
+DebugMon_Handler \
+	PROC                                   ;int12
+	EXPORT  DebugMon_Handler               [WEAK]
+	B       .
+	ENDP
+
+PendSV_Handler  PROC                           ;int14
+	EXPORT  PendSV_Handler                 [WEAK]
+	B       .
+	ENDP
+
+SysTick_Handler \
+	PROC                                   ;int15
+	EXPORT  SysTick_Handler                [WEAK]
+	B       .
+	ENDP
+
+;peripheral module int -----------------------------------------------
+WWDG_IWDG_Handler \
+	PROC                                   ;int16
+	EXPORT  WWDG_IWDG_Handler              [WEAK]
+	B       .
+	ENDP
+
+LVD_Handler \
+	PROC                                   ;int17
+	EXPORT  LVD_Handler                    [WEAK]
+	B       .
+	ENDP
+
+RTC_TEMP_Handler \
+	PROC                                   ;int18
+	EXPORT  RTC_TEMP_Handler               [WEAK]
+	B       .
+	ENDP
+
+CRYPT_TRNG_Handler \
+	PROC                                   ;int19
+	EXPORT  CRYPT_TRNG_Handler             [WEAK]
+	B       .
+	ENDP
+
+CMU_Handler \
+	PROC                                   ;int20
+	EXPORT  CMU_Handler                    [WEAK]
+	B       .
+	ENDP
+
+EXTI0_3_Handler \
+	PROC                                   ;int21
+	EXPORT  EXTI0_3_Handler                [WEAK]
+	B       .
+	ENDP
+
+EXTI4_7_Handler \
+	PROC                                   ;int22
+	EXPORT  EXTI4_7_Handler                [WEAK]
+	B       .
+	ENDP
+
+EXTI8_11_Handler \
+	PROC                                   ;int23
+	EXPORT  EXTI8_11_Handler               [WEAK]
+	B       .
+	ENDP
+
+EXTI12_15_Handler \
+	PROC                                   ;int24
+	EXPORT  EXTI12_15_Handler              [WEAK]
+	B       .
+	ENDP
+
+DMA_Handler \
+	PROC                                   ;int25
+	EXPORT  DMA_Handler                    [WEAK]
+	B       .
+	ENDP
+
+CAN0_Handler \
+	PROC                                   ;int26
+	EXPORT  CAN0_Handler                   [WEAK]
+	B       .
+	ENDP
+
+LPTIM0_SPI2_Handler \
+	PROC                                   ;int27
+	EXPORT  LPTIM0_SPI2_Handler            [WEAK]
+	B       .
+	ENDP
+
+ADC_ACMP_Handler \
+	PROC                                   ;int28
+	EXPORT  ADC_ACMP_Handler               [WEAK]
+	B       .
+	ENDP
+
+AD16C4T0_BRK_UP_TRIG_COM_Handler \
+	PROC                                     ;int29
+	EXPORT  AD16C4T0_BRK_UP_TRIG_COM_Handler [WEAK]
+	B       .
+	ENDP
+
+AD16C4T0_CC_Handler \
+	PROC                                   ;int30
+	EXPORT  AD16C4T0_CC_Handler            [WEAK]
+	B       .
+	ENDP
+
+BS16T0_Handler \
+	PROC                                   ;int31
+	EXPORT  BS16T0_Handler [WEAK]
+	B       .
+	ENDP
+
+GP16C2T0_Handler PROC                           ;int33
+	EXPORT  GP16C2T0_Handler                [WEAK]
+	B       .
+	ENDP
+
+GP16C2T1_Handler  PROC                          ;int34
+	EXPORT  GP16C2T1_Handler                [WEAK]
+	B       .
+	ENDP
+
+BS16T1_UART2_Handler \
+	PROC                                   ;int35
+	EXPORT  BS16T1_UART2_Handler           [WEAK]
+	B       .
+	ENDP
+
+BS16T2_UART3_Handler \
+	PROC                                   ;int36
+	EXPORT  BS16T2_UART3_Handler           [WEAK]
+	B       .
+	ENDP
+
+GP16C4T0_LCD_Handler \
+	PROC                                   ;int37
+	EXPORT  GP16C4T0_LCD_Handler           [WEAK]
+	B       .
+	ENDP
+
+BS16T3_DAC0_Handler \
+	PROC                                   ;int38
+	EXPORT  BS16T3_DAC0_Handler            [WEAK]
+	B       .
+	ENDP
+
+I2C0_Handler \
+	PROC                                   ;int39
+	EXPORT  I2C0_Handler                   [WEAK]
+	B       .
+	ENDP
+
+I2C1_Handler \
+	PROC                                   ;int40
+	EXPORT  I2C1_Handler                   [WEAK]
+	B       .
+	ENDP
+
+SPI0_Handler \
+	PROC                                   ;int41
+	EXPORT  SPI0_Handler                   [WEAK]
+	B       .
+	ENDP
+
+SPI1_Handler \
+	PROC                                   ;int42
+	EXPORT  SPI1_Handler                   [WEAK]
+	B       .
+	ENDP
+
+UART0_Handler \
+	PROC                                   ;int43
+	EXPORT  UART0_Handler                  [WEAK]
+	B       .
+	ENDP
+
+UART1_Handler \
+	PROC                                   ;int44
+	EXPORT  UART1_Handler                  [WEAK]
+	B       .
+	ENDP
+
+USART0_Handler \
+	PROC                                   ;int45
+	EXPORT  USART0_Handler                 [WEAK]
+	B       .
+	ENDP
+
+USART1_Handler \
+	PROC                                   ;int46
+	EXPORT  USART1_Handler                 [WEAK]
+	B       .
+	ENDP
+
+LPUART0_Handler \
+	PROC                                   ;int47
+	EXPORT  LPUART0_Handler                [WEAK]
+	B       .
+	ENDP
+
+; User Initial Stack & Heap-----------------------------------------------------
+	ALIGN
+	IF      :DEF:__MICROLIB
+
+	EXPORT  __initial_sp
+	EXPORT  __heap_base
+	EXPORT  __heap_limit
+
+	ELSE
+
+	IMPORT  __use_two_region_memory
+	EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+	LDR     R0, =  Heap_Mem
+	LDR     R1, = (Stack_Mem + Stack_Size)
+	LDR     R2, = (Heap_Mem +  Heap_Size)
+	LDR     R3, = Stack_Mem
+	BX      LR
+
+	ALIGN
+
+	ENDIF
+
+	END

bsp/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/System/system_es32f033x.c

+/**
+  *********************************************************************************
+  *
+  * @file    system_es32f033x.c
+  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer
+  *
+  * @version V1.0
+  * @date    6 Dec 2018
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  *********************************************************************************
+  */
+
+#include "utils.h"
+
+
+/**
+  * @brief  Configuring system clock before startup.
+  * @note   This function must be used after reset.
+  * @retval None
+  */
+void system_init (void)
+{
+	/* do nothing */
+}
\ No newline at end of file

bsp/es32f0334/libraries/CMSIS/Include/SConscript

+Import('ES32_SDK_ROOT')
+
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+include_path  = [cwd]
+
+group = DefineGroup('CMSIS2', src, depend = [''], CPPPATH = include_path)
+
+Return('group')

bsp/es32f0334/libraries/CMSIS/Include/arm_common_tables.h

+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. October 2015
+* $Revision: 	V.1.4.5 a
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+/* extern const q31_t realCoefAQ31[1024]; */
+/* extern const q31_t realCoefBQ31[1024]; */
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */

bsp/es32f0334/libraries/CMSIS/Include/arm_const_structs.h

+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif

bsp/es32f0334/libraries/CMSIS/Include/core_cmFunc.h

+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */

bsp/es32f0334/libraries/CMSIS/Include/core_cmInstr.h

+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

bsp/es32f0334/libraries/CMSIS/Include/core_cmSimd.h

+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */

bsp/es32f0334/libraries/CMSIS/index.html

+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<title>Redirect to the CMSIS main page after 0 seconds</title>
+<meta http-equiv="refresh" content="0; URL=Documentation/General/html/index.html">
+<meta name="keywords" content="automatic redirection">
+</head>
+
+<body>
+
+If the automatic redirection is failing, click <a href="Documentation/General/html/index.html">open CMSIS Documentation</a>.
+
+</body>
+</html>