提交 c5fd1aaf 编写于 作者: B Bernard Xiong

Merge branch 'master' of https://github.com/RT-Thread/rt-thread

......@@ -18,8 +18,8 @@ if rtconfig.CROSS_TOOL == 'gcc':
src = src + ['CMSIS/ST/STM32F4xx/Source/Templates/gcc_ride7/startup_stm32f4xx.s']
elif rtconfig.CROSS_TOOL == 'keil':
src = src + ['CMSIS/ST/STM32F4xx/Source/Templates/arm/startup_stm32f4xx.s']
# elif rtconfig.CROSS_TOOL == 'iar':
# src = src + ['CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/iar/' + startup_scripts[rtconfig.STM32_TYPE]]
elif rtconfig.CROSS_TOOL == 'iar':
src = src + ['CMSIS/ST/STM32F4xx/Source/Templates/iar/startup_stm32f4xx.s']
path = [cwd + '/STM32F4xx_StdPeriph_Driver/inc',
cwd + '/CMSIS/ST/STM32F4xx/Include',
......
......@@ -6,4 +6,20 @@ note:
in drivers/stm32f4xx_conf.h
/* Redefine the HSE value; it's equal to 8 MHz on the STM32F4-DISCOVERY Kit */
#define HSE_VALUE ((uint32_t)8000000)
**================= IAR WARNING =================**
after use `scons --target=iar -s` cmd to product IAR project, you have to add iar link file by hand
IAR steps:
1. Project-->Options-->Linker
2. Config-->Linker Configuration file
3. select `Override Default`, then select `bsp/stm32f40x/stm32f40x_flash.icf`
4. rebuild project
**TODO**
auto add *.icf by scons script
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; /*STM32 F446RE*/
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x200;
define symbol __ICFEDIT_size_heap__ = 0x000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
keep { section FSymTab };
keep { section VSymTab };
keep { section .rti_fn* };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite, block CSTACK, last block HEAP};
......@@ -25,7 +25,7 @@
#include <rtthread.h>
#include "board.h"
#include "sram.h"
#include "drv_mpu.h"
/**
* @addtogroup STM32
......@@ -165,7 +165,7 @@ void HAL_ResumeTick(void)
void rt_hw_board_init()
{
/* Configure the MPU attributes as Write Through */
//mpu_init();
mpu_init();
/* Enable the CPU Cache */
CPU_CACHE_Enable();
......
......@@ -81,4 +81,4 @@ int mpu_init(void)
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
return 0;
}
INIT_BOARD_EXPORT(mpu_init);
//INIT_BOARD_EXPORT(mpu_init);
......@@ -96,7 +96,8 @@ struct romfs_dirent *dfs_romfs_lookup(struct romfs_dirent *root_dirent, const ch
{
if (check_dirent(&dirent[index]) != 0)
return RT_NULL;
if (rt_strncmp(dirent[index].name, subpath, (subpath_end - subpath)) == 0)
if (rt_strlen(dirent[index].name) == (subpath_end - subpath) &&
rt_strncmp(dirent[index].name, subpath, (subpath_end - subpath)) == 0)
{
dirent_size = dirent[index].size;
......
......@@ -234,7 +234,7 @@ int cmd_mkfs(int argc, char **argv)
if (strcmp(argv[1], "-t") == 0)
{
type = argv[2];
result = dfs_mkfs(type, argv[1]);
result = dfs_mkfs(type, argv[3]);
}
}
else
......
......@@ -425,7 +425,7 @@ void finsh_thread_entry(void *parameter)
if (rt_device_read(shell->device, 0, &next, 1) == 1)
{
if (next == '\0') ch = 'r'; /* linux telnet will issue '\0' */
if (next == '\0') ch = '\r'; /* linux telnet will issue '\0' */
else ch = next;
}
else ch = '\r';
......
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