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提交 518bdc44 编写于 作者: wuyangyong's avatar wuyangyong
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update lpc2148 startup_gcc.S 

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1584 bbd45198-f89e-11dd-88c7-29a3b14d5316
上级 b4bc59f9
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Showing with 85 addition and 123 deletion
libcpu/arm/lpc214x/startup_gcc.S
浏览文件 @ 518bdc44
.extern main /* 引入外部C入口 */ .extern main /* 引入外部C入口 */
.extern __bss_beg__
.extern __bss_end
.extern __stack_end__
.extern __data_beg__
.extern __data_end__
.extern __data+beg_src__
.extern rt_interrupt_enter .extern rt_interrupt_enter
.extern rt_interrupt_leave .extern rt_interrupt_leave
.extern rt_thread_switch_interrput_flag .extern rt_thread_switch_interrput_flag
...@@ -18,19 +11,6 @@ ...@@ -18,19 +11,6 @@
.global endless_loop .global endless_loop
.global rt_hw_context_switch_interrupt_do .global rt_hw_context_switch_interrupt_do
/************* 目标配置 *************/
.set UND_STACK_SIZE, 0x00000004
.set ABT_STACK_SIZE, 0x00000004
.set FIQ_STACK_SIZE, 0x00000004
.set IRQ_STACK_SIZE, 0x00000400
.set SVC_STACK_SIZE, 0x00000400
.set UND_Stack_Size, 0x00000004
.set ABT_Stack_Size, 0x00000004
.set FIQ_Stack_Size, 0x00000004
.set IRQ_Stack_Size, 0x00000400
.set SVC_Stack_Size, 0x00000400
/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */ /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
.set MODE_USR, 0x10 /* User Mode */ .set MODE_USR, 0x10 /* User Mode */
.set MODE_FIQ, 0x11 /* FIQ Mode */ .set MODE_FIQ, 0x11 /* FIQ Mode */
...@@ -39,13 +19,6 @@ ...@@ -39,13 +19,6 @@
.set MODE_ABT, 0x17 /* Abort Mode */ .set MODE_ABT, 0x17 /* Abort Mode */
.set MODE_UND, 0x1B /* Undefined Mode */ .set MODE_UND, 0x1B /* Undefined Mode */
.set MODE_SYS, 0x1F /* System Mode */ .set MODE_SYS, 0x1F /* System Mode */
.set MODE_USR, 0x10 /* User Mode */
.set Mode_FIQ, 0x11 /* FIQ Mode */
.set Mode_IRQ, 0x12 /* IRQ Mode */
.set Mode_SVC, 0x13 /* Supervisor Mode */
.set Mode_ABT, 0x17 /* Abort Mode */
.set Mode_UND, 0x1B /* Undefined Mode */
.set Mode_SYS, 0x1F /* System Mode */
.equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */ .equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
.equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */ .equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
...@@ -57,18 +30,17 @@ ...@@ -57,18 +30,17 @@
.set VPBDIV_VALUE, 0x00000000 .set VPBDIV_VALUE, 0x00000000
/* Phase Locked Loop (PLL) definitions*/ /* Phase Locked Loop (PLL) definitions*/
.equ PLL_BASE, 0xE01FC080 .equ PLL_BASE, 0xE01FC080 /* PLL Base Address */
.equ PLLCON_OFS, 0x00 .equ PLLCON_OFS, 0x00 /* PLL Control Offset */
.equ PLLCFG_OFS, 0x04 .equ PLLCFG_OFS, 0x04 /* PLL Configuration Offset */
.equ PLLSTAT_OFS, 0x08 .equ PLLSTAT_OFS, 0x08 /* PLL Status Offset */
.equ PLLFEED_OFS, 0x0C .equ PLLFEED_OFS, 0x0C /* PLL Feed Offset */
.equ PLLCON_PLLE, (1<<0) /* PLL Enable */
.equ PLLCON_PLLE, (1<<0) /* PLL Enable */ .equ PLLCON_PLLC, (1<<1) /* PLL Connect */
.equ PLLCON_PLLC, (1<<1) /* PLL Connect */ .equ PLLCFG_MSEL, (0x1F<<0) /* PLL Multiplier */
.equ PLLSTAT_LOCK, (1<<10) /* PLL Lock Status */ .equ PLLCFG_PSEL, (0x03<<5) /* PLL Divider */
//.equ PLLCFG_MSEL, ((PLL_MUL - 1) << 0) .equ PLLSTAT_PLOCK, (1<<10) /* PLL Lock Status */
.equ PLLCFG_PSEL, (0x02 << 5) .equ PLLCFG_Val, 0x00000024 /* <o1.0..4> MSEL: PLL Multiplier Selection,<o1.5..6> PSEL: PLL Divider Selection */
//.equ PLLCFG_Val, (PLLCFG_MSEL|PLLCFG_PSEL)
.equ MEMMAP, 0xE01FC040 /*Memory Mapping Control*/ .equ MEMMAP, 0xE01FC040 /*Memory Mapping Control*/
...@@ -87,19 +59,12 @@ ...@@ -87,19 +59,12 @@
/* Setup the operating mode & stack.*/ /* Setup the operating mode & stack.*/
/* --------------------------------- */ /* --------------------------------- */
.global _start, start, _reset, reset, .global _reset
.func _start,
_start:
start:
_reset: _reset:
reset:
.code 32 .code 32
.align 0 .align 0
/************************* PLL_SETUP **********************************/ /************************* PLL_SETUP **********************************/
#if (PLL_MUL>1)
ldr r0, =PLL_BASE ldr r0, =PLL_BASE
mov r1, #0xAA mov r1, #0xAA
mov r2, #0x55 mov r2, #0x55
...@@ -115,7 +80,7 @@ reset: ...@@ -115,7 +80,7 @@ reset:
/* Wait until PLL Locked */ /* Wait until PLL Locked */
PLL_Locked_loop: PLL_Locked_loop:
ldr r3, [r0, #PLLSTAT_OFS] ldr r3, [r0, #PLLSTAT_OFS]
ands r3, r3, #PLLSTAT_LOCK ands r3, r3, #PLLSTAT_PLOCK
beq PLL_Locked_loop beq PLL_Locked_loop
/* Switch to PLL Clock */ /* Switch to PLL Clock */
...@@ -123,8 +88,6 @@ PLL_Locked_loop: ...@@ -123,8 +88,6 @@ PLL_Locked_loop:
str r3, [r0, #PLLCON_OFS] str r3, [r0, #PLLCON_OFS]
str r1, [r0, #PLLFEED_OFS] str r1, [r0, #PLLFEED_OFS]
str R2, [r0, #PLLFEED_OFS] str R2, [r0, #PLLFEED_OFS]
#endif
/************************* PLL_SETUP **********************************/ /************************* PLL_SETUP **********************************/
/************************ Setup VPBDIV ********************************/ /************************ Setup VPBDIV ********************************/
...@@ -142,105 +105,104 @@ PLL_Locked_loop: ...@@ -142,105 +105,104 @@ PLL_Locked_loop:
/************** Setup MAM **************/ /************** Setup MAM **************/
/************************ setup stack *********************************/ /************************ setup stack *********************************/
ldr r0, .LC6 /* LC6:__stack_end__ */ ldr r0, .undefined_stack_top
sub r0, r0, #4
msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */ msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
mov sp, r0 mov sp, r0
sub r0, r0, #UND_STACK_SIZE
ldr r0, .abort_stack_top
sub r0, r0, #4
msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */ msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
mov sp, r0 mov sp, r0
sub r0, r0, #ABT_STACK_SIZE
ldr r0, .fiq_stack_top
sub r0, r0, #4
msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */ msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
mov sp, r0 mov sp, r0
sub r0, r0, #FIQ_STACK_SIZE
ldr r0, .irq_stack_top
sub r0, r0, #4
msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */ msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
mov sp, r0 mov sp, r0
sub r0, r0, #IRQ_STACK_SIZE
ldr r0, .svc_stack_top
sub r0, r0, #4
msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */ msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
mov sp, r0 mov sp, r0
/************************ setup stack ********************************/ /************************ setup stack ********************************/
/************************ Clear BSS ********************************/ /* copy .data to SRAM */
/* Clear BSS. */ ldr r1, =_sidata /* .data start in image */
ldr r2, =_edata /* .data end in image */
mov a2, #0 /* Fill value */ ldr r3, =_sdata /* sram data start */
mov fp, a2 /* Null frame pointer */ data_loop:
mov r7, a2 /* Null frame pointer for Thumb */ ldr r0, [r1, #0]
str r0, [r3]
ldr r1, .LC1 /* Start of memory block */
ldr r3, .LC2 /* End of memory block */ add r1, r1, #4
subs r3, r3, r1 /* Length of block */ add r3, r3, #4
beq .end_clear_loop
mov r2, #0 cmp r3, r2 /* check if data to clear */
blo data_loop /* loop until done */
.clear_loop:
strb r2, [r1], #1 /* clear .bss */
subs r3, r3, #1 mov r0,#0 /* get a zero */
bgt .clear_loop ldr r1,=__bss_start /* bss start */
ldr r2,=__bss_end /* bss end */
.end_clear_loop:
bss_loop:
/* Initialise data. */ cmp r1,r2 /* check if data to clear */
strlo r0,[r1],#4 /* clear 4 bytes */
ldr r1, .LC3 /* Start of memory block */ blo bss_loop /* loop until done */
ldr r2, .LC4 /* End of memory block */
ldr r3, .LC5
subs r3, r3, r1 /* Length of block */ /* call C++ constructors of global objects */
beq .end_set_loop ldr r0, =__ctors_start__
ldr r1, =__ctors_end__
.set_loop:
ldrb r4, [r2], #1 ctor_loop:
strb r4, [r1], #1 cmp r0, r1
subs r3, r3, #1 beq ctor_end
bgt .set_loop ldr r2, [r0], #4
stmfd sp!, {r0-r1}
.end_set_loop: mov lr, pc
bx r2
mov r0, #0 /* no arguments */ ldmfd sp!, {r0-r1}
mov r1, #0 /* no argv either */ b ctor_loop
ctor_end:
/* enter C code */
bl main bl main
endless_loop:
b endless_loop
.align 0 .align 0
.undefined_stack_top:
.LC1: .word _undefined_stack_top
.word __bss_beg__ .abort_stack_top:
.LC2: .word _abort_stack_top
.word __bss_end .fiq_stack_top:
.LC3: .word _fiq_stack_top
.word __data_beg__ .irq_stack_top:
.LC4: .word _irq_stack_top
.word __data_beg_src__ .svc_stack_top:
.LC5: .word _svc_stack_top
.word __data_end__
.LC6:
.word __stack_end__
/*********************** END Clear BSS ******************************/ /*********************** END Clear BSS ******************************/
/******************** 跳转到 main() ********************/ .section .init,"ax"
LDR R0, =main /* 获得main()入口地址 */ .code 32
BX R0 /* 长跳转到main() */ .align 0
/******************** 跳转到 main() ********************/ .globl _start
_start:
/* 本段为.startup段 在链接脚本中被链接到程序最开头 */
.section .startup,"ax"
.code 32
.align 0
ldr pc, __start /* reset - _start */ ldr pc, __start /* reset - _start */
ldr pc, _undf /* undefined - _undf */ ldr pc, _undf /* undefined - _undf */
ldr pc, _swi /* SWI - _swi */ ldr pc, _swi /* SWI - _swi */
ldr pc, _pabt /* program abort - _pabt */ ldr pc, _pabt /* program abort - _pabt */
ldr pc, _dabt /* data abort - _dabt */ ldr pc, _dabt /* data abort - _dabt */
//.word 0xB9205F80 /* 默认 0xB9205F80 */ .word 0xB8A06F58 /* reserved */
.word 0xB8A06F58 /* 0xB8A06F58 全为 */
ldr pc, __IRQ_Handler /* IRQ - read the VIC */ ldr pc, __IRQ_Handler /* IRQ - read the VIC */
ldr pc, _fiq /* FIQ - _fiq */ ldr pc, _fiq /* FIQ - _fiq */
__start:.word _start __start:.word _reset
_undf: .word __undf /* undefined */ _undf: .word __undf /* undefined */
_swi: .word __swi /* SWI */ _swi: .word __swi /* SWI */
_pabt: .word __pabt /* program abort */ _pabt: .word __pabt /* program abort */
......
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