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rt-thread
提交 4a9c3fae 编写于 作者: A Arda
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Merge pull request #3 from RT-Thread/master 

sync with official source
上级 5fe489a3 89ceb7dc
展开全部 隐藏空白更改
内联 并排
Showing with 201326 addition and 123758 deletion

要显示的变更太多。

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文本差异 电子邮件补丁
bsp/lpc176x/rtthread-lpc17xx.ld
浏览文件 @ 4a9c3fae
...@@ -43,6 +43,21 @@ SECTIONS ...@@ -43,6 +43,21 @@ SECTIONS
__rt_init_end = .; __rt_init_end = .;
. = ALIGN(4); . = ALIGN(4);
PROVIDE(__ctors_start__ = .);
/* old GCC version uses .ctors */
KEEP(*(SORT(.ctors.*)))
KEEP(*(.ctors))
/* new GCC version uses .init_array */
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
/* section information for modules */
. = ALIGN(4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
. = ALIGN(4); . = ALIGN(4);
_etext = .; _etext = .;
} > CODE = 0 } > CODE = 0
......
bsp/lpc178x/drivers/board.c
浏览文件 @ 4a9c3fae
...@@ -65,7 +65,7 @@ void rt_hw_board_init() ...@@ -65,7 +65,7 @@ void rt_hw_board_init()
#endif #endif
/* init systick */ /* init systick */
SysTick_Config( SystemCoreClock/RT_TICK_PER_SECOND - 1); SysTick_Config(SystemCoreClock/RT_TICK_PER_SECOND);
/* set pend exception priority */ /* set pend exception priority */
NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1); NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
......
bsp/lpc408x/applications/application.c
浏览文件 @ 4a9c3fae
...@@ -14,7 +14,11 @@ ...@@ -14,7 +14,11 @@
#include <rtthread.h> #include <rtthread.h>
#include <board.h> #ifdef RT_USING_FINSH
#include <shell.h>
#include <finsh.h>
#endif
#ifdef RT_USING_COMPONENTS_INIT #ifdef RT_USING_COMPONENTS_INIT
#include <components.h> #include <components.h>
#endif #endif
...@@ -25,12 +29,8 @@ void rt_init_thread_entry(void *parameter) ...@@ -25,12 +29,8 @@ void rt_init_thread_entry(void *parameter)
/* Initialization RT-Thread Components */ /* Initialization RT-Thread Components */
#ifdef RT_USING_COMPONENTS_INIT #ifdef RT_USING_COMPONENTS_INIT
rt_components_init(); rt_components_init();
#endif #elif defined(RT_USING_FINSH)
#ifdef RT_USING_FINSH
/* initialize finsh */
finsh_system_init(); finsh_system_init();
finsh_set_device(FINSH_DEVICE_NAME);
#endif #endif
} }
......
bsp/lpc408x/applications/board.c
浏览文件 @ 4a9c3fae
...@@ -52,7 +52,7 @@ void rt_hw_board_init() ...@@ -52,7 +52,7 @@ void rt_hw_board_init()
#endif #endif
/* init systick */ /* init systick */
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND - 1); SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
/* set pend exception priority */ /* set pend exception priority */
NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1); NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
/*init uart device*/ /*init uart device*/
......
bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/ARM/startup_LPC43xx_M0.s
浏览文件 @ 4a9c3fae
...@@ -96,10 +96,10 @@ __Vectors DCD __initial_sp ; 0 Top of Stack ...@@ -96,10 +96,10 @@ __Vectors DCD __initial_sp ; 0 Top of Stack
DCD ADC1_IRQHandler ; 37 ADC1 DCD ADC1_IRQHandler ; 37 ADC1
DCD SSP0_OR_SSP1_IRQHandler ; 38 SSP0 or SSP1 DCD SSP0_OR_SSP1_IRQHandler ; 38 SSP0 or SSP1
DCD EVENTROUTER_IRQHandler ; 39 Event router DCD EVENTROUTER_IRQHandler ; 39 Event router
DCD USART0_IRQHandler ; 40 USART0 DCD UART0_IRQHandler ; 40 USART0
DCD UART1_IRQHandler ; 41 UART1/Modem DCD UART1_IRQHandler ; 41 UART1/Modem
DCD USART2_OR_C_CAN1_IRQHandler ; 42 USART2 or C CAN1 DCD UART2_OR_C_CAN1_IRQHandler ; 42 USART2 or C CAN1
DCD USART3_IRQHandler ; 43 USART3 DCD UART3_IRQHandler ; 43 USART3
DCD I2S0_OR_I2S1_OR_QEI_IRQHandler ; 44 I2S0 or I2S1 or QEI DCD I2S0_OR_I2S1_OR_QEI_IRQHandler ; 44 I2S0 or I2S1 or QEI
DCD C_CAN0_IRQHandler ; 45 C CAN0 DCD C_CAN0_IRQHandler ; 45 C CAN0
DCD 0 ; 46 Reserved DCD 0 ; 46 Reserved
...@@ -175,10 +175,10 @@ Default_Handler PROC ...@@ -175,10 +175,10 @@ Default_Handler PROC
EXPORT ADC1_IRQHandler [WEAK] EXPORT ADC1_IRQHandler [WEAK]
EXPORT SSP0_OR_SSP1_IRQHandler [WEAK] EXPORT SSP0_OR_SSP1_IRQHandler [WEAK]
EXPORT EVENTROUTER_IRQHandler [WEAK] EXPORT EVENTROUTER_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK] EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK] EXPORT UART1_IRQHandler [WEAK]
EXPORT USART2_OR_C_CAN1_IRQHandler [WEAK] EXPORT UART2_OR_C_CAN1_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK] EXPORT UART3_IRQHandler [WEAK]
EXPORT I2S0_OR_I2S1_OR_QEI_IRQHandler [WEAK] EXPORT I2S0_OR_I2S1_OR_QEI_IRQHandler [WEAK]
EXPORT C_CAN0_IRQHandler [WEAK] EXPORT C_CAN0_IRQHandler [WEAK]
...@@ -206,10 +206,10 @@ SPI_OR_DAC_IRQHandler ...@@ -206,10 +206,10 @@ SPI_OR_DAC_IRQHandler
ADC1_IRQHandler ADC1_IRQHandler
SSP0_OR_SSP1_IRQHandler SSP0_OR_SSP1_IRQHandler
EVENTROUTER_IRQHandler EVENTROUTER_IRQHandler
USART0_IRQHandler UART0_IRQHandler
UART1_IRQHandler UART1_IRQHandler
USART2_OR_C_CAN1_IRQHandler UART2_OR_C_CAN1_IRQHandler
USART3_IRQHandler UART3_IRQHandler
I2S0_OR_I2S1_OR_QEI_IRQHandler I2S0_OR_I2S1_OR_QEI_IRQHandler
C_CAN0_IRQHandler C_CAN0_IRQHandler
......
bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx.s
浏览文件 @ 4a9c3fae
...@@ -109,30 +109,56 @@ __interrupt_vector: ...@@ -109,30 +109,56 @@ __interrupt_vector:
.type Reset_Handler, %function .type Reset_Handler, %function
Reset_Handler: Reset_Handler:
.fnstart .fnstart
.ifdef RAM_MODE /* Single section scheme.
/* Clear .bss section (Zero init) */ *
mov R0, #0 * The ranges of copy from/to are specified by following symbols
ldr R1, =__bss_start__ * _sidata: LMA of start of the section to copy from. Usually end of text
ldr R2, =__bss_end__ * _sdata: VMA of start of the section to copy to
cmp R1,R2 * _edata: VMA of end of the section to copy to
beq BSSIsEmpty *
LoopZI: * All addresses must be aligned to 4 bytes boundary.
cmp R1, R2 */
bhs BSSIsEmpty ldr r1, =_sidata
str R0, [R1] ldr r2, =_sdata
add R1, #4 ldr r3, =_edata
blo LoopZI
BSSIsEmpty: subs r3, r2
ldr R0, =SystemInit ble .L_loop1_done
blx R0
ldr R0,=main .L_loop1:
bx R0 subs r3, #4
.else ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .L_loop1
.L_loop1_done:
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start: start of the BSS section.
* __bss_end: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start
ldr r2, =__bss_end
movs r0, 0
subs r2, r1
ble .L_loop3_done
.L_loop3:
subs r2, #4
str r0, [r1, r2]
bgt .L_loop3
.L_loop3_done:
ldr R0, =SystemInit ldr R0, =SystemInit
blx R0 blx R0
ldr R0,=main ldr R0,=main
bx R0 bx R0
.endif
.pool .pool
.cantunwind .cantunwind
......
bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/GCC/startup_LPC43xx_M0.s
浏览文件 @ 4a9c3fae
...@@ -6,9 +6,9 @@ ...@@ -6,9 +6,9 @@
.syntax unified .syntax unified
.cpu cortex-m0 .cpu cortex-m0
.fpu softvfp .arch armv6-m
.thumb .thumb
.word _sidata .word _sidata
.word _sdata .word _sdata
.word _edata .word _edata
...@@ -43,59 +43,38 @@ __interrupt_vector: ...@@ -43,59 +43,38 @@ __interrupt_vector:
.long SysTick_Handler /* SysTick Handler */ .long SysTick_Handler /* SysTick Handler */
/* External Interrupts */ /* External Interrupts */
.long DAC_IRQHandler /* 16 D/A Converter */ .long RTC_IRQHandler /* 16 D/A Converter */
.long M4CORE_IRQHandler /* 17 M0 Core */ .long M4CORE_IRQHandler /* 17 M0 Core */
.long DMA_IRQHandler /* 18 General Purpose DMA */ .long DMA_IRQHandler /* 18 General Purpose DMA */
.long EZH_IRQHandler /* 19 EZH/EDM */ .long 0 /* 19 EZH/EDM */
.long FLASH_EEPROM_IRQHandler /* 20 Reserved for Typhoon */ .long FLASHEEPROMAT_IRQHandler /* 20 Reserved for Typhoon */
.long ETH_IRQHandler /* 21 Ethernet */ .long ETH_IRQHandler /* 21 Ethernet */
.long SDIO_IRQHandler /* 22 SD/MMC */ .long SDIO_IRQHandler /* 22 SD/MMC */
.long LCD_IRQHandler /* 23 LCD */ .long LCD_IRQHandler /* 23 LCD */
.long USB0_IRQHandler /* 24 USB0 */ .long USB0_IRQHandler /* 24 USB0 */
.long USB1_IRQHandler /* 25 USB1 */ .long USB1_IRQHandler /* 25 USB1 */
.long SCT_IRQHandler /* 26 State Configurable Timer */ .long SCT_IRQHandler /* 26 State Configurable Timer */
.long RIT_IRQHandler /* 27 Repetitive Interrupt Timer*/ .long RIT_OR_WWDT_IRQHandler /* 27 Repetitive Interrupt Timer*/
.long TIMER0_IRQHandler /* 28 Timer0 */ .long TIMER0_IRQHandler /* 28 Timer0 */
.long TIMER1_IRQHandler /* 29 Timer1 */ .long GINT1_IRQHandler /* 29 Timer1 */
.long TIMER2_IRQHandler /* 30 Timer2 */ .long PIN_INT4_IRQHandler /* 30 Timer2 */
.long TIMER3_IRQHandler /* 31 Timer3 */ .long TIMER3_IRQHandler /* 31 Timer3 */
.long MCPWM_IRQHandler /* 32 Motor Control PWM */ .long MCPWM_IRQHandler /* 32 Motor Control PWM */
.long ADC0_IRQHandler /* 33 A/D Converter 0 */ .long ADC0_IRQHandler /* 33 A/D Converter 0 */
.long I2C0_IRQHandler /* 34 I2C0 */ .long I2C0_OR_I2C1_IRQHandler /* 34 I2C0 */
.long I2C1_IRQHandler /* 35 I2C1 */ .long SGPIO_IRQHandler /* 35 I2C1 */
.long SPI_IRQHandler /* 36 SPI */ .long SPI_OR_DAC_IRQHandler /* 36 SPI */
.long ADC1_IRQHandler /* 37 A/D Converter 1 */ .long ADC1_IRQHandler /* 37 A/D Converter 1 */
.long SSP0_IRQHandler /* 38 SSP0 */ .long SSP0_OR_SSP1_IRQHandler /* 38 SSP0 */
.long SSP1_IRQHandler /* 39 SSP1 */ .long EVENTROUTER_IRQHandler /* 39 SSP1 */
.long UART0_IRQHandler /* 40 UART0 */ .long UART0_IRQHandler /* 40 UART0 */
.long UART1_IRQHandler /* 41 UART1 */ .long UART1_IRQHandler /* 41 UART1 */
.long UART2_IRQHandler /* 42 UART2 */ .long UART2_OR_C_CAN1_IRQHandler /* 42 UART2 */
.long UART3_IRQHandler /* 43 UART3 */ .long UART3_IRQHandler /* 43 UART3 */
.long I2S0_IRQHandler /* 44 I2S0 */ .long I2S0_OR_I2S1_OR_QEI_IRQHandler /* 44 I2S0 */
.long I2S1_IRQHandler /* 45 I2S1 */ .long C_CAN0_IRQHandler /* 45 I2S1 */
.long SPIFI_IRQHandler /* 46 SPI Flash Interface */ .long 0 /* 46 SPI Flash Interface */
.long SGPIO_IRQHandler /* 47 SGPIO */ .long 0 /* 47 SGPIO */
.long GPIO0_IRQHandler /* 48 GPIO0 */
.long GPIO1_IRQHandler /* 49 GPIO1 */
.long GPIO2_IRQHandler /* 50 GPIO2 */
.long GPIO3_IRQHandler /* 51 GPIO3 */
.long GPIO4_IRQHandler /* 52 GPIO4 */
.long GPIO5_IRQHandler /* 53 GPIO5 */
.long GPIO6_IRQHandler /* 54 GPIO6 */
.long GPIO7_IRQHandler /* 55 GPIO7 */
.long GINT0_IRQHandler /* 56 GINT0 */
.long GINT1_IRQHandler /* 57 GINT1 */
.long EVRT_IRQHandler /* 58 Event Router */
.long CAN1_IRQHandler /* 59 C_CAN1 */
.long 0 /* 60 Reserved */
.long VADC_IRQHandler /* 61 VADC */
.long ATIMER_IRQHandler /* 62 ATIMER */
.long RTC_IRQHandler /* 63 RTC */
.long 0 /* 64 Reserved */
.long WDT_IRQHandler /* 65 WDT */
.long M0s_IRQHandler /* 66 M0s */
.long CAN0_IRQHandler /* 67 C_CAN0 */
.long QEI_IRQHandler /* 68 QEI */
.size __interrupt_vector, . - __interrupt_vector .size __interrupt_vector, . - __interrupt_vector
...@@ -109,30 +88,56 @@ __interrupt_vector: ...@@ -109,30 +88,56 @@ __interrupt_vector:
.type Reset_Handler, %function .type Reset_Handler, %function
Reset_Handler: Reset_Handler:
.fnstart .fnstart
.ifdef RAM_MODE /* Single section scheme.
/* Clear .bss section (Zero init) */ *
mov R0, #0 * The ranges of copy from/to are specified by following symbols
ldr R1, =__bss_start__ * _sidata: LMA of start of the section to copy from. Usually end of text
ldr R2, =__bss_end__ * _sdata: VMA of start of the section to copy to
cmp R1,R2 * _edata: VMA of end of the section to copy to
beq BSSIsEmpty *
LoopZI: * All addresses must be aligned to 4 bytes boundary.
cmp R1, R2 */
bhs BSSIsEmpty ldr r1, =_sidata
str R0, [R1] ldr r2, =_sdata
add R1, #4 ldr r3, =_edata
blo LoopZI
BSSIsEmpty: subs r3, r2
ldr R0, =SystemInit ble .L_loop1_done
blx R0
ldr R0,=main .L_loop1:
bx R0 subs r3, #4
.else ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .L_loop1
.L_loop1_done:
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start: start of the BSS section.
* __bss_end: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start
ldr r2, =__bss_end
movs r0, 0
subs r2, r1
ble .L_loop3_done
.L_loop3:
subs r2, #4
str r0, [r1, r2]
bgt .L_loop3
.L_loop3_done:
ldr R0, =SystemInit ldr R0, =SystemInit
blx R0 blx R0
ldr R0,=main ldr R0,=main
bx R0 bx R0
.endif
.pool .pool
.cantunwind .cantunwind
...@@ -211,56 +216,34 @@ Default_Handler: ...@@ -211,56 +216,34 @@ Default_Handler:
.set \handler, Default_Handler .set \handler, Default_Handler
.endm .endm
IRQ DAC_IRQHandler IRQ RTC_IRQHandler
IRQ M0CORE_IRQHandler IRQ M4CORE_IRQHandler
IRQ DMA_IRQHandler IRQ DMA_IRQHandler
IRQ EZH_IRQHandler IRQ FLASHEEPROMAT_IRQHandler
IRQ FLASH_EEPROM_IRQHandler
IRQ ETH_IRQHandler IRQ ETH_IRQHandler
IRQ SDIO_IRQHandler IRQ SDIO_IRQHandler
IRQ LCD_IRQHandler IRQ LCD_IRQHandler
IRQ USB0_IRQHandler IRQ USB0_IRQHandler
IRQ USB1_IRQHandler IRQ USB1_IRQHandler
IRQ SCT_IRQHandler IRQ SCT_IRQHandler
IRQ RIT_IRQHandler IRQ RIT_OR_WWDT_IRQHandler
IRQ TIMER0_IRQHandler IRQ TIMER0_IRQHandler
IRQ TIMER1_IRQHandler IRQ GINT1_IRQHandler
IRQ TIMER2_IRQHandler IRQ PIN_INT4_IRQHandler
IRQ TIMER3_IRQHandler IRQ TIMER3_IRQHandler
IRQ MCPWM_IRQHandler IRQ MCPWM_IRQHandler
IRQ ADC0_IRQHandler IRQ ADC0_IRQHandler
IRQ I2C0_IRQHandler IRQ I2C0_OR_I2C1_IRQHandler
IRQ I2C1_IRQHandler IRQ SGPIO_IRQHandler
IRQ SPI_IRQHandler IRQ SPI_OR_DAC_IRQHandler
IRQ ADC1_IRQHandler IRQ ADC1_IRQHandler
IRQ SSP0_IRQHandler IRQ SSP0_OR_SSP1_IRQHandler
IRQ SSP1_IRQHandler IRQ EVENTROUTER_IRQHandler
IRQ UART0_IRQHandler IRQ UART0_IRQHandler
IRQ UART1_IRQHandler IRQ UART1_IRQHandler
IRQ UART2_IRQHandler IRQ UART2_OR_C_CAN1_IRQHandler
IRQ UART3_IRQHandler IRQ UART3_IRQHandler
IRQ I2S0_IRQHandler IRQ I2S0_OR_I2S1_OR_QEI_IRQHandler
IRQ I2S1_IRQHandler IRQ C_CAN0_IRQHandler
IRQ SPIFI_IRQHandler
IRQ SGPIO_IRQHandler
IRQ GPIO0_IRQHandler
IRQ GPIO1_IRQHandler
IRQ GPIO2_IRQHandler
IRQ GPIO3_IRQHandler
IRQ GPIO4_IRQHandler
IRQ GPIO5_IRQHandler
IRQ GPIO6_IRQHandler
IRQ GPIO7_IRQHandler
IRQ GINT0_IRQHandler
IRQ GINT1_IRQHandler
IRQ EVRT_IRQHandler
IRQ CAN1_IRQHandler
IRQ VADC_IRQHandler
IRQ ATIMER_IRQHandler
IRQ RTC_IRQHandler
IRQ WDT_IRQHandler
IRQ M0s_IRQHandler
IRQ CAN0_IRQHandler
IRQ QEI_IRQHandler
.end .end
bsp/lpc43xx/Libraries/Device/NXP/LPC43xx/Source/Templates/system_LPC43xx.c
浏览文件 @ 4a9c3fae
...@@ -869,6 +869,7 @@ void SystemCoreClockUpdate (void) { ...@@ -869,6 +869,7 @@ void SystemCoreClockUpdate (void) {
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
void SystemInit (void) { void SystemInit (void) {
#ifdef BOOT_PROCESSOR
#if (__FPU_USED == 1) #if (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */ (3UL << 11*2) ); /* set CP11 Full Access */
...@@ -880,9 +881,10 @@ void SystemInit (void) { ...@@ -880,9 +881,10 @@ void SystemInit (void) {
/* Configure PLL0 and PLL1, connect CPU clock to selected clock source */ /* Configure PLL0 and PLL1, connect CPU clock to selected clock source */
SetClock(); SetClock();
/* Update SystemCoreClock variable */
SystemCoreClockUpdate();
/* Configure External Memory Controller */ /* Configure External Memory Controller */
SystemInit_ExtMemCtl (); SystemInit_ExtMemCtl ();
#endif
/* Update SystemCoreClock variable */
SystemCoreClockUpdate();
} }
bsp/lpc43xx/M0/SConscript
浏览文件 @ 4a9c3fae
...@@ -2,12 +2,16 @@ from building import * ...@@ -2,12 +2,16 @@ from building import *
cwd = GetCurrentDir() cwd = GetCurrentDir()
objs = [] objs = []
list = os.listdir(os.path.join(cwd, '..'))
for d in list: for d in os.listdir(os.path.join(cwd, '..')):
if (d != 'M4' and d != 'M0'): if d not in ('M0', 'M4'):
path = os.path.join(cwd, '..', d) path = os.path.join('..', d, 'SConscript')
if os.path.isfile(os.path.join(path, 'SConscript')): if os.path.isfile(os.path.join(cwd, path)):
objs = objs + SConscript(os.path.join(path, 'SConscript')) objs = objs + SConscript(os.path.join(cwd, path))
for d in os.listdir(cwd):
p = os.path.join(d, 'SConscript');
if os.path.isfile(os.path.join(cwd, p)):
objs = objs + SConscript(p)
Return('objs') Return('objs')
bsp/lpc43xx/M0/SConstruct
浏览文件 @ 4a9c3fae
...@@ -5,7 +5,7 @@ import rtconfig ...@@ -5,7 +5,7 @@ import rtconfig
if os.getenv('RTT_ROOT'): if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT') RTT_ROOT = os.getenv('RTT_ROOT')
else: else:
RTT_ROOT = os.path.join(Dir('#').get_abspath(), '..', '..', 'rt-thread') RTT_ROOT = os.path.join(Dir('#').get_abspath(), '..', '..', '..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import * from building import *
...@@ -25,5 +25,23 @@ Export('rtconfig') ...@@ -25,5 +25,23 @@ Export('rtconfig')
# prepare building environment # prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
if rtconfig.CROSS_TOOL == 'gcc':
import glob
# Remove the .o for M0 left on the drivers dir.
for i in glob.glob(GetCurrentDir() + '/../drivers/*.o'):
print 'RM %s' % i
os.unlink(i)
if sys.platform.startswith('linux'):
import glob
ocwd = os.getcwdu()
res = os.system('cd ../Libraries/; find -name \*.o -exec rm {} \;')
os.chdir(ocwd)
else:
# Assume Windows.
ocwd = os.getcwdu()
print 'TODO: remove the object files in ../Libraries'
os.chdir(ocwd)
# do building # do building
DoBuilding(TARGET, objs) DoBuilding(TARGET, objs)
bsp/lpc43xx/applications/application.c → bsp/lpc43xx/M0/applications/application.c
浏览文件 @ 4a9c3fae
...@@ -16,46 +16,84 @@ ...@@ -16,46 +16,84 @@
#include <board.h> #include <board.h>
#include <rtdevice.h> #include <rtdevice.h>
#include "drv_led.h" #include "drv_led.h"
#ifdef RT_USING_FINSH #ifdef RT_USING_FINSH
#include <finsh.h> #include <finsh.h>
#include <shell.h> #include <shell.h>
#endif #endif
#ifdef RT_USING_LOGTRACE
#include <log_trace.h>
#endif
#ifdef RT_USING_VBUS
#include <vbus.h>
#endif
/* thread phase init */ /* thread phase init */
void rt_init_thread_entry(void *parameter) void rt_init_thread_entry(void *parameter)
{ {
#ifdef RT_USING_LOGTRACE
log_trace_init();
log_trace_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#ifdef RT_USING_FINSH #ifdef RT_USING_FINSH
/* initialize finsh */ /* initialize finsh */
finsh_system_init(); finsh_system_init();
finsh_set_device(RT_CONSOLE_DEVICE_NAME); finsh_set_device(RT_CONSOLE_DEVICE_NAME);
#endif #endif
#ifdef RT_USING_VBUS
rt_vbus_do_init();
#endif
} }
/*the led thread*/ /*the led thread*/
ALIGN(RT_ALIGN_SIZE) ALIGN(RT_ALIGN_SIZE)
static rt_uint8_t led_stack[ 512 ]; static rt_uint8_t led_stack[1024];
static struct rt_thread led_thread; static struct rt_thread led_thread;
static void led_thread_entry(void *parameter) static void led_thread_entry(void *parameter)
{ {
rt_uint8_t led_value = 0;
rt_device_t led_dev; rt_device_t led_dev;
rt_device_t vbus_dev;
rt_err_t err;
rt_led_hw_init(); rt_led_hw_init();
led_dev = rt_device_find("led"); led_dev = rt_device_find("led");
if (led_dev == RT_NULL) if (led_dev == RT_NULL)
{ {
rt_kprintf("can not find the led device!\n"); rt_kprintf("can not find the led device\n");
return; return;
} }
vbus_dev = rt_device_find("vecho");
if (vbus_dev == RT_NULL)
{
rt_kprintf("can not find the vbus device\n");
return;
}
err = rt_device_open(vbus_dev, RT_DEVICE_OFLAG_RDWR);
if (err != RT_EOK)
{
rt_kprintf("open vbus failed: %d\n", err);
return;
}
while (1) while (1)
{ {
/* led0 on */ rt_uint8_t led_value;
led_value = 1; int len;
led_dev->write(led_dev, 0, &led_value, 1);
rt_thread_delay(RT_TICK_PER_SECOND / 2); /* sleep 0.5 second and switch to other thread */ len = rt_device_read(vbus_dev, 0, &led_value, sizeof(led_value));
if (len <= 0)
/* led0 off */ {
led_value = 0; rt_kprintf("vbus read err: %d, %d\n", len, rt_get_errno());
led_dev->write(led_dev, 0, &led_value, 1); }
rt_thread_delay(RT_TICK_PER_SECOND / 2);
led_dev->write(led_dev, 1, &led_value, sizeof(led_value));
} }
} }
...@@ -65,20 +103,19 @@ int rt_application_init(void) ...@@ -65,20 +103,19 @@ int rt_application_init(void)
rt_err_t result; rt_err_t result;
tid = rt_thread_create("init", tid = rt_thread_create("init",
rt_init_thread_entry, RT_NULL, rt_init_thread_entry, RT_NULL,
2048, RT_THREAD_PRIORITY_MAX / 3, 20); 2048, 3, 20);
if (tid != RT_NULL) rt_thread_startup(tid); if (tid != RT_NULL)
rt_thread_startup(tid);
/* init led thread */ /* init led thread */
result = rt_thread_init(&led_thread, result = rt_thread_init(&led_thread, "led",
"led", led_thread_entry, RT_NULL,
led_thread_entry, (rt_uint8_t *)&led_stack[0], sizeof(led_stack),
RT_NULL, 20, 5);
(rt_uint8_t *)&led_stack[0],
sizeof(led_stack),
20,
5);
if (result == RT_EOK) if (result == RT_EOK)
{ {
rt_thread_startup(&led_thread); rt_thread_startup(&led_thread);
} }
return 0; return 0;
} }
bsp/lpc43xx/M0/applications/board.c 0 → 100644
浏览文件 @ 4a9c3fae
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2014 RT-Thread Develop Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard first implementation
* 2014-06-20 xiaonong ported to LPC43xx
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
#include "drv_uart.h"
/** M0 does not have SysTick so we have to use RIT timer for it... */
void RIT_OR_WWDT_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
if (LPC_RITIMER->CTRL & 0x01)
{
rt_tick_increase();
LPC_RITIMER->CTRL |= 0x01;
}
/* leave interrupt */
rt_interrupt_leave();
}
extern void SystemCoreClockUpdate(void);
/**
* This function will initial LPC43xx board.
*/
void rt_hw_board_init()
{
SystemCoreClockUpdate();
/* Setup RIT timer. */
LPC_RITIMER->MASK = 0;
LPC_RITIMER->COMPVAL = SystemCoreClock / RT_TICK_PER_SECOND;
/* Enable auto-clear. */
LPC_RITIMER->CTRL |= 1 << 1;
/* Reset the counter as the counter is enabled after reset. */
LPC_RITIMER->COUNTER = 0;
NVIC_SetPriority(M0_RITIMER_OR_WWDT_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
NVIC_EnableIRQ(M0_RITIMER_OR_WWDT_IRQn);
/* set pend exception priority */
NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
/* init uart device */
rt_hw_uart_init();
/* setup the console device */
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
}
bsp/lpc43xx/M0/applications/board.h 0 → 100644
浏览文件 @ 4a9c3fae
/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-09-22 Bernard add board.h to this bsp
* 2010-02-04 Magicoe add board.h to LPC176x bsp
* 2013-12-18 Bernard porting to LPC4088 bsp
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include "LPC43xx.h"
#include <rtthread.h>
/* disable SDRAM in default */
#ifndef LPC_EXT_SDRAM
#define LPC_EXT_SDRAM 0
#endif
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
// <integer name="LPC_EXT_SDRAM" description="Begin Address of External SDRAM" default="0xA0000000" />
#define LPC_EXT_SDRAM_BEGIN 0xA0000000
// <integer name="LPC_EXT_SDRAM_END" description="End Address of External SDRAM" default="0xA2000000" />
#define LPC_EXT_SDRAM_END 0xA2000000
// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
// <bool name="RT_USING_UART1" description="Using UART1" default="true" />
//#define RT_USING_UART1
// <bool name="RT_USING_UART2" description="Using UART2" default="true" />
//#define RT_USING_UART2
// </RDTConfigurator>
#ifdef __CC_ARM
extern int Image$$RW_IRAM2$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM2$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define HEAP_BEGIN ((void *)&__bss_end)
#endif
#define HEAP_END (void*)(0x10080000 + 0x8000)
void rt_hw_board_init(void);
int rt_hw_board_heap_init(void);
int rt_vbus_do_init(void);
#endif
bsp/lpc43xx/M0/applications/vbus_conf.h 0 → 100644
浏览文件 @ 4a9c3fae
#ifndef __VBUS_CONF_H__
#define __VBUS_CONF_H__
/* Number of blocks in VBus. The total size of VBus is
* RT_VMM_RB_BLK_NR * 64byte * 2. */
#define RT_VMM_RB_BLK_NR 20
/* We don't use the IRQ number to trigger IRQ in this BSP. */
#define RT_VBUS_GUEST_VIRQ 0
#define RT_VBUS_HOST_VIRQ 0
#endif /* end of include guard: __VBUS_CONF_H__ */
bsp/lpc43xx/M0/applications/vbus_drv.c 0 → 100644
浏览文件 @ 4a9c3fae
/*
* VMM Bus Driver
*
* COPYRIGHT (C) 2015, Shanghai Real-Thread Technology Co., Ltd
* http://www.rt-thread.com
*
* This file is part of RT-Thread (http://www.rt-thread.org)
*
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2015-01-07 Grissiom add comment
*/
#include <rtthread.h>
#ifdef RT_USING_VBUS
#include <rtdevice.h>
#include <vbus.h>
#include <board.h>
struct rt_vbus_ring rt_vbus_rings[2] SECTION("vbus_ring");
int rt_vbus_do_init(void)
{
return rt_vbus_init(&rt_vbus_rings[1], &rt_vbus_rings[0]);
}
INIT_COMPONENT_EXPORT(rt_vbus_do_init);
int rt_vbus_hw_init(void)
{
NVIC_ClearPendingIRQ(M0_M4CORE_IRQn);
NVIC_EnableIRQ(M0_M4CORE_IRQn);
return 0;
}
void M4CORE_IRQHandler(void)
{
LPC_CREG->M4TXEVENT = 0;
rt_vbus_isr(M0_M4CORE_IRQn, RT_NULL);
}
int rt_vbus_hw_eoi(int irqnr, void *param)
{
/* Nothing to do here as we cleared the interrupt in IRQHandler. */
return 0;
}
struct rt_vbus_dev rt_vbus_chn_devx[] = {
{
.req =
{
.prio = 30,
.name = "vecho",
.is_server = 0,
.recv_wm.low = RT_VMM_RB_BLK_NR / 3,
.recv_wm.high = RT_VMM_RB_BLK_NR * 2 / 3,
.post_wm.low = RT_VMM_RB_BLK_NR / 3,
.post_wm.high = RT_VMM_RB_BLK_NR * 2 / 3,
}
},
{
.req =
{
.name = RT_NULL,
}
},
};
#endif /* RT_USING_VBUS */
bsp/lpc43xx/M0/applications/vbus_hw.h 0 → 100644
浏览文件 @ 4a9c3fae
/*
* VMM Bus
*
* COPYRIGHT (C) 2015, Shanghai Real-Thread Technology Co., Ltd
*
* This file is part of RT-Thread (http://www.rt-thread.org)
*
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2015-01-07 Grissiom init commit
*/
#include <rtthread.h>
#include <board.h>
rt_inline void rt_vbus_tick(unsigned int target_cpu, unsigned int irqnr)
{
__SEV();
}
/* Read memory barrier. */
rt_inline void rt_vbus_smp_rmb(void)
{
__DMB();
}
/* Write memory barrier. */
rt_inline void rt_vbus_smp_wmb(void)
{
__DSB();
}
/* General memory barrier. */
rt_inline void rt_vbus_smp_mb(void)
{
__DSB();
}
bsp/lpc43xx/M0/rtconfig.h
浏览文件 @ 4a9c3fae
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
#define RT_DEBUG #define RT_DEBUG
// <bool name="RT_DEBUG_INIT" description="debug init enable" default=0 /> // <bool name="RT_DEBUG_INIT" description="debug init enable" default=0 />
#define RT_DEBUG_INIT 0 #define RT_DEBUG_INIT 0
//#define RT_DEBUG_SCHEDULER 1
// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" /> // <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
// #define RT_THREAD_DEBUG // #define RT_THREAD_DEBUG
// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" /> // <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
...@@ -33,7 +34,7 @@ ...@@ -33,7 +34,7 @@
// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" /> // <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
#define RT_USING_HOOK #define RT_USING_HOOK
// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" > // <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
#define RT_USING_TIMER_SOFT //#define RT_USING_TIMER_SOFT
// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" /> // <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
#define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_PRIO 4
// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" /> // <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
...@@ -96,6 +97,7 @@ ...@@ -96,6 +97,7 @@
#define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLEBUF_SIZE 128
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" /> // <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
#define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_USING_UART0
// </section> // </section>
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" /> // <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
...@@ -222,7 +224,8 @@ ...@@ -222,7 +224,8 @@
#define RT_LWIP_MSKADDR3 0 #define RT_LWIP_MSKADDR3 0
// </section> // </section>
#define RT_USING_VBUS
#define RT_USING_LOGTRACE
// </RDTConfigurator> // </RDTConfigurator>
......
bsp/lpc43xx/M0/rtconfig.py
浏览文件 @ 4a9c3fae
...@@ -2,15 +2,11 @@ import os ...@@ -2,15 +2,11 @@ import os
# core to be use # core to be use
USE_CORE = 'CORE_M0' USE_CORE = 'CORE_M0'
#USE_CORE = 'CORE_M4'
# toolchains options # toolchains options
ARCH='arm' ARCH='arm'
if USE_CORE == 'CORE_M4': CPU = 'cortex-m0'
CPU = 'cortex-m4'
else:
CPU = 'cortex-m0'
CROSS_TOOL='keil' CROSS_TOOL='keil'
...@@ -35,7 +31,7 @@ if os.getenv('RTT_EXEC_PATH'): ...@@ -35,7 +31,7 @@ if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH') EXEC_PATH = os.getenv('RTT_EXEC_PATH')
# #
BUILD = 'release' BUILD = 'debug'
if PLATFORM == 'gcc': if PLATFORM == 'gcc':
# toolchains # toolchains
...@@ -48,23 +44,24 @@ if PLATFORM == 'gcc': ...@@ -48,23 +44,24 @@ if PLATFORM == 'gcc':
SIZE = PREFIX + 'size' SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump' OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy' OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections' DEVICE = ' -mthumb -mcpu=cortex-m0 -ffunction-sections -fdata-sections -Wall'
if USE_CORE == 'CORE_M4': CFLAGS = DEVICE
DEVICE += ' -mfpu=fpv4-sp-d16 -mfloat-abi=softfp'
CFLAGS = DEVICE
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc43xx.map,-cref,-u,Reset_Handler -T rtthread-lpc43xx_spifi.ld' LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc43xx.map,-cref,-u,Reset_Handler -T rtthread-lpc43xx.ld'
CPATH = '' CPATH = ''
LPATH = '' LPATH = ''
CFLAGS += ' -gdwarf-2'
AFLAGS += ' -gdwarf-2'
if BUILD == 'debug': if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2' CFLAGS += ' -O0'
AFLAGS += ' -gdwarf-2'
else: else:
CFLAGS += ' -O2' CFLAGS += ' -O2'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\
SIZE + ' $TARGET \n' +\
'../bin2C.py rtthread.bin ../M4/applications/M0_CODE.h'
elif PLATFORM == 'armcc': elif PLATFORM == 'armcc':
# toolchains # toolchains
......
bsp/lpc43xx/M0/rtthread-lpc43xx.ld 0 → 100644
浏览文件 @ 4a9c3fae
/*
* linker script for LPC43xx SPIFI (4Mb NorFlash, 32kB SRAM ) with GNU ld
* yiyue.fang 2012-04-14
*/
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
CODE (rx) : ORIGIN = 0x1B000000, LENGTH = 0x00080000
DATA (rw) : ORIGIN = 0x10080000, LENGTH = 0x00008000
AHBRAM (rw) : ORIGIN = 0x20000000, LENGTH = 0x00010000
}
ENTRY(Reset_Handler)
_system_stack_size = 0x200;
SECTIONS
{
.text :
{
. = ALIGN(4);
KEEP(*(.interrupt_vector)) /* Startup code */
. = ALIGN(4);
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
. = ALIGN(4);
_etext = .;
} > CODE = 0
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > CODE
__exidx_end = .;
/* .data section which is used for initialized data */
.data : AT (_sidata)
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >DATA
.stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
_estack = .;
} >DATA
__bss_start = .;
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
*(.bss.init)
} > DATA
__bss_end = .;
.vbus_ring (NOLOAD) :
{
*(vbus_ring)
} > AHBRAM
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}
bsp/lpc43xx/M0/rtthread_lpc43xx.sct 0 → 100644
浏览文件 @ 4a9c3fae
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM2 0x1B000000 0x00080000 { ; load region size_region
ER_IROM2 0x1B000000 0x00080000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM2 0x10080000 0x00008000 { ; RW data
.ANY (+RW +ZI)
}
RW_AHBRAM 0x20000000 0x00010000 { ; RW data
* (vbus_ring)
}
}
bsp/lpc43xx/M0/template.uvproj
浏览文件 @ 4a9c3fae
...@@ -12,13 +12,13 @@ ...@@ -12,13 +12,13 @@
<ToolsetName>ARM-ADS</ToolsetName> <ToolsetName>ARM-ADS</ToolsetName>
<TargetOption> <TargetOption>
<TargetCommonOption> <TargetCommonOption>
<Device>LPC4357</Device> <Device>LPC4357 CM0</Device>
<Vendor>NXP (founded by Philips)</Vendor> <Vendor>NXP</Vendor>
<Cpu>IRAM(0x10000000-0x10007FFF) IRAM2(0x20000000-0x2000FFFF) IROM(0x1A000000-0x1A07FFFF) IROM2(0x1B000000-0x1B07FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2</Cpu> <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0")</Cpu>
<FlashUtilSpec></FlashUtilSpec> <FlashUtilSpec></FlashUtilSpec>
<StartupFile>"STARTUP\NXP\LPC43xx\startup_LPC43xx.s" ("NXP LPC43xx Startup Code")</StartupFile> <StartupFile>"STARTUP\NXP\LPC43xx\startup_LPC43xx_M0.s" ("NXP LPC43xx CM0 Startup Code")</StartupFile>
<FlashDriverDll>UL2CM3(-O975 -S0 -C0 -FO7 -FD10000000 -FC800 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000)</FlashDriverDll> <FlashDriverDll>UL2CM3(-O910 -S8 -C1 -FO7 -FD10000000 -FC800 -FN0)</FlashDriverDll>
<DeviceId>6414</DeviceId> <DeviceId>6917</DeviceId>
<RegisterFile>LPC43xx.H</RegisterFile> <RegisterFile>LPC43xx.H</RegisterFile>
<MemoryEnv></MemoryEnv> <MemoryEnv></MemoryEnv>
<Cmp></Cmp> <Cmp></Cmp>
...@@ -26,10 +26,11 @@ ...@@ -26,10 +26,11 @@
<Linker></Linker> <Linker></Linker>
<OHString></OHString> <OHString></OHString>
<InfinionOptionDll></InfinionOptionDll> <InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc> <SLE66CMisc>-DCORE_M0</SLE66CMisc>
<SLE66AMisc></SLE66AMisc> <SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc> <SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>SFD\NXP\LPC43xx\LPC43xx.SFR</SFDFile> <SFDFile>SFD\NXP\LPC43xx\LPC43xx.SFR</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv> <UseEnv>0</UseEnv>
<BinPath></BinPath> <BinPath></BinPath>
<IncludePath></IncludePath> <IncludePath></IncludePath>
...@@ -73,10 +74,10 @@ ...@@ -73,10 +74,10 @@
<UserProg2Dos16Mode>0</UserProg2Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</BeforeMake> </BeforeMake>
<AfterMake> <AfterMake>
<RunUserProg1>0</RunUserProg1> <RunUserProg1>1</RunUserProg1>
<RunUserProg2>0</RunUserProg2> <RunUserProg2>1</RunUserProg2>
<UserProg1Name></UserProg1Name> <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
<UserProg2Name></UserProg2Name> <UserProg2Name>C:\Python27\python.exe ..\bin2C.py rtthread.bin ..\M4\applications\M0_CODE.h</UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode> <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode> <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</AfterMake> </AfterMake>
...@@ -208,10 +209,10 @@ ...@@ -208,10 +209,10 @@
<hadIRAM>1</hadIRAM> <hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM> <hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam> <uocXRam>0</uocXRam>
<RvdsVP>1</RvdsVP> <RvdsVP>2</RvdsVP>
<hadIRAM2>1</hadIRAM2> <hadIRAM2>1</hadIRAM2>
<hadIROM2>1</hadIROM2> <hadIROM2>1</hadIROM2>
<StupSel>1</StupSel> <StupSel>16</StupSel>
<useUlib>1</useUlib> <useUlib>1</useUlib>
<EndSel>0</EndSel> <EndSel>0</EndSel>
<uLtcg>0</uLtcg> <uLtcg>0</uLtcg>
...@@ -224,11 +225,11 @@ ...@@ -224,11 +225,11 @@
<NoZi3>0</NoZi3> <NoZi3>0</NoZi3>
<NoZi4>0</NoZi4> <NoZi4>0</NoZi4>
<NoZi5>0</NoZi5> <NoZi5>0</NoZi5>
<Ro1Chk>1</Ro1Chk> <Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk> <Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk> <Ro3Chk>0</Ro3Chk>
<Ir1Chk>0</Ir1Chk> <Ir1Chk>0</Ir1Chk>
<Ir2Chk>0</Ir2Chk> <Ir2Chk>1</Ir2Chk>
<Ra1Chk>0</Ra1Chk> <Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk> <Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk> <Ra3Chk>0</Ra3Chk>
...@@ -338,7 +339,7 @@ ...@@ -338,7 +339,7 @@
<Optim>1</Optim> <Optim>1</Optim>
<oTime>0</oTime> <oTime>0</oTime>
<SplitLS>0</SplitLS> <SplitLS>0</SplitLS>
<OneElfS>0</OneElfS> <OneElfS>1</OneElfS>
<Strict>0</Strict> <Strict>0</Strict>
<EnumInt>0</EnumInt> <EnumInt>0</EnumInt>
<PlainCh>0</PlainCh> <PlainCh>0</PlainCh>
...@@ -371,7 +372,7 @@ ...@@ -371,7 +372,7 @@
</VariousControls> </VariousControls>
</Aads> </Aads>
<LDads> <LDads>
<umfTarg>1</umfTarg> <umfTarg>0</umfTarg>
<Ropi>0</Ropi> <Ropi>0</Ropi>
<Rwpi>0</Rwpi> <Rwpi>0</Rwpi>
<noStLib>0</noStLib> <noStLib>0</noStLib>
...@@ -379,390 +380,8 @@ ...@@ -379,390 +380,8 @@
<useFile>0</useFile> <useFile>0</useFile>
<TextAddressRange>0x14000000</TextAddressRange> <TextAddressRange>0x14000000</TextAddressRange>
<DataAddressRange>0x10000000</DataAddressRange> <DataAddressRange>0x10000000</DataAddressRange>
<ScatterFile></ScatterFile> <pXoBase></pXoBase>
<IncludeLibs></IncludeLibs> <ScatterFile>.\rtthread_lpc43xx.sct</ScatterFile>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
</Target>
<Target>
<TargetName>LPC43xx RAM</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<TargetCommonOption>
<Device>LPC4357</Device>
<Vendor>NXP (founded by Philips)</Vendor>
<Cpu>IRAM(0x10000000-0x10007FFF) IRAM2(0x20000000-0x2000FFFF) IROM(0x1A000000-0x1A07FFFF) IROM2(0x1B000000-0x1B07FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile>"STARTUP\NXP\LPC43xx\startup_LPC43xx.s" ("NXP LPC43xx Startup Code")</StartupFile>
<FlashDriverDll>UL2CM3(-O975 -S0 -C0 -FO7 -FD10000000 -FC800 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000)</FlashDriverDll>
<DeviceId>6414</DeviceId>
<RegisterFile>LPC43xx.H</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>SFD\NXP\LPC43xx\LPC43xx.SFR</SFDFile>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath>NXP\LPC43xx\</RegisterFilePath>
<DBRegisterFilePath>NXP\LPC43xx\</DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\build\</OutputDirectory>
<OutputName>rtthread_lpc43xx</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\build\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments>-MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments>-MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
<Simulator>
<UseSimulator>0</UseSimulator>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>1</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
</Simulator>
<Target>
<UseTarget>1</UseTarget>
<LoadApplicationAtStartup>0</LoadApplicationAtStartup>
<RunToMain>0</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>0</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<RestoreTracepoints>0</RestoreTracepoints>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>1</TargetSelection>
<SimDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
</SimDlls>
<TargetDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile>.\Dbg_RAM.ini</InitializationFile>
<Driver>BIN\UL2CM3.DLL</Driver>
</TargetDlls>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>1</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>1</RvdsVP>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>1</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>0</Im1Chk>
<Im2Chk>1</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x10000000</StartAddress>
<Size>0x8000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x1a000000</StartAddress>
<Size>0x80000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x1a000000</StartAddress>
<Size>0x80000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x1b000000</StartAddress>
<Size>0x80000</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x10000000</StartAddress>
<Size>0x8000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x10000</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>0</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<VariousControls>
<MiscControls></MiscControls>
<Define>NO_CRP</Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x10000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs> <IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath> <IncludeLibsPath></IncludeLibsPath>
<Misc></Misc> <Misc></Misc>
...@@ -773,5 +392,4 @@ ...@@ -773,5 +392,4 @@
</TargetOption> </TargetOption>
</Target> </Target>
</Targets> </Targets>
</Project> </Project>
bsp/lpc43xx/M0/vbus_local_conf.h 0 → 100644
浏览文件 @ 4a9c3fae
#ifndef __VBUS_LOCAL_CONF_H__
#define __VBUS_LOCAL_CONF_H__
#define RT_VBUS_USING_FLOW_CONTROL
#define RT_VBUS_USING_TESTS
#endif /* end of include guard: __VBUS_LOCAL_CONF_H__ */
bsp/lpc43xx/M4/SConscript
浏览文件 @ 4a9c3fae
...@@ -2,12 +2,16 @@ from building import * ...@@ -2,12 +2,16 @@ from building import *
cwd = GetCurrentDir() cwd = GetCurrentDir()
objs = [] objs = []
list = os.listdir(os.path.join(cwd, '..'))
for d in list: for d in os.listdir(os.path.join(cwd, '..')):
if (d != 'M4' and d != 'M0'): if d not in ('M0', 'M4'):
path = os.path.join(cwd, '..', d) path = os.path.join('..', d, 'SConscript')
if os.path.isfile(os.path.join(path, 'SConscript')): if os.path.isfile(os.path.join(cwd, path)):
objs = objs + SConscript(os.path.join(path, 'SConscript')) objs = objs + SConscript(os.path.join(cwd, path))
for d in os.listdir(cwd):
p = os.path.join(d, 'SConscript');
if os.path.isfile(os.path.join(cwd, p)):
objs = objs + SConscript(p)
Return('objs') Return('objs')
bsp/lpc43xx/M4/SConstruct
浏览文件 @ 4a9c3fae
...@@ -5,12 +5,12 @@ import rtconfig ...@@ -5,12 +5,12 @@ import rtconfig
if os.getenv('RTT_ROOT'): if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT') RTT_ROOT = os.getenv('RTT_ROOT')
else: else:
RTT_ROOT = os.path.join(Dir('#').get_abspath(), '..', '..', 'rt-thread') RTT_ROOT = os.path.join(Dir('#').get_abspath(), '..', '..', '..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import * from building import *
TARGET = 'rtthread-lpc40xx.' + rtconfig.TARGET_EXT TARGET = 'build/rtthread_lpc43xx.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'], env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
...@@ -25,5 +25,30 @@ Export('rtconfig') ...@@ -25,5 +25,30 @@ Export('rtconfig')
# prepare building environment # prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
if rtconfig.CROSS_TOOL == 'gcc':
print 'build M0 code first'
if sys.platform.startswith('linux'):
import glob
ocwd = os.getcwdu()
os.chdir('../M0')
res = os.system('scons')
if res:
print 'build M0 exit with code %d\n' % res
sys.exit(res)
os.chdir(ocwd)
res = os.system('cd ../Libraries/; find -name \*.o -exec rm {} \;')
os.chdir(ocwd)
else:
# Assume Windows.
ocwd = os.getcwdu()
os.chdir('..\M0')
os.system('scons.bat')
os.chdir(ocwd)
# Remove the .o for M0 left on the drivers dir.
for i in glob.glob(GetCurrentDir() + '/../drivers/*.o'):
print 'RM %s' % i
os.unlink(i)
# do building # do building
DoBuilding(TARGET, objs) DoBuilding(TARGET, objs)
bsp/lpc43xx/M4/applications/SConscript 0 → 100644
浏览文件 @ 4a9c3fae
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'applications')
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src,
depend = [''], CPPPATH = CPPPATH,
CPPDEFINES = ['BOOT_PROCESSOR'])
Return('group')
bsp/lpc43xx/M4/applications/application.c 0 → 100644
浏览文件 @ 4a9c3fae
/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2014, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2014-07-13 xiaonong port for lpc43xx
*/
#include <rtthread.h>
#include <board.h>
#include <rtdevice.h>
#include "drv_led.h"
#ifdef RT_USING_FINSH
#include <finsh.h>
#include <shell.h>
#endif
#ifdef RT_USING_LOGTRACE
#include <log_trace.h>
#endif
#ifdef RT_USING_VBUS
#include <vbus.h>
#endif
static const unsigned char _M0_CODE[] SECTION("M0_CODE") = {
#include "M0_CODE.h"
};
static void _boot_M0(void)
{
volatile uint32_t u32REG, u32Val;
LPC_CREG->M0APPMEMMAP = (uint32_t)&_M0_CODE[0];
// Release Slave from reset, first read status
u32REG = LPC_RGU->RESET_ACTIVE_STATUS1;
// If the M0 is being held in reset, release it...
// 1 = no reset, 0 = reset
while(!(u32REG & (1u << 24)))
{
u32Val = (~(u32REG) & (~(1 << 24)));
LPC_RGU->RESET_CTRL1 = u32Val;
u32REG = LPC_RGU->RESET_ACTIVE_STATUS1;
}
rt_kprintf("M0 boot to %p\n", &_M0_CODE[0]);
}
/* thread phase init */
void rt_init_thread_entry(void *parameter)
{
/*
*register unsigned int _msp __asm("msp");
*register unsigned int _psp __asm("psp");
*rt_kprintf("msp@ %p, psp@ %p\n", _msp, _psp);
*/
#ifdef RT_USING_LOGTRACE
log_trace_init();
log_trace_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#ifdef RT_USING_FINSH
/* initialize finsh */
finsh_system_init();
finsh_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#ifdef RT_USING_VBUS
rt_vbus_do_init();
#endif
_boot_M0();
}
/*the led thread*/
ALIGN(RT_ALIGN_SIZE)
static rt_uint8_t led_stack[ 512 ];
static struct rt_thread led_thread;
static void led_thread_entry(void *parameter)
{
rt_uint8_t led_value;
rt_device_t led_dev;
rt_device_t vbus_dev;
rt_err_t err;
rt_led_hw_init();
led_dev = rt_device_find("led");
if (led_dev == RT_NULL)
{
rt_kprintf("can not find the led device\n");
return;
}
vbus_dev = rt_device_find("vecho");
if (vbus_dev == RT_NULL)
{
rt_kprintf("can not find the vbus device\n");
return;
}
err = rt_device_open(vbus_dev, RT_DEVICE_OFLAG_RDWR);
if (err != RT_EOK)
{
rt_kprintf("open vbus failed: %d\n", err);
return;
}
led_value = 0;
while (1)
{
int len;
led_dev->write(led_dev, 0, &led_value, sizeof(led_value));
led_value = !led_value;
len = rt_device_write(vbus_dev, 0, &led_value, sizeof(led_value));
if (len <= 0)
{
rt_kprintf("vbus write err: %d, %d\n", len, rt_get_errno());
}
rt_thread_delay(1000);
}
}
int rt_application_init(void)
{
rt_thread_t tid;
rt_err_t result;
tid = rt_thread_create("init",
rt_init_thread_entry, RT_NULL,
2048, 3, 20);
if (tid != RT_NULL)
rt_thread_startup(tid);
/* init led thread */
result = rt_thread_init(&led_thread, "led",
led_thread_entry, RT_NULL,
(rt_uint8_t *)&led_stack[0], sizeof(led_stack),
20, 5);
if (result == RT_EOK)
{
rt_thread_startup(&led_thread);
}
return 0;
}
bsp/lpc43xx/drivers/board.c → bsp/lpc43xx/M4/applications/board.c
浏览文件 @ 4a9c3fae
...@@ -43,20 +43,19 @@ void rt_hw_board_init() ...@@ -43,20 +43,19 @@ void rt_hw_board_init()
{ {
#ifdef CORE_M4 #ifdef CORE_M4
/* NVIC Configuration */ /* NVIC Configuration */
#define NVIC_VTOR_MASK 0x3FFFFF80
#ifdef VECT_TAB_RAM #ifdef VECT_TAB_RAM
/* Set the Vector Table base location at 0x10000000 */ /* Set the Vector Table base location at 0x10000000 */
SCB->VTOR = (0x10000000 & NVIC_VTOR_MASK); SCB->VTOR = 0x10000000;
#else /* VECT_TAB_FLASH */ #else /* VECT_TAB_FLASH */
/* Set the Vector Table base location at 0x00000000 */ /* Set the Vector Table base location at 0x00000000 */
SCB->VTOR = (0x00000000 & NVIC_VTOR_MASK); SCB->VTOR = 0x1A000000;
#endif #endif
#endif #endif
/* update the core clock */ /* update the core clock */
SystemCoreClockUpdate(); SystemCoreClockUpdate();
/* init systick */ /* init systick */
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND - 1); SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
/* set pend exception priority */ /* set pend exception priority */
NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1); NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
......
bsp/lpc43xx/drivers/board.h → bsp/lpc43xx/M4/applications/board.h
浏览文件 @ 4a9c3fae
...@@ -33,7 +33,6 @@ ...@@ -33,7 +33,6 @@
#define LPC_EXT_SDRAM_END 0xA2000000 #define LPC_EXT_SDRAM_END 0xA2000000
// <bool name="RT_USING_UART0" description="Using UART0" default="true" /> // <bool name="RT_USING_UART0" description="Using UART0" default="true" />
#define RT_USING_UART0
// <bool name="RT_USING_UART1" description="Using UART1" default="true" /> // <bool name="RT_USING_UART1" description="Using UART1" default="true" />
//#define RT_USING_UART1 //#define RT_USING_UART1
// <bool name="RT_USING_UART2" description="Using UART2" default="true" /> // <bool name="RT_USING_UART2" description="Using UART2" default="true" />
...@@ -55,6 +54,6 @@ extern int __bss_end; ...@@ -55,6 +54,6 @@ extern int __bss_end;
void rt_hw_board_init(void); void rt_hw_board_init(void);
int rt_hw_board_heap_init(void); int rt_hw_board_heap_init(void);
int rt_vbus_do_init(void);
#endif #endif
bsp/lpc43xx/M4/applications/startup.c 0 → 100644
浏览文件 @ 4a9c3fae
/*
* File : startup.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Bernard first implementation
* 2014-07-13 xiaonong for LPC43xx
*/
#include <rthw.h>
#include <rtthread.h>
#include "board.h"
extern int rt_application_init(void);
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* initialize board */
rt_hw_board_init();
/* show version */
rt_show_version();
#ifdef RT_USING_HEAP
#if LPC_EXT_SDRAM
rt_system_heap_init((void *)LPC_EXT_SDRAM_BEGIN, (void *)LPC_EXT_SDRAM_END);
sram_init();
#else
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
#endif
/* initialize scheduler system */
rt_system_scheduler_init();
/* initialize system timer*/
rt_system_timer_init();
/* initialize application */
rt_application_init();
/* initialize timer thread */
rt_system_timer_thread_init();
/* initialize idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
}
int main(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* startup RT-Thread RTOS */
rtthread_startup();
return 0;
}
bsp/lpc43xx/M4/applications/vbus_conf.h 0 → 100644
浏览文件 @ 4a9c3fae
#ifndef __VBUS_CONF_H__
#define __VBUS_CONF_H__
/* Number of blocks in VBus. The total size of VBus is
* RT_VMM_RB_BLK_NR * 64byte * 2. */
#define RT_VMM_RB_BLK_NR 20
/* We don't use the IRQ number to trigger IRQ in this BSP. */
#define RT_VBUS_GUEST_VIRQ 0
#define RT_VBUS_HOST_VIRQ 0
#endif /* end of include guard: __VBUS_CONF_H__ */
bsp/lpc43xx/M4/applications/vbus_drv.c 0 → 100644
浏览文件 @ 4a9c3fae
/*
* VMM Bus Driver
*
* COPYRIGHT (C) 2015, Shanghai Real-Thread Technology Co., Ltd
* http://www.rt-thread.com
*
* This file is part of RT-Thread (http://www.rt-thread.org)
*
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2015-01-07 Grissiom add comment
*/
#include <rtthread.h>
#ifdef RT_USING_VBUS
#include <rtdevice.h>
#include <vbus.h>
#include <board.h>
struct rt_vbus_ring rt_vbus_rings[2] SECTION("vbus_ring");
int rt_vbus_do_init(void)
{
return rt_vbus_init(&rt_vbus_rings[0], &rt_vbus_rings[1]);
}
INIT_COMPONENT_EXPORT(rt_vbus_do_init);
int rt_vbus_hw_init(void)
{
NVIC_ClearPendingIRQ(M0CORE_IRQn);
NVIC_EnableIRQ(M0CORE_IRQn);
return 0;
}
void M0CORE_IRQHandler(void)
{
LPC_CREG->M0TXEVENT = 0;
rt_vbus_isr(M0CORE_IRQn, RT_NULL);
}
int rt_vbus_hw_eoi(int irqnr, void *param)
{
/* Nothing to do here as we cleared the interrupt in IRQHandler. */
return 0;
}
struct rt_vbus_dev rt_vbus_chn_devx[] = {
{
.req =
{
.prio = 30,
.name = "vecho",
.is_server = 1,
.recv_wm.low = RT_VMM_RB_BLK_NR / 3,
.recv_wm.high = RT_VMM_RB_BLK_NR * 2 / 3,
.post_wm.low = RT_VMM_RB_BLK_NR / 3,
.post_wm.high = RT_VMM_RB_BLK_NR * 2 / 3,
}
},
{
.req =
{
.name = RT_NULL,
}
},
};
#endif /* RT_USING_VBUS */
bsp/lpc43xx/M4/applications/vbus_hw.h 0 → 100644
浏览文件 @ 4a9c3fae
/*
* VMM Bus
*
* COPYRIGHT (C) 2015, Shanghai Real-Thread Technology Co., Ltd
*
* This file is part of RT-Thread (http://www.rt-thread.org)
*
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2015-01-07 Grissiom init commit
*/
#include <rtthread.h>
#include <board.h>
rt_inline void rt_vbus_tick(unsigned int target_cpu, unsigned int irqnr)
{
__SEV();
}
/* Read memory barrier. */
rt_inline void rt_vbus_smp_rmb(void)
{
__DMB();
}
/* Write memory barrier. */
rt_inline void rt_vbus_smp_wmb(void)
{
__DSB();
}
/* General memory barrier. */
rt_inline void rt_vbus_smp_mb(void)
{
__DSB();
}
bsp/lpc43xx/M4/rtconfig.h
浏览文件 @ 4a9c3fae
...@@ -95,7 +95,8 @@ ...@@ -95,7 +95,8 @@
// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" /> // <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
#define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLEBUF_SIZE 128
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" /> // <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
#define RT_CONSOLE_DEVICE_NAME "uart0" #define RT_CONSOLE_DEVICE_NAME "uart3"
#define RT_USING_UART3
// </section> // </section>
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" /> // <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
...@@ -222,7 +223,8 @@ ...@@ -222,7 +223,8 @@
#define RT_LWIP_MSKADDR3 0 #define RT_LWIP_MSKADDR3 0
// </section> // </section>
#define RT_USING_VBUS
#define RT_USING_LOGTRACE
// </RDTConfigurator> // </RDTConfigurator>
......
bsp/lpc43xx/M4/rtconfig.py
浏览文件 @ 4a9c3fae
...@@ -35,7 +35,7 @@ if os.getenv('RTT_EXEC_PATH'): ...@@ -35,7 +35,7 @@ if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH') EXEC_PATH = os.getenv('RTT_EXEC_PATH')
# #
BUILD = 'release' BUILD = 'debug'
if PLATFORM == 'gcc': if PLATFORM == 'gcc':
# toolchains # toolchains
...@@ -44,23 +44,24 @@ if PLATFORM == 'gcc': ...@@ -44,23 +44,24 @@ if PLATFORM == 'gcc':
AS = PREFIX + 'gcc' AS = PREFIX + 'gcc'
AR = PREFIX + 'ar' AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc' LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf' TARGET_EXT = 'axf'
SIZE = PREFIX + 'size' SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump' OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy' OBJCPY = PREFIX + 'objcopy'
DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections' DEVICE = ' -mcpu=' + CPU + ' -mthumb -ffunction-sections -fdata-sections -Wall'
if USE_CORE == 'CORE_M4': if USE_CORE == 'CORE_M4':
DEVICE += ' -mfpu=fpv4-sp-d16 -mfloat-abi=softfp' DEVICE += ' -mfpu=fpv4-sp-d16 -mfloat-abi=softfp'
CFLAGS = DEVICE CFLAGS = DEVICE
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc43xx.map,-cref,-u,Reset_Handler -T rtthread-lpc43xx_spifi.ld' LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc43xx.map,-cref,-u,Reset_Handler -T rtthread-lpc43xx.ld'
CPATH = '' CPATH = ''
LPATH = '' LPATH = ''
CFLAGS += ' -gdwarf-2'
AFLAGS += ' -gdwarf-2'
if BUILD == 'debug': if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2' CFLAGS += ' -O0'
AFLAGS += ' -gdwarf-2'
else: else:
CFLAGS += ' -O2' CFLAGS += ' -O2'
......
bsp/lpc43xx/M4/rtthread-lpc43xx.ld 0 → 100644
浏览文件 @ 4a9c3fae
/*
* linker script for LPC43xx SPIFI (4Mb NorFlash, 32kB SRAM ) with GNU ld
* yiyue.fang 2012-04-14
*/
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
CODE (rx) : ORIGIN = 0x1A000000, LENGTH = 0x00080000
M0CODE (rx) : ORIGIN = 0x1B000000, LENGTH = 0x00080000
DATA (rw) : ORIGIN = 0x10000000, LENGTH = 0x00008000
AHBRAM (rw) : ORIGIN = 0x20000000, LENGTH = 0x00010000
}
ENTRY(Reset_Handler)
_system_stack_size = 0x200;
SECTIONS
{
.text :
{
. = ALIGN(4);
KEEP(*(.interrupt_vector)) /* Startup code */
. = ALIGN(4);
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
. = ALIGN(4);
_etext = .;
} > CODE = 0
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > CODE
__exidx_end = .;
/* .data section which is used for initialized data */
.data : AT (_sidata)
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >DATA
. = _edata ;
.stack :
{
. = . + _system_stack_size;
. = ALIGN(4);
_estack = .;
} >DATA
__bss_start = .;
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
*(.bss.init)
} > DATA
__bss_end = .;
.vbus_ring (NOLOAD) :
{
*(vbus_ring)
} > AHBRAM
.text.M0CODE :
{
*(M0_CODE)
} > M0CODE = 0
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}
bsp/lpc43xx/M4/rtthread_lpc43xx.sct 0 → 100644
浏览文件 @ 4a9c3fae
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x1A000000 0x00080000 { ; load region size_region
ER_IROM1 0x1A000000 0x00080000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x10000000 0x00008000 { ; RW data
.ANY (+RW +ZI)
}
RW_AHBRAM 0x20000000 0x00010000 { ; RW data
* (vbus_ring)
}
}
LR_IROM2 0x1B000000 0x00080000 {
ER_IROM2 0x1B000000 0x00080000 { ; load address = execution address
* (M0_CODE)
}
}
bsp/lpc43xx/M4/template.uvproj
浏览文件 @ 4a9c3fae
...@@ -211,7 +211,7 @@ ...@@ -211,7 +211,7 @@
<RvdsVP>2</RvdsVP> <RvdsVP>2</RvdsVP>
<hadIRAM2>1</hadIRAM2> <hadIRAM2>1</hadIRAM2>
<hadIROM2>1</hadIROM2> <hadIROM2>1</hadIROM2>
<StupSel>1</StupSel> <StupSel>8</StupSel>
<useUlib>1</useUlib> <useUlib>1</useUlib>
<EndSel>0</EndSel> <EndSel>0</EndSel>
<uLtcg>0</uLtcg> <uLtcg>0</uLtcg>
...@@ -224,10 +224,10 @@ ...@@ -224,10 +224,10 @@
<NoZi3>0</NoZi3> <NoZi3>0</NoZi3>
<NoZi4>0</NoZi4> <NoZi4>0</NoZi4>
<NoZi5>0</NoZi5> <NoZi5>0</NoZi5>
<Ro1Chk>1</Ro1Chk> <Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk> <Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk> <Ro3Chk>0</Ro3Chk>
<Ir1Chk>0</Ir1Chk> <Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk> <Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk> <Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk> <Ra2Chk>0</Ra2Chk>
...@@ -338,7 +338,7 @@ ...@@ -338,7 +338,7 @@
<Optim>1</Optim> <Optim>1</Optim>
<oTime>0</oTime> <oTime>0</oTime>
<SplitLS>0</SplitLS> <SplitLS>0</SplitLS>
<OneElfS>0</OneElfS> <OneElfS>1</OneElfS>
<Strict>0</Strict> <Strict>0</Strict>
<EnumInt>0</EnumInt> <EnumInt>0</EnumInt>
<PlainCh>0</PlainCh> <PlainCh>0</PlainCh>
...@@ -371,7 +371,7 @@ ...@@ -371,7 +371,7 @@
</VariousControls> </VariousControls>
</Aads> </Aads>
<LDads> <LDads>
<umfTarg>1</umfTarg> <umfTarg>0</umfTarg>
<Ropi>0</Ropi> <Ropi>0</Ropi>
<Rwpi>0</Rwpi> <Rwpi>0</Rwpi>
<noStLib>0</noStLib> <noStLib>0</noStLib>
...@@ -379,390 +379,8 @@ ...@@ -379,390 +379,8 @@
<useFile>0</useFile> <useFile>0</useFile>
<TextAddressRange>0x14000000</TextAddressRange> <TextAddressRange>0x14000000</TextAddressRange>
<DataAddressRange>0x10000000</DataAddressRange> <DataAddressRange>0x10000000</DataAddressRange>
<ScatterFile></ScatterFile> <pXoBase></pXoBase>
<IncludeLibs></IncludeLibs> <ScatterFile>.\rtthread_lpc43xx.sct</ScatterFile>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
</Target>
<Target>
<TargetName>LPC43xx RAM</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<TargetCommonOption>
<Device>LPC4357</Device>
<Vendor>NXP (founded by Philips)</Vendor>
<Cpu>IRAM(0x10000000-0x10007FFF) IRAM2(0x20000000-0x2000FFFF) IROM(0x1A000000-0x1A07FFFF) IROM2(0x1B000000-0x1B07FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile>"STARTUP\NXP\LPC43xx\startup_LPC43xx.s" ("NXP LPC43xx Startup Code")</StartupFile>
<FlashDriverDll>UL2CM3(-O975 -S0 -C0 -FO7 -FD10000000 -FC800 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000)</FlashDriverDll>
<DeviceId>6414</DeviceId>
<RegisterFile>LPC43xx.H</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>SFD\NXP\LPC43xx\LPC43xx.SFR</SFDFile>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath>NXP\LPC43xx\</RegisterFilePath>
<DBRegisterFilePath>NXP\LPC43xx\</DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\build\</OutputDirectory>
<OutputName>rtthread_lpc43xx</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\build\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments>-MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments>-MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
<Simulator>
<UseSimulator>0</UseSimulator>
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
<RunToMain>1</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
<RestoreFunctions>1</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
</Simulator>
<Target>
<UseTarget>1</UseTarget>
<LoadApplicationAtStartup>0</LoadApplicationAtStartup>
<RunToMain>0</RunToMain>
<RestoreBreakpoints>1</RestoreBreakpoints>
<RestoreWatchpoints>1</RestoreWatchpoints>
<RestoreMemoryDisplay>0</RestoreMemoryDisplay>
<RestoreFunctions>0</RestoreFunctions>
<RestoreToolbox>1</RestoreToolbox>
<RestoreTracepoints>0</RestoreTracepoints>
</Target>
<RunDebugAfterBuild>0</RunDebugAfterBuild>
<TargetSelection>1</TargetSelection>
<SimDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile></InitializationFile>
</SimDlls>
<TargetDlls>
<CpuDll></CpuDll>
<CpuDllArguments></CpuDllArguments>
<PeripheralDll></PeripheralDll>
<PeripheralDllArguments></PeripheralDllArguments>
<InitializationFile>.\Dbg_RAM.ini</InitializationFile>
<Driver>BIN\UL2CM3.DLL</Driver>
</TargetDlls>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>1</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4096</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<hadIRAM2>1</hadIRAM2>
<hadIROM2>1</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>0</Im1Chk>
<Im2Chk>1</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x10000000</StartAddress>
<Size>0x8000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x1a000000</StartAddress>
<Size>0x80000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x1a000000</StartAddress>
<Size>0x80000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x1b000000</StartAddress>
<Size>0x80000</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x10000000</StartAddress>
<Size>0x8000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x10000</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>0</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>0</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<VariousControls>
<MiscControls></MiscControls>
<Define>NO_CRP</Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x10000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs> <IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath> <IncludeLibsPath></IncludeLibsPath>
<Misc></Misc> <Misc></Misc>
...@@ -773,5 +391,4 @@ ...@@ -773,5 +391,4 @@
</TargetOption> </TargetOption>
</Target> </Target>
</Targets> </Targets>
</Project> </Project>
bsp/lpc43xx/M4/vbus_local_conf.h 0 → 100644
浏览文件 @ 4a9c3fae
#ifndef __VBUS_LOCAL_CONF_H__
#define __VBUS_LOCAL_CONF_H__
#define RT_VBUS_USING_FLOW_CONTROL
#define RT_VBUS_USING_TESTS
#endif /* end of include guard: __VBUS_LOCAL_CONF_H__ */
bsp/lpc43xx/bin2C.py 0 → 100644
浏览文件 @ 4a9c3fae
#!/bin/env python
import sys
fi = open(sys.argv[1], 'rb')
fo = open(sys.argv[2], 'wb')
idx = 0
for i in fi.read():
idx += 1
fo.write('0x%02x, ' % ord(i))
if idx % 16 == 0:
fo.write('\n')
fo.write('\n')
bsp/lpc43xx/drivers/drv_uart.c
浏览文件 @ 4a9c3fae
...@@ -26,19 +26,7 @@ struct lpc_uart ...@@ -26,19 +26,7 @@ struct lpc_uart
static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_configure *cfg) static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{ {
// struct lpc_uart *uart;
RT_ASSERT(serial != RT_NULL); RT_ASSERT(serial != RT_NULL);
// uart = (struct lpc_uart *)serial->parent.user_data;
// Initialize FIFO for UART0 peripheral
// UART_FIFOConfig(uart->USART, &UARTFIFOConfigStruct);
// UART_TxCmd(uart->USART, ENABLE);
return RT_EOK; return RT_EOK;
} }
...@@ -95,60 +83,62 @@ static const struct rt_uart_ops lpc_uart_ops = ...@@ -95,60 +83,62 @@ static const struct rt_uart_ops lpc_uart_ops =
lpc_getc, lpc_getc,
}; };
#if defined(RT_USING_UART0) static void _do_uart_isr(struct rt_serial_device *sdev)
/* UART0 device driver structure */
struct lpc_uart uart0 =
{
LPC_USART0,
USART0_IRQn,
};
struct rt_serial_device serial0;
void UART0_IRQHandler(void)
{ {
struct lpc_uart *uart; struct lpc_uart *uart;
volatile uint32_t intsrc, temp; uint32_t intsrc;
uart = &uart0; uart = sdev->parent.user_data;
/* enter interrupt */
rt_interrupt_enter();
/* Determine the interrupt source */ /* Determine the interrupt source */
intsrc = uart->USART->IIR & UART_IIR_INTID_MASK; intsrc = uart->USART->IIR & UART_IIR_INTID_MASK;
switch (intsrc) switch (intsrc)
{ {
case UART_IIR_INTID_RLS:
case UART_IIR_INTID_RLS: /* Receive Line Status interrupt*/ /* Receive Line Status interrupt */
/* read the line status */ /* read the line status */
intsrc = uart->USART->LSR; intsrc = uart->USART->LSR;
/* Receive an error data */ /* Receive an error data */
if (intsrc & UART_LSR_PE) if (intsrc & UART_LSR_PE)
{ {
temp = LPC_USART0->RBR; uart->USART->RBR;
} }
break; break;
case UART_IIR_INTID_RDA:
case UART_IIR_INTID_RDA: /* Receive data */ /* Receive data */
case UART_IIR_INTID_CTI: /* Receive data timeout */ case UART_IIR_INTID_CTI:
/* Receive data timeout */
/* read the data to buffer */ /* read the data to buffer */
while (uart->USART->LSR & UART_LSR_RDR) while (uart->USART->LSR & UART_LSR_RDR)
{ {
rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND); rt_hw_serial_isr(sdev, RT_SERIAL_EVENT_RX_IND);
} }
break; break;
default: default:
break; break;
} }
}
/* leave interrupt */ #if defined(RT_USING_UART0)
/* UART0 device driver structure */
struct lpc_uart uart0 =
{
LPC_USART0,
USART0_IRQn,
};
struct rt_serial_device serial0;
void UART0_IRQHandler(void)
{
rt_interrupt_enter();
_do_uart_isr(&serial0);
rt_interrupt_leave(); rt_interrupt_leave();
} }
#endif #endif
#if defined(RT_USING_UART2) #if defined(RT_USING_UART2)
/* UART2 device driver structure */
struct lpc_uart uart2 = struct lpc_uart uart2 =
{ {
LPC_USART2, LPC_USART2,
...@@ -158,47 +148,28 @@ struct rt_serial_device serial2; ...@@ -158,47 +148,28 @@ struct rt_serial_device serial2;
void UART2_IRQHandler(void) void UART2_IRQHandler(void)
{ {
struct lpc_uart *uart;
uint32_t intsrc, temp;
uart = &uart2;
/* enter interrupt */
rt_interrupt_enter(); rt_interrupt_enter();
_do_uart_isr(&serial2);
rt_interrupt_leave();
}
#endif
/* Determine the interrupt source */ #if defined(RT_USING_UART3)
intsrc = uart->USART->IIR & UART_IIR_INTID_MASK; struct lpc_uart uart3 =
{
switch (intsrc) LPC_USART3,
{ USART3_IRQn,
};
case UART_IIR_INTID_RLS: /* Receive Line Status interrupt*/ struct rt_serial_device serial3;
/* read the line status */
intsrc = uart->USART->LSR;
/* Receive an error data */
if (intsrc & UART_LSR_PE)
{
temp = LPC_USART0->RBR;
}
break;
case UART_IIR_INTID_RDA: /* Receive data */
case UART_IIR_INTID_CTI: /* Receive data timeout */
/* read the data to buffer */
while (uart->USART->LSR & UART_LSR_RDR)
{
rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
}
break;
default:
break;
}
/* leave interrupt */ void UART3_IRQHandler(void)
{
rt_interrupt_enter();
_do_uart_isr(&serial3);
rt_interrupt_leave(); rt_interrupt_leave();
} }
#endif #endif
void rt_hw_uart_init(void) void rt_hw_uart_init(void)
{ {
struct lpc_uart *uart; struct lpc_uart *uart;
...@@ -212,7 +183,7 @@ void rt_hw_uart_init(void) ...@@ -212,7 +183,7 @@ void rt_hw_uart_init(void)
config.parity = PARITY_NONE; config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1; config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL; config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ; config.bufsz = RT_SERIAL_RB_BUFSZ;
serial0.ops = &lpc_uart_ops; serial0.ops = &lpc_uart_ops;
serial0.config = config; serial0.config = config;
...@@ -221,36 +192,36 @@ void rt_hw_uart_init(void) ...@@ -221,36 +192,36 @@ void rt_hw_uart_init(void)
LPC_CCU1->CLK_M4_GPIO_CFG |= 0x01; LPC_CCU1->CLK_M4_GPIO_CFG |= 0x01;
while (!(LPC_CCU1->CLK_M4_GPIO_STAT & 0x01)); while (!(LPC_CCU1->CLK_M4_GPIO_STAT & 0x01));
/* Enable USART1 peripheral clock */ /* Enable USART0 peripheral clock */
LPC_CCU2->CLK_APB0_USART0_CFG |= 0x01; LPC_CCU2->CLK_APB0_USART0_CFG |= 0x01;
while (!(LPC_CCU2->CLK_APB0_USART0_STAT & 0x01)); while (!(LPC_CCU2->CLK_APB0_USART0_STAT & 0x01));
/* Enable USART1 register interface clock */ /* Enable USART0 register interface clock */
LPC_CCU1->CLK_M4_USART0_CFG |= 0x01; LPC_CCU1->CLK_M4_USART0_CFG |= 0x01;
while (!(LPC_CCU1->CLK_M4_USART0_STAT & 0x01)); while (!(LPC_CCU1->CLK_M4_USART0_STAT & 0x01));
/* Init GPIO pins */ /* Init GPIO pins */
LPC_SCU->SFSP2_0 = (1 << 6) | /* Input buffer enabled */ LPC_SCU->SFSP2_0 = (1 << 6) | /* Input buffer enabled */
(1 << 4) | /* Pull-up disabled */ (1 << 4) | /* Pull-up disabled */
(1 << 0) ; /* Pin P2_0 used as U0_TXD */ (1 << 0) ; /* Pin P2_0 used as U0_TXD */
LPC_SCU->SFSP2_1 = (1 << 6) | /* Input buffer enabled */ LPC_SCU->SFSP2_1 = (1 << 6) | /* Input buffer enabled */
(1 << 4) | /* Pull-up disabled */ (1 << 4) | /* Pull-up disabled */
(1 << 0) ; /* Pin P2_1 used as U0_RXD */ (1 << 0) ; /* Pin P2_1 used as U0_RXD */
/* Init USART0 */ /* Init USART0 */
LPC_USART0->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */ uart->USART->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
LPC_USART0->DLL = 0x06; /* 115200 Baudrate @ 12 MHz IRC */ uart->USART->DLL = 0x06; /* 115200 Baudrate @ 12 MHz IRC */
LPC_USART0->DLM = 0x00; uart->USART->DLM = 0x00;
LPC_USART0->FDR = 0xC1; uart->USART->FDR = 0xC1;
LPC_USART0->LCR = 0x03; /* DLAB = 0 */ uart->USART->LCR = 0x03; /* DLAB = 0 */
/* preemption = 1, sub-priority = 1 */ /* preemption = 1, sub-priority = 1 */
NVIC_SetPriority(uart->USART_IRQn, ((0x01 << 3) | 0x01)); NVIC_SetPriority(uart->USART_IRQn, ((0x01 << 3) | 0x01));
/* Enable Interrupt for UART channel */ /* Enable Interrupt for UART channel */
NVIC_EnableIRQ(uart->USART_IRQn); NVIC_EnableIRQ(uart->USART_IRQn);
/* register UART1 device */ /* register UART0 device */
rt_hw_serial_register(&serial0, "uart0", rt_hw_serial_register(&serial0, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart); uart);
...@@ -263,7 +234,7 @@ void rt_hw_uart_init(void) ...@@ -263,7 +234,7 @@ void rt_hw_uart_init(void)
config.parity = PARITY_NONE; config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1; config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL; config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ; config.bufsz = RT_SERIAL_RB_BUFSZ;
serial2.ops = &lpc_uart_ops; serial2.ops = &lpc_uart_ops;
serial2.config = config; serial2.config = config;
...@@ -272,39 +243,91 @@ void rt_hw_uart_init(void) ...@@ -272,39 +243,91 @@ void rt_hw_uart_init(void)
LPC_CCU1->CLK_M4_GPIO_CFG |= 0x01; LPC_CCU1->CLK_M4_GPIO_CFG |= 0x01;
while (!(LPC_CCU1->CLK_M4_GPIO_STAT & 0x01)); while (!(LPC_CCU1->CLK_M4_GPIO_STAT & 0x01));
/* Enable USART1 peripheral clock */ /* Enable USART2 peripheral clock */
LPC_CCU2->CLK_APB0_USART0_CFG |= 0x01; LPC_CCU2->CLK_APB2_USART2_CFG |= 0x01;
while (!(LPC_CCU2->CLK_APB2_USART2_STAT & 0x01)); while (!(LPC_CCU2->CLK_APB2_USART2_STAT & 0x01));
/* Enable USART2 register interface clock */ /* Enable USART2 register interface clock */
LPC_CCU1->CLK_M4_USART0_CFG |= 0x01; LPC_CCU1->CLK_M4_USART2_CFG |= 0x01;
while (!(LPC_CCU1->CLK_M4_USART2_STAT & 0x01)); while (!(LPC_CCU1->CLK_M4_USART2_STAT & 0x01));
/* Init GPIO pins */ /* Init GPIO pins */
LPC_SCU->SFSP1_15 = (1 << 6) | /* Input buffer enabled */ LPC_SCU->SFSP1_15 = (1 << 6) | /* Input buffer enabled */
(1 << 4) | /* Pull-up disabled */ (1 << 4) | /* Pull-up disabled */
(1 << 0) ; /* Pin P1_15 used as U2_TXD */ (1 << 0) ; /* Pin P1_15 used as U2_TXD */
LPC_SCU->SFSP1_16 = (1 << 6) | /* Input buffer enabled */ LPC_SCU->SFSP1_16 = (1 << 6) | /* Input buffer enabled */
(1 << 4) | /* Pull-up disabled */ (1 << 4) | /* Pull-up disabled */
(1 << 0) ; /* Pin P1_16 used as U2_RXD */ (1 << 0) ; /* Pin P1_16 used as U2_RXD */
/* Init USART2 */ /* Init USART2 */
LPC_USART2->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */ uart->USART->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
LPC_USART2->DLL = 0x06; /* 115200 Baudrate @ 12 MHz IRC */ uart->USART->DLL = 0x06; /* 115200 Baudrate @ 12 MHz IRC */
LPC_USART2->DLM = 0x00; uart->USART->DLM = 0x00;
LPC_USART2->FDR = 0xC1; uart->USART->FDR = 0xC1;
LPC_USART2->LCR = 0x03; /* DLAB = 0 */ uart->USART->LCR = 0x03; /* DLAB = 0 */
/* preemption = 1, sub-priority = 1 */ /* preemption = 1, sub-priority = 1 */
NVIC_SetPriority(uart->USART_IRQn, ((0x01 << 3) | 0x01)); NVIC_SetPriority(uart->USART_IRQn, ((0x01 << 3) | 0x01));
/* Enable Interrupt for UART channel */ /* Enable Interrupt for UART channel */
NVIC_EnableIRQ(uart->USART_IRQn); NVIC_EnableIRQ(uart->USART_IRQn);
/* register UART1 device */ /* register UART2 device */
rt_hw_serial_register(&serial2, "uart2", rt_hw_serial_register(&serial2, "uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart); uart);
#endif #endif
#ifdef RT_USING_UART3
uart = &uart3;
config.baud_rate = BAUD_RATE_115200;
config.bit_order = BIT_ORDER_LSB;
config.data_bits = DATA_BITS_8;
config.parity = PARITY_NONE;
config.stop_bits = STOP_BITS_1;
config.invert = NRZ_NORMAL;
config.bufsz = RT_SERIAL_RB_BUFSZ;
serial3.ops = &lpc_uart_ops;
serial3.config = config;
/* Enable GPIO register interface clock */
LPC_CCU1->CLK_M4_GPIO_CFG |= 0x01;
while (!(LPC_CCU1->CLK_M4_GPIO_STAT & 0x01));
/* Enable USART3 peripheral clock */
LPC_CCU2->CLK_APB2_USART3_CFG |= 0x01;
while (!(LPC_CCU2->CLK_APB2_USART3_STAT & 0x01));
/* Enable USART3 register interface clock */
LPC_CCU1->CLK_M4_USART3_CFG |= 0x01;
while (!(LPC_CCU1->CLK_M4_USART3_STAT & 0x01));
/* Init GPIO pins */
LPC_SCU->SFSP2_3 = (1 << 6) | /* Input buffer enabled */
(1 << 4) | /* Pull-up disabled */
(2 << 0) ; /* Pin P1_15 used as U2_TXD */
LPC_SCU->SFSP2_4 = (1 << 6) | /* Input buffer enabled */
(1 << 4) | /* Pull-up disabled */
(2 << 0) ; /* Pin P1_16 used as U2_RXD */
/* Init USART3 */
uart->USART->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
uart->USART->DLL = 0x06; /* 115200 Baudrate @ 12 MHz IRC */
uart->USART->DLM = 0x00;
uart->USART->FDR = 0xC1;
uart->USART->LCR = 0x03; /* DLAB = 0 */
/* preemption = 1, sub-priority = 1 */
NVIC_SetPriority(uart->USART_IRQn, ((0x01 << 3) | 0x01));
/* Enable Interrupt for UART channel */
NVIC_EnableIRQ(uart->USART_IRQn);
/* register UART2 device */
rt_hw_serial_register(&serial3, "uart3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
#endif
} }
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1. M4 run on flash bank A. M0 run on flash bank B and the binary code of M0 is
embedded into the code of M4.
3. Compile the project in M0/ first and then compile the project in M4/. Then
flash it into the chip with JLink.
bsp/lpc5410x/Libraries/CMSIS/Include/arm_common_tables.h 0 → 100644
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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
*
* $Date: 17. January 2013
* $Revision: V1.4.1
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
extern const q31_t realCoefAQ31[1024];
extern const q31_t realCoefBQ31[1024];
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoefQ31[6144];
extern const q15_t twiddleCoefQ15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
#endif /* ARM_COMMON_TABLES_H */
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# RT-Thread building script for component
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Split('''
startup/sysinit.c
''')
CPPPATH = [cwd + '/../CMSIS/Include']
CPPDEFINES = ['CORE_M4']
# add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
src += ['startup/gcc_startup_lpc5410x.c']
elif rtconfig.CROSS_TOOL == 'keil':
src += ['startup/keil_startup_lpc5410x.s']
group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
Return('group')
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//*****************************************************************************
// crp.c
//
// Source file to create CRP word expected by LPCXpresso IDE linker
//*****************************************************************************
//
// Copyright(C) NXP Semiconductors, 2013
// All rights reserved.
//
// Software that is described herein is for illustrative purposes only
// which provides customers with programming information regarding the
// LPC products. This software is supplied "AS IS" without any warranties of
// any kind, and NXP Semiconductors and its licensor disclaim any and
// all warranties, express or implied, including all implied warranties of
// merchantability, fitness for a particular purpose and non-infringement of
// intellectual property rights. NXP Semiconductors assumes no responsibility
// or liability for the use of the software, conveys no license or rights under any
// patent, copyright, mask work right, or any other intellectual property rights in
// or to any products. NXP Semiconductors reserves the right to make changes
// in the software without notification. NXP Semiconductors also makes no
// representation or warranty that such application will be suitable for the
// specified use without further testing or modification.
//
// Permission to use, copy, modify, and distribute this software and its
// documentation is hereby granted, under NXP Semiconductors' and its
// licensor's relevant copyrights in the software, without fee, provided that it
// is used in conjunction with NXP Semiconductors microcontrollers. This
// copyright, permission, and disclaimer notice must appear in all copies of
// this code.
//*****************************************************************************
#if defined (__CODE_RED)
#include <NXP/crp.h>
// Variable to store CRP value in. Will be placed automatically
// by the linker when "Enable Code Read Protect" selected.
// See crp.h header for more information
__CRP const unsigned int CRP_WORD = CRP_NO_CRP ;
#endif
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//*****************************************************************************
// +--+
// | ++----+
// +-++ |
// | |
// +-+--+ |
// | +--+--+
// +----+ Copyright (c) 2013 Code Red Technologies Ltd.
//
// mtb.c
//
// Optionally defines an array to be used as a buffer for Micro Trace
// Buffer (MTB) instruction trace on Cortex-M0+ parts
//
// Version : 130502
//
// Software License Agreement
//
// The software is owned by Code Red Technologies and/or its suppliers, and is
// protected under applicable copyright laws. All rights are reserved. Any
// use in violation of the foregoing restrictions may subject the user to criminal
// sanctions under applicable laws, as well as to civil liability for the breach
// of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
// CODE RED TECHNOLOGIES LTD.
//
//*****************************************************************************
/*******************************************************************
* Symbols controlling behavior of this code...
*
* __MTB_DISABLE
* If this symbol is defined, then the buffer array for the MTB
* will not be created.
*
* __MTB_BUFFER_SIZE
* Symbol specifying the sizer of the buffer array for the MTB.
* This must be a power of 2 in size, and fit into the available
* RAM. The MTB buffer will also be aligned to its 'size'
* boundary and be placed at the start of a RAM bank (which
* should ensure minimal or zero padding due to alignment).
*
* __MTB_RAM_BANK
* Allows MTB Buffer to be placed into specific RAM bank. When
* this is not defined, the "default" (first if there are
* several) RAM bank is used.
*******************************************************************/
// Ignore with none Code Red tools
#if defined (__CODE_RED)
// Allow MTB to be removed by setting a define (via command line)
#if !defined (__MTB_DISABLE)
// Allow for MTB buffer size being set by define set via command line
// Otherwise provide small default buffer
#if !defined (__MTB_BUFFER_SIZE)
#define __MTB_BUFFER_SIZE 128
#endif
// Check that buffer size requested is >0 bytes in size
#if (__MTB_BUFFER_SIZE > 0)
// Pull in MTB related macros
#include <cr_mtb_buffer.h>
// Check if MYTB buffer is to be placed in specific RAM bank
#if defined(__MTB_RAM_BANK)
// Place MTB buffer into explicit bank of RAM
__CR_MTB_BUFFER_EXT(__MTB_BUFFER_SIZE,__MTB_RAM_BANK);
#else
// Place MTB buffer into 'default' bank of RAM
__CR_MTB_BUFFER(__MTB_BUFFER_SIZE);
#endif // defined(__MTB_RAM_BANK)
#endif // (__MTB_BUFFER_SIZE > 0)
#endif // !defined (__MTB_DISABLE)
#endif // defined (__CODE_RED)
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/*
* @brief Common SystemInit function for LPC54xxx chips
*
* @note
* Copyright(C) NXP Semiconductors, 2014
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/* Clock rate on the CLKIN pin */
const uint32_t ExtClockIn = 0;
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Set up and initialize hardware prior to call to main */
void SystemInit(void)
{
#if defined(__CODE_RED)
extern void(*const g_pfnVectors[]) (void);
SCB->VTOR = (uint32_t) &g_pfnVectors;
#else
//extern void *__Vectors;
//SCB->VTOR = (uint32_t) &isr_vector;
SCB->VTOR = 0x00000000 & 0x3FFFFF80;
#endif
#if defined(CORE_M4)
#if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
fpuInit();
#endif
#endif
#if !defined(__MULTICORE_M0SLAVE) && !defined(__MULTICORE_M4SLAVE)
/* Chip specific SystemInit */
Chip_SystemInit();
#endif
}
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# RT-Thread building script for bridge
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
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dir *.c >C:\Users\Administrator\Desktop\c.txt
\ No newline at end of file
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components/finsh/msh_cmd.c
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components/vbus/SConscript 0 → 100644
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