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体验新版 GitCode,发现更多精彩内容 >>
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2de47972
编写于
12月 10, 2021
作者:
B
Bernard Xiong
提交者:
GitHub
12月 10, 2021
浏览文件
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差异文件
Merge pull request #5354 from Lim-LinYuanbo/master
完善代码,解决部分BUG
上级
1e03864f
6378f95f
变更
16
隐藏空白更改
内联
并排
Showing
16 changed file
with
344 addition
and
88 deletion
+344
-88
bsp/n32g452xx/Libraries/rt_drivers/SConscript
bsp/n32g452xx/Libraries/rt_drivers/SConscript
+4
-3
bsp/n32g452xx/Libraries/rt_drivers/drv_clk.c
bsp/n32g452xx/Libraries/rt_drivers/drv_clk.c
+244
-0
bsp/n32g452xx/Libraries/rt_drivers/drv_clk.h
bsp/n32g452xx/Libraries/rt_drivers/drv_clk.h
+41
-0
bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c
bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c
+0
-1
bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.h
bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.h
+1
-0
bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.c
bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.c
+18
-65
bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.h
bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.h
+1
-1
bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.c
bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.c
+0
-1
bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c
bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c
+0
-1
bsp/n32g452xx/Libraries/rt_drivers/drv_usart.h
bsp/n32g452xx/Libraries/rt_drivers/drv_usart.h
+1
-0
bsp/n32g452xx/n32g452xx-mini-system/.config
bsp/n32g452xx/n32g452xx-mini-system/.config
+5
-3
bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig
bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig
+3
-3
bsp/n32g452xx/n32g452xx-mini-system/board/board.c
bsp/n32g452xx/n32g452xx-mini-system/board/board.c
+11
-0
bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c
bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c
+3
-2
bsp/n32g452xx/n32g452xx-mini-system/rtconfig.h
bsp/n32g452xx/n32g452xx-mini-system/rtconfig.h
+4
-2
bsp/n32g452xx/n32g452xx-mini-system/rtconfig.py
bsp/n32g452xx/n32g452xx-mini-system/rtconfig.py
+8
-6
未找到文件。
bsp/n32g452xx/Libraries/rt_drivers/SConscript
浏览文件 @
2de47972
...
...
@@ -10,14 +10,15 @@ src = Split("""
"""
)
src
+=
[
'drv_common.c'
]
src
+=
[
'drv_clk.c'
]
if
GetDepend
([
'
RT_USING_PIN
'
]):
if
GetDepend
([
'
BSP_USING_GPIO
'
]):
src
+=
[
'drv_gpio.c'
]
if
GetDepend
([
'
RT_USING_WD
T'
]):
if
GetDepend
([
'
BSP_USING_UAR
T'
]):
src
+=
[
'drv_wdt.c'
]
if
GetDepend
([
'
RT_USING_SERIAL
'
]):
if
GetDepend
([
'
BSP_USING_UART
'
]):
src
+=
[
'drv_usart.c'
]
if
GetDepend
([
'BSP_USING_PWM'
]):
...
...
bsp/n32g452xx/Libraries/rt_drivers/drv_clk.c
0 → 100755
浏览文件 @
2de47972
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-20 breo.com first version
*/
#include "drv_clk.h"
#include "board.h"
void
DumpClock
(
const
char
*
msg
)
{
RCC_ClocksType
RCC_ClockFreq
;
rt_kprintf
(
"--------------------------------
\n
"
);
rt_kprintf
(
"%s:
\n
"
,
msg
);
RCC_GetClocksFreqValue
(
&
RCC_ClockFreq
);
rt_kprintf
(
"SYSCLK: %d
\n
"
,
RCC_ClockFreq
.
SysclkFreq
);
rt_kprintf
(
"HCLK: %d
\n
"
,
RCC_ClockFreq
.
HclkFreq
);
rt_kprintf
(
"PCLK1: %d
\n
"
,
RCC_ClockFreq
.
Pclk1Freq
);
rt_kprintf
(
"PCLK2: %d
\n
"
,
RCC_ClockFreq
.
Pclk2Freq
);
}
void
SetSysClockToHSI
(
void
)
{
RCC_DeInit
();
RCC_EnableHsi
(
ENABLE
);
/* Enable Prefetch Buffer */
FLASH_PrefetchBufSet
(
FLASH_PrefetchBuf_EN
);
/* Flash 0 wait state */
FLASH_SetLatency
(
FLASH_LATENCY_0
);
/* HCLK = SYSCLK */
RCC_ConfigHclk
(
RCC_SYSCLK_DIV1
);
/* PCLK2 = HCLK */
RCC_ConfigPclk2
(
RCC_HCLK_DIV1
);
/* PCLK1 = HCLK */
RCC_ConfigPclk1
(
RCC_HCLK_DIV1
);
/* Select HSE as system clock source */
RCC_ConfigSysclk
(
RCC_SYSCLK_SRC_HSI
);
/* Wait till PLL is used as system clock source */
while
(
RCC_GetSysclkSrc
()
!=
0x00
)
{
}
}
/**
* @brief Selects HSE as System clock source and configure HCLK, PCLK2
* and PCLK1 prescalers.
*/
void
SetSysClockToHSE
(
void
)
{
ErrorStatus
HSEStartUpStatus
;
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration
* -----------------------------*/
/* RCC system reset(for debug purpose) */
RCC_DeInit
();
/* Enable HSE */
RCC_ConfigHse
(
RCC_HSE_ENABLE
);
/* Wait till HSE is ready */
HSEStartUpStatus
=
RCC_WaitHseStable
();
if
(
HSEStartUpStatus
==
SUCCESS
)
{
/* Enable Prefetch Buffer */
FLASH_PrefetchBufSet
(
FLASH_PrefetchBuf_EN
);
if
(
HSE_Value
<=
32000000
)
{
/* Flash 0 wait state */
FLASH_SetLatency
(
FLASH_LATENCY_0
);
}
else
{
/* Flash 1 wait state */
FLASH_SetLatency
(
FLASH_LATENCY_1
);
}
/* HCLK = SYSCLK */
RCC_ConfigHclk
(
RCC_SYSCLK_DIV1
);
/* PCLK2 = HCLK */
RCC_ConfigPclk2
(
RCC_HCLK_DIV1
);
/* PCLK1 = HCLK */
RCC_ConfigPclk1
(
RCC_HCLK_DIV1
);
/* Select HSE as system clock source */
RCC_ConfigSysclk
(
RCC_SYSCLK_SRC_HSE
);
/* Wait till HSE is used as system clock source */
while
(
RCC_GetSysclkSrc
()
!=
0x04
)
{
}
}
else
{
/* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
/* Go to infinite loop */
while
(
1
)
{
}
}
}
void
SetSysClockToPLL
(
uint32_t
freq
,
uint8_t
src
)
{
uint32_t
pllsrc
=
(
src
==
SYSCLK_PLLSRC_HSI
?
RCC_PLL_SRC_HSI_DIV2
:
RCC_PLL_SRC_HSE_DIV2
);
uint32_t
pllmul
;
uint32_t
latency
;
uint32_t
pclk1div
,
pclk2div
;
ErrorStatus
HSEStartUpStatus
;
if
(
HSE_VALUE
!=
8000000
)
{
/* HSE_VALUE == 8000000 is needed in this project! */
while
(
1
)
;
}
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration
* -----------------------------*/
/* RCC system reset(for debug purpose) */
RCC_DeInit
();
if
(
src
==
SYSCLK_PLLSRC_HSE
)
{
/* Enable HSE */
RCC_ConfigHse
(
RCC_HSE_ENABLE
);
/* Wait till HSE is ready */
HSEStartUpStatus
=
RCC_WaitHseStable
();
if
(
HSEStartUpStatus
!=
SUCCESS
)
{
/* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this
error */
/* Go to infinite loop */
while
(
1
)
;
}
}
switch
(
freq
)
{
case
24000000
:
latency
=
FLASH_LATENCY_0
;
pllmul
=
RCC_PLL_MUL_6
;
pclk1div
=
RCC_HCLK_DIV1
;
pclk2div
=
RCC_HCLK_DIV1
;
break
;
case
36000000
:
latency
=
FLASH_LATENCY_1
;
pllmul
=
RCC_PLL_MUL_9
;
pclk1div
=
RCC_HCLK_DIV1
;
pclk2div
=
RCC_HCLK_DIV1
;
break
;
case
48000000
:
latency
=
FLASH_LATENCY_1
;
pllmul
=
RCC_PLL_MUL_12
;
pclk1div
=
RCC_HCLK_DIV2
;
pclk2div
=
RCC_HCLK_DIV1
;
break
;
case
56000000
:
latency
=
FLASH_LATENCY_1
;
pllmul
=
RCC_PLL_MUL_14
;
pclk1div
=
RCC_HCLK_DIV2
;
pclk2div
=
RCC_HCLK_DIV1
;
break
;
case
72000000
:
latency
=
FLASH_LATENCY_2
;
pllmul
=
RCC_PLL_MUL_18
;
pclk1div
=
RCC_HCLK_DIV2
;
pclk2div
=
RCC_HCLK_DIV1
;
break
;
case
96000000
:
latency
=
FLASH_LATENCY_2
;
pllmul
=
RCC_PLL_MUL_24
;
pclk1div
=
RCC_HCLK_DIV4
;
pclk2div
=
RCC_HCLK_DIV2
;
break
;
case
128000000
:
latency
=
FLASH_LATENCY_3
;
pllmul
=
RCC_PLL_MUL_32
;
pclk1div
=
RCC_HCLK_DIV4
;
pclk2div
=
RCC_HCLK_DIV2
;
break
;
case
144000000
:
/* must use HSE as PLL source */
latency
=
FLASH_LATENCY_4
;
pllsrc
=
RCC_PLL_SRC_HSE_DIV1
;
pllmul
=
RCC_PLL_MUL_18
;
pclk1div
=
RCC_HCLK_DIV4
;
pclk2div
=
RCC_HCLK_DIV2
;
break
;
default:
while
(
1
)
;
}
FLASH_SetLatency
(
latency
);
/* HCLK = SYSCLK */
RCC_ConfigHclk
(
RCC_SYSCLK_DIV1
);
/* PCLK2 = HCLK */
RCC_ConfigPclk2
(
pclk2div
);
/* PCLK1 = HCLK */
RCC_ConfigPclk1
(
pclk1div
);
RCC_ConfigPll
(
pllsrc
,
pllmul
);
/* Enable PLL */
RCC_EnablePll
(
ENABLE
);
/* Wait till PLL is ready */
while
(
RCC_GetFlagStatus
(
RCC_FLAG_PLLRD
)
==
RESET
)
;
/* Select PLL as system clock source */
RCC_ConfigSysclk
(
RCC_SYSCLK_SRC_PLLCLK
);
/* Wait till PLL is used as system clock source */
while
(
RCC_GetSysclkSrc
()
!=
0x08
)
;
}
bsp/n32g452xx/Libraries/rt_drivers/drv_clk.h
0 → 100755
浏览文件 @
2de47972
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-20 breo.com first version
*/
#ifndef __DRV_CLK_H__
#define __DRV_CLK_H__
#include <stdint.h>
#include <rtthread.h>
#include <rthw.h>
#ifdef RT_USING_DEVICE
#include <rtdevice.h>
#endif
#ifdef __cplusplus
extern
"C"
{
#endif
void
DumpClock
(
const
char
*
msg
);
void
SetSysClockToHSI
(
void
);
void
SetSysClockToHSE
(
void
);
enum
{
SYSCLK_PLLSRC_HSI
,
SYSCLK_PLLSRC_HSE
,
};
void
SetSysClockToPLL
(
uint32_t
freq
,
uint8_t
src
);
#ifdef __cplusplus
}
#endif
#endif
bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c
浏览文件 @
2de47972
...
...
@@ -763,7 +763,6 @@ int n32_hw_pin_init(void)
result
=
rt_device_pin_register
(
"pin"
,
&
_n32_pin_ops
,
RT_NULL
);
return
result
;
}
INIT_BOARD_EXPORT
(
n32_hw_pin_init
);
rt_inline
void
pin_irq_hdr
(
int
irqno
)
{
...
...
bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.h
浏览文件 @
2de47972
...
...
@@ -10,5 +10,6 @@
#ifndef GPIO_H__
#define GPIO_H__
int
n32_hw_pin_init
(
void
);
#endif
bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.c
浏览文件 @
2de47972
...
...
@@ -49,34 +49,6 @@ enum
#ifdef BSP_USING_HW_TIM8
TIM8_INDEX
,
#endif
#ifdef BSP_USING_HWTIM9
TIM9_INDEX
,
#endif
#ifdef BSP_USING_HWTIM10
TIM10_INDEX
,
#endif
#ifdef BSP_USING_HWTIM11
TIM11_INDEX
,
#endif
#ifdef BSP_USING_HWTIM12
TIM12_INDEX
,
#endif
#ifdef BSP_USING_HWTIM13
TIM13_INDEX
,
#endif
#ifdef BSP_USING_HWTIM14
TIM14_INDEX
,
#endif
#ifdef BSP_USING_HWTIM15
TIM15_INDEX
,
#endif
};
struct
n32_hwtimer
...
...
@@ -120,34 +92,6 @@ static struct n32_hwtimer n32_hwtimer_obj[] =
#ifdef BSP_USING_HWTIM8
TIM8_CONFIG
,
#endif
#ifdef BSP_USING_HWTIM9
TIM9_CONFIG
,
#endif
#ifdef BSP_USING_HWTIM10
TIM10_CONFIG
,
#endif
#ifdef BSP_USING_HWTIM11
TIM11_CONFIG
,
#endif
#ifdef BSP_USING_HWTIM12
TIM12_CONFIG
,
#endif
#ifdef BSP_USING_HWTIM13
TIM13_CONFIG
,
#endif
#ifdef BSP_USING_HWTIM14
TIM14_CONFIG
,
#endif
#ifdef BSP_USING_HWTIM15
TIM15_CONFIG
,
#endif
};
static
void
n32_timer_init
(
struct
rt_hwtimer_device
*
timer
,
rt_uint32_t
state
)
...
...
@@ -155,6 +99,8 @@ static void n32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
RCC_ClocksType
RCC_ClockStruct
;
TIM_TimeBaseInitType
TIM_TimeBaseStructure
;
NVIC_InitType
NVIC_InitStructure
;
uint32_t
freq
=
0
;
uint32_t
input_clock
;
uint32_t
prescaler_value
=
0
;
TIM_Module
*
tim
=
RT_NULL
;
struct
n32_hwtimer
*
tim_device
=
RT_NULL
;
...
...
@@ -165,18 +111,22 @@ static void n32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
tim
=
(
TIM_Module
*
)
timer
->
parent
.
user_data
;
tim_device
=
(
struct
n32_hwtimer
*
)
timer
;
RT_ASSERT
((
tim
==
TIM2
)
||
(
tim
==
TIM3
)
||
(
tim
==
TIM4
)
||
(
tim
==
TIM5
)
||
(
tim
==
TIM6
)
||
(
tim
==
TIM7
));
/* timer clock enable */
n32_msp_hwtim_init
(
tim
);
/* timer init */
freq
=
timer
->
freq
;
RCC_GetClocksFreqValue
(
&
RCC_ClockStruct
);
/* Set timer clock is 1Mhz */
prescaler_value
=
(
uint32_t
)(
RCC_ClockStruct
.
SysclkFreq
/
10000
)
-
1
;
if
(
1
==
(
RCC_ClockStruct
.
HclkFreq
/
RCC_ClockStruct
.
Pclk1Freq
))
input_clock
=
RCC_ClockStruct
.
Pclk1Freq
;
else
input_clock
=
RCC_ClockStruct
.
Pclk1Freq
*
2
;
prescaler_value
=
(
uint32_t
)(
input_clock
/
freq
)
-
1
;
TIM_TimeBaseStructure
.
Period
=
10000
-
1
;
rt_kprintf
(
"Period=[%d]"
,
TIM_TimeBaseStructure
.
Period
);
TIM_TimeBaseStructure
.
Period
=
freq
-
1
;
TIM_TimeBaseStructure
.
Prescaler
=
prescaler_value
;
rt_kprintf
(
"Prescaler=[%d]"
,
TIM_TimeBaseStructure
.
Prescaler
);
TIM_TimeBaseStructure
.
ClkDiv
=
TIM_CLK_DIV1
;
TIM_TimeBaseStructure
.
RepetCnt
=
0
;
...
...
@@ -274,6 +224,7 @@ static rt_err_t n32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
{
case
HWTIMER_CTRL_FREQ_SET
:
{
rt_uint32_t
input_clock
;
rt_uint32_t
freq
;
rt_uint16_t
val
;
...
...
@@ -282,9 +233,11 @@ static rt_err_t n32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
/* time init */
RCC_GetClocksFreqValue
(
&
RCC_ClockStruct
);
val
=
RCC_ClockStruct
.
SysclkFreq
/
freq
;
if
(
1
==
(
RCC_ClockStruct
.
HclkFreq
/
RCC_ClockStruct
.
Pclk1Freq
))
input_clock
=
RCC_ClockStruct
.
Pclk1Freq
;
else
input_clock
=
RCC_ClockStruct
.
Pclk1Freq
*
2
;
val
=
input_clock
/
freq
;
TIM_ConfigPrescaler
(
tim
,
val
-
1
,
TIM_PSC_RELOAD_MODE_IMMEDIATE
);
}
break
;
...
...
bsp/n32g452xx/Libraries/rt_drivers/drv_hwtimer.h
浏览文件 @
2de47972
...
...
@@ -22,7 +22,7 @@ extern "C" {
#define TIM_DEV_INFO_CONFIG \
{ \
.maxfreq = 1000000, \
.minfreq =
4
000, \
.minfreq =
1
000, \
.maxcnt = 0xFFFF, \
.cntmode = HWTIMER_CNTMODE_UP, \
}
...
...
bsp/n32g452xx/Libraries/rt_drivers/drv_soft_i2c.c
浏览文件 @
2de47972
...
...
@@ -214,7 +214,6 @@ int rt_hw_i2c_init(void)
return
RT_EOK
;
}
INIT_BOARD_EXPORT
(
rt_hw_i2c_init
);
#endif
/* RT_USING_I2C */
bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c
浏览文件 @
2de47972
...
...
@@ -554,5 +554,4 @@ int rt_hw_usart_init(void)
return
RT_EOK
;
}
INIT_BOARD_EXPORT
(
rt_hw_usart_init
);
bsp/n32g452xx/Libraries/rt_drivers/drv_usart.h
浏览文件 @
2de47972
...
...
@@ -11,5 +11,6 @@
#ifndef __USART_H__
#define __USART_H__
int
rt_hw_usart_init
(
void
);
#endif
bsp/n32g452xx/n32g452xx-mini-system/.config
浏览文件 @
2de47972
...
...
@@ -31,6 +31,7 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_ASM_MEMCPY is not set
# CONFIG_RT_USING_TINY_FFS is not set
CONFIG_RT_DEBUG
=
y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
...
...
@@ -134,7 +135,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN
=
y
# CONFIG_RT_USING_ADC is not set
CONFIG_RT_USING_ADC
=
y
# CONFIG_RT_USING_DAC is not set
CONFIG_RT_USING_PWM
=
y
# CONFIG_RT_USING_MTD_NOR is not set
...
...
@@ -167,6 +168,7 @@ CONFIG_RT_LIBC_USING_TIME=y
# CONFIG_RT_LIBC_USING_FILEIO is not set
# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_DEFAULT_TIMEZONE
=
8
# CONFIG_RT_USING_POSIX is not set
# CONFIG_RT_USING_PTHREADS is not set
#
...
...
@@ -580,14 +582,14 @@ CONFIG_SOC_N32G452XX=y
#
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_UART
=
y
#
# On-chip Peripheral Drivers
#
CONFIG_
RT
_USING_GPIO
=
y
CONFIG_
BSP
_USING_GPIO
=
y
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
# CONFIG_BSP_USING_WDT is not set
CONFIG_BSP_USING_UART
=
y
CONFIG_BSP_USING_UART1
=
y
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
...
...
bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig
浏览文件 @
2de47972
...
...
@@ -9,9 +9,9 @@ config SOC_N32G452XX
menu "Onboard Peripheral Drivers"
config
RT_USING_SERIAL
config
BSP_USING_UART
bool "Enable USART (uart1)"
select
BSP_USING_UART
select
RT_USING_SERIAL
select BSP_USING_UART1
default y
...
...
@@ -19,7 +19,7 @@ endmenu
menu "On-chip Peripheral Drivers"
config
RT
_USING_GPIO
config
BSP
_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
...
...
bsp/n32g452xx/n32g452xx-mini-system/board/board.c
浏览文件 @
2de47972
...
...
@@ -13,6 +13,7 @@
#include <rtthread.h>
#include <board.h>
#include <drv_clk.h>
#ifdef BSP_USING_SRAM
#include "drv_sram.h"
...
...
@@ -72,6 +73,16 @@ void rt_hw_board_init()
SystemClock_Config
();
#ifdef RT_USING_PIN
int
n32_hw_pin_init
(
void
);
n32_hw_pin_init
();
#endif
#ifdef RT_USING_SERIAL
int
rt_hw_usart_init
(
void
);
rt_hw_usart_init
();
#endif
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init
();
#endif
...
...
bsp/n32g452xx/n32g452xx-mini-system/board/msp/n32_msp.c
浏览文件 @
2de47972
...
...
@@ -8,7 +8,8 @@
* 2021-08-20 breo.com first version
*/
#include <stdio.h>
#include <string.h>
#include <rtthread.h>
#include <rtdevice.h>
#include "n32g45x.h"
...
...
@@ -383,7 +384,7 @@ static void uart_test(void)
static
rt_device_t
u2
=
NULL
;
uart_test_rw
(
u2
,
"uart2"
);
#endif
#ifdef BSP_USING_UART
2
#ifdef BSP_USING_UART
3
static
rt_device_t
u3
=
NULL
;
uart_test_rw
(
u3
,
"uart3"
);
#endif
...
...
bsp/n32g452xx/n32g452xx-mini-system/rtconfig.h
浏览文件 @
2de47972
...
...
@@ -84,6 +84,7 @@
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_USING_ADC
#define RT_USING_PWM
#define RT_USING_WDT
...
...
@@ -175,10 +176,11 @@
/* Onboard Peripheral Drivers */
#define BSP_USING_UART
/* On-chip Peripheral Drivers */
#define RT_USING_GPIO
#define BSP_USING_UART
#define BSP_USING_GPIO
#define BSP_USING_UART1
#endif
bsp/n32g452xx/n32g452xx-mini-system/rtconfig.py
浏览文件 @
2de47972
...
...
@@ -19,18 +19,20 @@ else:
# cross_tool provides the cross compiler
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
if
os
.
getenv
(
'RTT_EXEC_PATH'
):
EXEC_PATH
=
os
.
getenv
(
'RTT_EXEC_PATH'
)
if
CROSS_TOOL
==
'gcc'
:
PLATFORM
=
'gcc'
EXEC_PATH
=
r
'/opt/gcc-arm-none-eabi-6_2-2016q4/bin'
if
(
'EXEC_PATH'
in
dir
())
==
False
:
EXEC_PATH
=
r
'/opt/gcc-arm-none-eabi-6_2-2016q4/bin'
elif
CROSS_TOOL
==
'keil'
:
PLATFORM
=
'armcc'
EXEC_PATH
=
r
'C:/Keil_v5'
if
(
'EXEC_PATH'
in
dir
())
==
False
:
EXEC_PATH
=
r
'C:/Keil_v5'
elif
CROSS_TOOL
==
'iar'
:
PLATFORM
=
'iar'
EXEC_PATH
=
r
'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
if
os
.
getenv
(
'RTT_EXEC_PATH'
):
EXEC_PATH
=
os
.
getenv
(
'RTT_EXEC_PATH'
)
if
(
'EXEC_PATH'
in
dir
())
==
False
:
EXEC_PATH
=
r
'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
BUILD
=
'debug'
...
...
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