update jz47xx branch code.

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@891 bbd45198-f89e-11dd-88c7-29a3b14d5316

libcpu/mips/jz47xx/exception.c

@@ -7,6 +7,7 @@
 #include <rtthread.h>
 #include <rthw.h>
 #include "../common/exception.h"
+#include "../common/mipsregs.h"
 
 /**
  * @addtogroup Jz47xx
@@ -35,9 +36,16 @@ exception_func_t rt_set_except_vector(int n, exception_func_t func)
     return old_handler;
 }
 
-void tlbmiss_handle(rt_uint32_t epc)
+void tlb_refill_handler(void)
 {
-	rt_kprintf("tlb-miss happens, epc: 0x%08x\n", epc);
+	rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
+	rt_hw_cpu_shutdown();
+}
+
+void cache_error_handler(void)
+{
+	rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
+	rt_hw_cpu_shutdown();
 }
 
 static void unhandled_exception_handle(pt_regs_t *regs)

libcpu/mips/jz47xx/start_gcc.S

@@ -3,7 +3,9 @@
  * Change Logs:
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
+ * 2010-09-04     bernard      porting to Jz47xx
  */
+
 #include "../common/mips.inc"
 #include "../common/stackframe.h"
 #include "jz47xx.h"
@@ -11,33 +13,73 @@
     .section ".start", "ax"
     .set noreorder
 
-    .extern sys_exception_handlers
-    .extern tlbmiss_handle
-
-    .globl _entry
-    /* exception entry */
-_entry:
-.org 0x0
+    /* the program entry */
+    .globl  _start
+_start:
     .set    noreorder
-    mfc0    t0, $14
-    jal     tlbmiss_handle
-    move    a0, t0
-    j       _sys_dead                /* TLB Miss, should never happen */
+    la      ra, _start
+
+    /* init cp0 registers. */
+    li	    t0, 0x0040FC00
+    mtc0    t0, CP0_STATUS
+
+    li	    t1, 0x00800000
+    mtc0    t1, CP0_CAUSE
+
+    /* setup stack pointer */
+    li      sp, SYSTEM_STACK
+    la      gp, _gp
+
+    /* init caches, assumes a 4way * 128set * 32byte I/D cache */
+    li      t0, 3            /* enable cache for kseg0 accesses */
+    mtc0    t0, CP0_CONFIG    /* CONFIG reg */
+    la      t0, 0x80000000   /* an idx op should use an unmappable address */
+    ori     t1, t0, 0x4000   /* 16kB cache */
+    mtc0    zero, CP0_TAGLO  /* TAGLO reg */
+    mtc0    zero, CP0_TAGHI  /* TAGHI reg */
+
+_cache_loop:
+    cache   0x8, 0(t0)       /* index store icache tag */
+    cache   0x9, 0(t0)       /* index store dcache tag */
+    bne     t0, t1, _cache_loop
+    addiu   t0, t0, 0x20     /* 32 bytes per cache line */
     nop
-    .set    reorder
 
-    /*
-     * void config_tick_timer(uint32_t perio)
-     */
-    .globl  config_tick_timer
-config_tick_timer:
-    mfc0    t0, $9          /* count */
+    /* invalidate BTB */
+    mfc0    t0, CP0_CONFIG
     nop
-    addu    t1, t0, a0
-    mtc0    t1, $11         /* compare */
-    jr      ra
+    ori     t0, 2
+    mtc0    t0, CP0_CONFIG
     nop
 
+    /* copy IRAM section */
+    la     t0, _iramcopy
+    la     t1, _iramstart
+    la     t2, _iramend
+_iram_loop:
+    lw     t3, 0(t0)
+    sw     t3, 0(t1)
+    addiu  t1, 4
+    bne    t1, t2, _iram_loop
+    addiu  t0, 4
+
+    /* clear bss */
+    la      t0, __bss_start
+    la      t1, __bss_end
+_clr_bss_loop:
+    sw      zero, 0(t0)
+    bne     t0, t1, _clr_bss_loop
+    addiu   t0, t0, 4
+
+    /* jump to RT-Thread RTOS */
+    jal     rtthread_startup
+    nop
+
+    /* restart, never die */
+    j       _start
+    nop
+    .set    reorder
+
     .globl  cp0_get_cause
 cp0_get_cause:
     mfc0    v0, CP0_CAUSE
@@ -62,39 +104,35 @@ cp0_get_lo:
     jr      ra
     nop
 
-.org 0x100
-    .set    noreorder
-    j       _sys_dead                /* cache error exception handle */
-    nop
-    .set    reorder
-
+	.extern tlb_refill_handler
+	.extern cache_error_handler
 
-    .globl  disable_cp0_counter
-disable_cp0_counter:
-    .set    noreorder
-    mfc0    t0, CP0_CAUSE
-    lui     t1, 0x0800
-    or      t0, t1
-    mtc0    t0, CP0_CAUSE
-    jr      ra
+	/* Exception Handler */
+	/* 0x0 - TLB refill handler */
+    .section .vectors.1, "ax", %progbits
+    j      tlb_refill_handler
     nop
-    .set    reorder
-
-    .globl  enable_cp0_counter
-enable_cp0_counter:
-    .set    noreorder
-    mfc0    t0, CP0_CAUSE
-    lui     t1, 0x0800
-    not     t2, t1
-    and     t0, t0, t2
-    mtc0    t0, CP0_CAUSE
-    jr      ra
+	
+	/* 0x100 - Cache error handler */
+    .section .vectors.2, "ax", %progbits
+    j      cache_error_handler
     nop
-    .set    reorder
+    
+	/* 0x180 - Exception/Interrupt handler */
+    .section .vectors.3, "ax", %progbits
+    j      _general_exception_handler
+    nop
+    
+	/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
+    .section .vectors.4, "ax", %progbits
+    j      _irq_handler
+    nop
+	
+    .section .vectors, "ax", %progbits
+	.extern mips_irq_handle
 
-    // general exception handle
-.org 0x180
-_gen_exp_handle:
+    /* general exception handler */
+_general_exception_handler:
     .set    noreorder
     mfc0    k1, CP0_CAUSE
     andi    k1, k1, 0x7c
@@ -104,74 +142,10 @@ _gen_exp_handle:
     nop
     .set    reorder
 
-    /* error happens */
-_sys_dead:
-    .set    noreorder
-    jal     rt_hw_cpu_reset
-    nop
-    /* should never return here */
-    j       _sys_dead
-    nop
-    .set    reorder
-
-
-    .globl mips_irq_handle
-    /* interrupt handle */
-.org 0x200
-_irq_handle:
+    /* interrupt handler */
+_irq_handler:
     .set    noreorder
     la      k0, mips_irq_handle
     jr      k0
     nop
     .set    reorder
-
-
-    /* the REAL program entry */
-    .extern mips32_cfg_init
-    .extern r4k_cache_init
-    .extern install_default_execpt_handle
-    .globl  _start
-.org 0x400
-_start:
-    .set    noreorder
-    la      ra, _start
-
-    /* init cp0 registers. */
-    li	    t0, 0x0040FC00
-    mtc0    t0, CP0_STATUS
-
-    li	    t1, 0x00800000
-    mtc0    t1, CP0_CAUSE
-
-    /* setup stack pointer */
-    li      sp, SYSTEM_STACK
-    la      gp, _gp
-
-    /* clear bss */
-    la      t0, __bss_start
-    la      t1, __bss_end
-_clr_bss_loop:
-    sw      zero, 0(t0)
-    bne     t0, t1, _clr_bss_loop
-    addiu   t0, t0, 4
-
-    /* read core config */
-    jal     mips32_cfg_init
-    nop
-
-    /* initialize cache */
-    jal     r4k_cache_init
-    nop
-
-    /* setup default exception handle */
-    jal     install_default_execpt_handle
-    nop
-
-    /* jump to RT-Thread RTOS */
-    jal     rtthread_startup
-    nop
-
-    /* restart, never die */
-    j       _start
-    nop
-    .set    reorder