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提交 09f698a2 编写于 作者: T tanek liang
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add eth driver

上级 ce4c351e
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Showing with 3561 addition and 88 deletion
bsp/gd32450z-eval/applications/rtgui_demo.c
浏览文件 @ 09f698a2
......@@ -12,15 +12,7 @@
*/
#include <rtthread.h>
#include <rtgui/rtgui.h>
#include <rtgui/rtgui_system.h>
#include <rtgui/rtgui_app.h>
#include <rtgui/widgets/window.h>
#include <rtgui/dc.h>
#include <rtgui/dc_hw.h>
#include "finsh.h"
#include <finsh.h>
#include "rtgui_demo.h"
#define DEBUG
......@@ -33,6 +25,14 @@
#ifdef RT_USING_GUIENGINE
#include <rtgui/rtgui.h>
#include <rtgui/rtgui_system.h>
#include <rtgui/rtgui_app.h>
#include <rtgui/widgets/window.h>
#include <rtgui/dc.h>
#include <rtgui/dc_hw.h>
struct rtgui_win *main_win;
rt_bool_t dc_event_handler(struct rtgui_object *object, rtgui_event_t *event);
......
bsp/gd32450z-eval/drivers/SConscript
浏览文件 @ 09f698a2
......@@ -11,6 +11,7 @@ drv_exmc_sdram.c
drv_usart.c
gd32f450z_lcd_eval.c
drv_lcd.c
drv_enet.c
""")
CPPPATH = [cwd]
......
bsp/gd32450z-eval/drivers/drv_enet.c 0 → 100644
浏览文件 @ 09f698a2
此差异已折叠。
bsp/gd32450z-eval/drivers/drv_lcd.c
浏览文件 @ 09f698a2
......@@ -9,7 +9,7 @@
*
* Change Logs:
* Date Author Notes
* 2009-01-05 Tanek the first version
* 2017-08-23 Tanek the first version
*/
#include "gd32f450z_lcd_eval.h"
......
bsp/gd32450z-eval/drivers/fm3_emac.h 0 → 100644
浏览文件 @ 09f698a2
此差异已折叠。
bsp/gd32450z-eval/drivers/gd32f4xx_libopt.h
浏览文件 @ 09f698a2
......@@ -20,7 +20,7 @@
#include "gd32f4xx_dbg.h"
#include "gd32f4xx_dci.h"
#include "gd32f4xx_dma.h"
#include "gd32f4xx_enet.h"
//#include "gd32f4xx_enet.h"
#include "gd32f4xx_exmc.h"
#include "gd32f4xx_exti.h"
#include "gd32f4xx_fmc.h"
......
bsp/gd32450z-eval/drivers/synopsys_emac.c 0 → 100644
浏览文件 @ 09f698a2
/*
* File : rthw.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include "synopsys_emac.h"
/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
extern EMAC_DMADESCTypeDef *DMATxDescToSet;
extern EMAC_DMADESCTypeDef *DMARxDescToGet;
/**
* Initializes the ETHERNET peripheral according to the specified
*/
rt_uint32_t EMAC_init(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t SystemCoreClock)
{
rt_uint32_t value = 0;
/*-------------------------------- MAC Config ------------------------------*/
/*---------------------- ETHERNET MACMIIAR Configuration -------------------*/
/* Get the ETHERNET MACMIIAR value */
value = ETHERNET_MAC->GAR;
/* Clear CSR Clock Range CR[2:0] bits */
value &= MACMIIAR_CR_MASK;
/* Get hclk frequency value */
/* Set CR bits depending on hclk value */
if((SystemCoreClock >= 20000000)&&(SystemCoreClock < 35000000))
{
/* CSR Clock Range between 20-35 MHz */
value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div16;
}
else if((SystemCoreClock >= 35000000)&&(SystemCoreClock < 60000000))
{
/* CSR Clock Range between 35-60 MHz */
value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div26;
}
else if((SystemCoreClock >= 60000000)&&(SystemCoreClock <= 100000000))
{
/* CSR Clock Range between 60-100 MHz */
value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div42;
}
else if((SystemCoreClock >= 100000000)&&(SystemCoreClock <= 150000000))
{
/* CSR Clock Range between 100-150 MHz */
value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div62;
}
else if((SystemCoreClock >= 150000000)&&(SystemCoreClock <= 250000000))
{
/* CSR Clock Range between 150-250 MHz */
value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div102;
}
else /* if((SystemCoreClock >= 250000000)&&(SystemCoreClock <= 300000000)) */
{
/* CSR Clock Range between 250-300 MHz */
value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div122;
}
/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
ETHERNET_MAC->GAR = (rt_uint32_t)value;
/*------------------------ ETHERNET MACCR Configuration --------------------*/
/* Get the ETHERNET MACCR value */
value = ETHERNET_MAC->MCR;
/* Clear WD, PCE, PS, TE and RE bits */
value &= MACCR_CLEAR_MASK;
value |= (rt_uint32_t)(EMAC_Watchdog_Enable |
EMAC_Jabber_Enable |
EMAC_InterFrameGap_96Bit |
EMAC_CarrierSense_Enable |
EMAC_Speed_100M |
EMAC_ReceiveOwn_Enable |
EMAC_LoopbackMode_Disable |
EMAC_Mode_FullDuplex |
EMAC_ChecksumOffload_Enable |
EMAC_RetryTransmission_Disable |
EMAC_AutomaticPadCRCStrip_Disable |
EMAC_BackOffLimit_10 |
EMAC_DeferralCheck_Disable);
/* Write to ETHERNET MACCR */
value |= (1<<15);
value &= ~(1<<25);
value &= ~(1<<24);
ETHERNET_MAC->MCR = (rt_uint32_t)value;
/*----------------------- ETHERNET MACFFR Configuration --------------------*/
/* Write to ETHERNET MACFFR */
ETHERNET_MAC->MFFR = (rt_uint32_t)(EMAC_ReceiveAll_Enable |
EMAC_SourceAddrFilter_Disable |
EMAC_PassControlFrames_BlockAll |
EMAC_BroadcastFramesReception_Disable |
EMAC_DestinationAddrFilter_Normal |
EMAC_PromiscuousMode_Disable |
EMAC_MulticastFramesFilter_Perfect |
EMAC_UnicastFramesFilter_Perfect);
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
/* Write to ETHERNET MACHTHR */
ETHERNET_MAC->MHTRH = 0;
/* Write to ETHERNET MACHTLR */
ETHERNET_MAC->MHTRL = 0;
/*----------------------- ETHERNET MACFCR Configuration --------------------*/
/* Get the ETHERNET MACFCR value */
value = ETHERNET_MAC->FCR;
/* Clear xx bits */
value &= MACFCR_CLEAR_MASK;
value |= (rt_uint32_t)((0 << 16) |
EMAC_ZeroQuantaPause_Disable |
EMAC_PauseLowThreshold_Minus4 |
EMAC_UnicastPauseFrameDetect_Disable |
EMAC_ReceiveFlowControl_Disable |
EMAC_TransmitFlowControl_Disable);
/* Write to ETHERNET MACFCR */
ETHERNET_MAC->FCR = (rt_uint32_t)value;
/*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
ETHERNET_MAC->VTR = (rt_uint32_t)(EMAC_VLANTagComparison_16Bit |
0);
/*-------------------------------- DMA Config ------------------------------*/
/*----------------------- ETHERNET DMAOMR Configuration --------------------*/
/* Get the ETHERNET DMAOMR value */
value = ETHERNET_MAC->OMR;
/* Clear xx bits */
value &= DMAOMR_CLEAR_MASK;
value |= (rt_uint32_t)(EMAC_DropTCPIPChecksumErrorFrame_Disable |
EMAC_ReceiveStoreForward_Enable |
EMAC_FlushReceivedFrame_Enable |
EMAC_TransmitStoreForward_Enable |
EMAC_TransmitThresholdControl_64Bytes |
EMAC_ForwardErrorFrames_Disable |
EMAC_ForwardUndersizedGoodFrames_Disable |
EMAC_ReceiveThresholdControl_64Bytes |
EMAC_SecondFrameOperate_Disable);
/* Write to ETHERNET DMAOMR */
ETHERNET_MAC->OMR = (rt_uint32_t)value;
/*----------------------- ETHERNET DMABMR Configuration --------------------*/
ETHERNET_MAC->BMR = (rt_uint32_t)(EMAC_AddressAlignedBeats_Enable |
EMAC_FixedBurst_Enable |
EMAC_RxDMABurstLength_32Beat | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
EMAC_TxDMABurstLength_32Beat |
(0 << 2) |
EMAC_DMAArbitration_RoundRobin_RxTx_2_1 |
EMAC_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
/* Return Ethernet configuration success */
return EMAC_SUCCESS;
}
/**
* Enables or disables the specified ETHERNET DMA interrupts.
*/
void EMAC_INT_config(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t EMAC_DMA_IT, rt_bool_t NewState)
{
if (NewState)
{
/* Enable the selected ETHERNET DMA interrupts */
ETHERNET_MAC->IER |= EMAC_DMA_IT;
}
else
{
/* Disable the selected ETHERNET DMA interrupts */
ETHERNET_MAC->IER &=(~(rt_uint32_t)EMAC_DMA_IT);
}
}
/**
* Configures the selected MAC address.
*/
void EMAC_MAC_Addr_config(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t MacAddr, rt_uint8_t *Addr)
{
rt_uint32_t value;
/* Calculate the selectecd MAC address high register */
value = ((rt_uint32_t)Addr[5] << 8) | (rt_uint32_t)Addr[4];
/* Load the selectecd MAC address high register */
//(*(volatile rt_uint32_t *) (EMAC_MAC_ADDR_HBASE + MacAddr)) = value;
ETHERNET_MAC->MARs[MacAddr].MARH = value;
/* Calculate the selectecd MAC address low register */
value = ((rt_uint32_t)Addr[3] << 24) | ((rt_uint32_t)Addr[2] << 16) | ((rt_uint32_t)Addr[1] << 8) | Addr[0];
/* Load the selectecd MAC address low register */
//(*(volatile rt_uint32_t *) (EMAC_MAC_ADDR_LBASE + MacAddr)) = value;
ETHERNET_MAC->MARs[MacAddr].MARL = value;
}
/**
* Enables or disables the MAC transmission.
*/
void EMAC_MACTransmissionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState)
{
if (NewState)
{
/* Enable the MAC transmission */
ETHERNET_MAC->MCR |= EMAC_MACCR_TE;
}
else
{
/* Disable the MAC transmission */
ETHERNET_MAC->MCR &= ~EMAC_MACCR_TE;
}
}
/**
* Clears the ETHERNET transmit FIFO.
*/
void EMAC_FlushTransmitFIFO(struct rt_synopsys_eth * ETHERNET_MAC)
{
/* Set the Flush Transmit FIFO bit */
ETHERNET_MAC->OMR |= EMAC_DMAOMR_FTF;
}
/**
* Enables or disables the MAC reception.
*/
void EMAC_MACReceptionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState)
{
if (NewState)
{
/* Enable the MAC reception */
ETHERNET_MAC->MCR |= EMAC_MACCR_RE;
}
else
{
/* Disable the MAC reception */
ETHERNET_MAC->MCR &= ~EMAC_MACCR_RE;
}
}
/**
* Enables or disables the DMA transmission.
*/
void EMAC_DMATransmissionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState)
{
if (NewState)
{
/* Enable the DMA transmission */
ETHERNET_MAC->OMR |= EMAC_DMAOMR_ST;
}
else
{
/* Disable the DMA transmission */
ETHERNET_MAC->OMR &= ~EMAC_DMAOMR_ST;
}
}
/**
* Enables or disables the DMA reception.
*/
void EMAC_DMAReceptionCmd(struct rt_synopsys_eth * ETHERNET_MAC, rt_bool_t NewState)
{
if (NewState)
{
/* Enable the DMA reception */
ETHERNET_MAC->OMR |= EMAC_DMAOMR_SR;
}
else
{
/* Disable the DMA reception */
ETHERNET_MAC->OMR &= ~EMAC_DMAOMR_SR;
}
}
/**
* Enables ENET MAC and DMA reception/transmission
*/
void EMAC_start(struct rt_synopsys_eth * ETHERNET_MAC)
{
/* Enable transmit state machine of the MAC for transmission on the MII */
EMAC_MACTransmissionCmd(ETHERNET_MAC, RT_TRUE);
/* Flush Transmit FIFO */
EMAC_FlushTransmitFIFO(ETHERNET_MAC);
/* Enable receive state machine of the MAC for reception from the MII */
EMAC_MACReceptionCmd(ETHERNET_MAC, RT_TRUE);
/* Start DMA transmission */
EMAC_DMATransmissionCmd(ETHERNET_MAC, RT_TRUE);
/* Start DMA reception */
EMAC_DMAReceptionCmd(ETHERNET_MAC, RT_TRUE);
}
/**
* Clears the ETHERNET's DMA interrupt pending bit.
*/
void EMAC_clear_pending(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t pending)
{
/* Clear the selected ETHERNET DMA IT */
ETHERNET_MAC->SR = (rt_uint32_t) pending;
}
/**
* Resumes the DMA Transmission by writing to the DmaRxPollDemand register
* (the data written could be anything). This forces the DMA to resume reception.
*/
void EMAC_resume_reception(struct rt_synopsys_eth * ETHERNET_MAC)
{
ETHERNET_MAC->RPDR = 0;
}
/**
* Resumes the DMA Transmission by writing to the DmaTxPollDemand register
* (the data written could be anything). This forces the DMA to resume transmission.
*/
void EMAC_resume_transmission(struct rt_synopsys_eth * ETHERNET_MAC)
{
ETHERNET_MAC->TPDR = 0;
}
/**
* Read a PHY register
*/
rt_uint16_t EMAC_PHY_read(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint16_t PHYAddress, rt_uint16_t PHYReg)
{
rt_uint32_t value = 0;
volatile rt_uint32_t timeout = 0;
/* Get the ETHERNET MACMIIAR value */
value = ETHERNET_MAC->GAR;
/* Keep only the CSR Clock Range CR[2:0] bits value */
value &= ~MACMIIAR_CR_MASK;
/* Prepare the MII address register value */
value |=(((rt_uint32_t)PHYAddress<<11) & EMAC_MACMIIAR_PA); /* Set the PHY device address */
value |=(((rt_uint32_t)PHYReg<<6) & EMAC_MACMIIAR_MR); /* Set the PHY register address */
value &= ~EMAC_MACMIIAR_MW; /* Set the read mode */
value |= EMAC_MACMIIAR_MB; /* Set the MII Busy bit */
/* Write the result value into the MII Address register */
ETHERNET_MAC->GAR = value;
/* Check for the Busy flag */
do
{
timeout++;
value = ETHERNET_MAC->GAR;
}
while ((value & EMAC_MACMIIAR_MB) && (timeout < (rt_uint32_t)PHY_READ_TO));
/* Return ERROR in case of timeout */
if(timeout == PHY_READ_TO)
{
return (rt_uint16_t)EMAC_ERROR;
}
/* Return data register value */
return (rt_uint16_t)(ETHERNET_MAC->GDR);
}
/**
* Write to a PHY register
*/
rt_uint32_t EMAC_PHY_write(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint16_t PHYAddress, rt_uint16_t PHYReg, rt_uint16_t PHYValue)
{
rt_uint32_t value = 0;
volatile rt_uint32_t timeout = 0;
/* Get the ETHERNET MACMIIAR value */
value = ETHERNET_MAC->GAR;
/* Keep only the CSR Clock Range CR[2:0] bits value */
value &= ~MACMIIAR_CR_MASK;
/* Prepare the MII register address value */
value |=(((rt_uint32_t)PHYAddress<<11) & EMAC_MACMIIAR_PA); /* Set the PHY device address */
value |=(((rt_uint32_t)PHYReg<<6) & EMAC_MACMIIAR_MR); /* Set the PHY register address */
value |= EMAC_MACMIIAR_MW; /* Set the write mode */
value |= EMAC_MACMIIAR_MB; /* Set the MII Busy bit */
/* Give the value to the MII data register */
ETHERNET_MAC->GDR = PHYValue;
/* Write the result value into the MII Address register */
ETHERNET_MAC->GAR = value;
/* Check for the Busy flag */
do
{
timeout++;
value = ETHERNET_MAC->GAR;
}
while ((value & EMAC_MACMIIAR_MB) && (timeout < (rt_uint32_t)PHY_WRITE_TO));
/* Return ERROR in case of timeout */
if(timeout == PHY_WRITE_TO)
{
return EMAC_ERROR;
}
/* Return SUCCESS */
return EMAC_SUCCESS;
}
bsp/gd32450z-eval/drivers/synopsys_emac.h 0 → 100644
浏览文件 @ 09f698a2
此差异已折叠。
bsp/gd32450z-eval/project.ewp
浏览文件 @ 09f698a2
......@@ -339,10 +339,14 @@
</option>
<option>
<name>CCIncludePath2</name>
<state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src</state>
<state>$PROJ_DIR$\..\..\..\git\rt-thread\libcpu\arm\cortex-m4</state>
<state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\include</state>
<state>$PROJ_DIR$\..\..\..\git\rt-thread\include</state>
<state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\arch\include</state>
<state>$PROJ_DIR$\drivers</state>
<state>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\include</state>
<state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\include\ipv4</state>
<state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\include\netif</state>
<state>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Include</state>
<state>$PROJ_DIR$\.</state>
<state>$PROJ_DIR$\applications</state>
......@@ -1367,10 +1371,14 @@
</option>
<option>
<name>CCIncludePath2</name>
<state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src</state>
<state>$PROJ_DIR$\..\..\..\git\rt-thread\libcpu\arm\cortex-m4</state>
<state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\include</state>
<state>$PROJ_DIR$\..\..\..\git\rt-thread\include</state>
<state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\arch\include</state>
<state>$PROJ_DIR$\drivers</state>
<state>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\include</state>
<state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\include\ipv4</state>
<state>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\include\netif</state>
<state>$PROJ_DIR$\Libraries\GD32F4xx_standard_peripheral\Include</state>
<state>$PROJ_DIR$\.</state>
<state>$PROJ_DIR$\applications</state>
......@@ -2072,6 +2080,9 @@
<file>
<name>$PROJ_DIR$\applications\mem_test.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\apps\ping\ping.c</name>
</file>
<file>
<name>$PROJ_DIR$\applications\rtgui_demo.c</name>
</file>
......@@ -2141,6 +2152,9 @@
<file>
<name>$PROJ_DIR$\drivers\board.c</name>
</file>
<file>
<name>$PROJ_DIR$\drivers\drv_enet.c</name>
</file>
<file>
<name>$PROJ_DIR$\drivers\drv_exmc_sdram.c</name>
</file>
......@@ -2153,6 +2167,9 @@
<file>
<name>$PROJ_DIR$\drivers\gd32f450z_lcd_eval.c</name>
</file>
<file>
<name>$PROJ_DIR$\drivers\synopsys_emac.c</name>
</file>
</group>
<group>
<name>finsh</name>
......@@ -2293,174 +2310,159 @@
</file>
</group>
<group>
<name>GUIEngine</name>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\asc12font.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\asc16font.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\blit.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\box.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\color.c</name>
</file>
<name>Kernel</name>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\container.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\clock.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\dc.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\components.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\dc_blend.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\device.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\dc_buffer.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\idle.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\dc_client.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\ipc.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\dc_hw.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\irq.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\dc_rotozoom.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\kservice.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\dc_trans.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\mem.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\filerw.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\memheap.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\font.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\mempool.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\font_bmp.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\module.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\font_fnt.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\object.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\font_freetype.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\scheduler.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\font_hz_bmp.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\thread.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\font_hz_file.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\timer.c</name>
</file>
</group>
<group>
<name>LwIP</name>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\hz12font.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\api\api_lib.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\hz16font.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\api\api_msg.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\image.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\ipv4\autoip.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\image_bmp.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\def.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\image_hdc.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\dhcp.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\image_jpg.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\dns.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\image_png.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\api\err.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\image_xpm.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\netif\etharp.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\matrix.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\netif\ethernetif.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\mouse.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\ipv4\icmp.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\region.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\ipv4\igmp.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\rtgui_app.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\ipv4\inet.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\rtgui_driver.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\ipv4\inet_chksum.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\rtgui_object.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\init.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\rtgui_system.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\ipv4\ip.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\server.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\ipv4\ip_addr.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\title.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\ipv4\ip_frag.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\topwin.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\memp.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\widget.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\api\netbuf.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\gui\src\window.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\api\netdb.c</name>
</file>
</group>
<group>
<name>Kernel</name>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\clock.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\netif.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\components.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\api\netifapi.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\device.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\pbuf.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\idle.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\raw.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\ipc.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\netif\slipif.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\irq.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\api\sockets.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\kservice.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\stats.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\mem.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\sys.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\memheap.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\arch\sys_arch.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\mempool.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\tcp.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\module.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\tcp_in.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\object.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\tcp_out.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\scheduler.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\api\tcpip.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\thread.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\timers.c</name>
</file>
<file>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\src\timer.c</name>
<name>$PROJ_DIR$\..\..\..\git\rt-thread\components\net\lwip-1.4.1\src\core\udp.c</name>
</file>
</group>
</project>
bsp/gd32450z-eval/project.uvprojx
浏览文件 @ 09f698a2
......@@ -10,6 +10,7 @@
<TargetName>rt-thread_gd32f4xx</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060422::V5.06 update 4 (build 422)::ARMCC</pCCUsed>
<TargetOption>
<TargetCommonOption>
<Device>GD32F450ZK</Device>
......@@ -403,6 +404,11 @@
<FileType>1</FileType>
<FilePath>applications\startup.c</FilePath>
</File>
<File>
<FileName>rtgui_demo.c</FileName>
<FileType>1</FileType>
<FilePath>.\applications\rtgui_demo.c</FilePath>
</File>
</Files>
</Group>
<Group>
......
bsp/gd32450z-eval/rtconfig.h
浏览文件 @ 09f698a2
......@@ -66,7 +66,7 @@
/* SECTION: RTGUI support */
/* using RTGUI support */
#define RT_USING_GUIENGINE
//#define RT_USING_GUIENGINE
/* name length of RTGUI object */
#define RTGUI_NAME_MAX 16
......@@ -159,7 +159,7 @@
// #define RT_USING_DFS_ROMFS
/* SECTION: lwip, a lighwight TCP/IP protocol stack */
//#define RT_USING_LWIP
#define RT_USING_LWIP
/* LwIP uses RT-Thread Memory Management */
#define RT_LWIP_USING_RT_MEM
/* Enable ICMP protocol*/
......@@ -173,7 +173,7 @@
/* Enable DHCP */
#define RT_LWIP_DHCP
/* Enable DEBUG */
//#define RT_LWIP_DEBUG
#define RT_LWIP_DEBUG
/* the number of simulatenously active TCP connections*/
#define RT_LWIP_TCP_PCB_NUM 5
......@@ -181,13 +181,13 @@
/* ip address of target*/
#define RT_LWIP_IPADDR0 192
#define RT_LWIP_IPADDR1 168
#define RT_LWIP_IPADDR2 1
#define RT_LWIP_IPADDR3 201
#define RT_LWIP_IPADDR2 10
#define RT_LWIP_IPADDR3 222
/* gateway address of target*/
#define RT_LWIP_GWADDR0 192
#define RT_LWIP_GWADDR1 168
#define RT_LWIP_GWADDR2 1
#define RT_LWIP_GWADDR2 10
#define RT_LWIP_GWADDR3 1
/* mask address of target*/
......
bsp/stm32f10x/project.uvprojx
浏览文件 @ 09f698a2
......@@ -10,6 +10,8 @@
<TargetName>rtthread-stm32</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pArmCC>5050169::V5.05 update 2 (build 169)::.\ARMCC_505u2</pArmCC>
<pCCUsed>5050169::V5.05 update 2 (build 169)::.\ARMCC_505u2</pCCUsed>
<TargetOption>
<TargetCommonOption>
<Device>STM32F103ZE</Device>
......
bsp/stm32f10x/rtconfig.h
浏览文件 @ 09f698a2
......@@ -194,4 +194,6 @@
/* nanopb support */
/* #define RT_USING_NANOPB */
#define RT_USING_CPU_FFS
#endif
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