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体验新版 GitCode,发现更多精彩内容 >>
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e8a80f52
编写于
3月 18, 2021
作者:
Thomas_Fly
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bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Inc/stm32h7xx_it.h
...50-artpi-h750/board/CubeMX_Config/Core/Inc/stm32h7xx_it.h
+0
-69
bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Src/main.c
.../stm32h750-artpi-h750/board/CubeMX_Config/Core/Src/main.c
+0
-332
bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Src/stm32h7xx_it.c
...50-artpi-h750/board/CubeMX_Config/Core/Src/stm32h7xx_it.c
+0
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bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Src/system_stm32h7xx.c
...rtpi-h750/board/CubeMX_Config/Core/Src/system_stm32h7xx.c
+0
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未找到文件。
bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Inc/stm32h7xx_it.h
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浏览文件 @
3e9c2e02
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32h7xx_it.h
* @brief This file contains the headers of the interrupt handlers.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_IT_H
#define __STM32H7xx_IT_H
#ifdef __cplusplus
extern
"C"
{
#endif
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
/* USER CODE BEGIN ET */
/* USER CODE END ET */
/* Exported constants --------------------------------------------------------*/
/* USER CODE BEGIN EC */
/* USER CODE END EC */
/* Exported macro ------------------------------------------------------------*/
/* USER CODE BEGIN EM */
/* USER CODE END EM */
/* Exported functions prototypes ---------------------------------------------*/
void
NMI_Handler
(
void
);
void
HardFault_Handler
(
void
);
void
MemManage_Handler
(
void
);
void
BusFault_Handler
(
void
);
void
UsageFault_Handler
(
void
);
void
SVC_Handler
(
void
);
void
DebugMon_Handler
(
void
);
void
PendSV_Handler
(
void
);
void
SysTick_Handler
(
void
);
/* USER CODE BEGIN EFP */
/* USER CODE END EFP */
#ifdef __cplusplus
}
#endif
#endif
/* __STM32H7xx_IT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Src/main.c
已删除
100644 → 0
浏览文件 @
3e9c2e02
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file : main.c
* @brief : Main program body
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
/* USER CODE END PTD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
UART_HandleTypeDef
huart4
;
UART_HandleTypeDef
huart3
;
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void
SystemClock_Config
(
void
);
static
void
MX_GPIO_Init
(
void
);
static
void
MX_UART4_Init
(
void
);
static
void
MX_USART3_UART_Init
(
void
);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/**
* @brief The application entry point.
* @retval int
*/
int
main
(
void
)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init
();
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config
();
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init
();
MX_UART4_Init
();
MX_USART3_UART_Init
();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while
(
1
)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
HAL_Delay
(
5000
);
HAL_GPIO_TogglePin
(
GPIOI
,
GPIO_PIN_8
);
}
/* USER CODE END 3 */
}
/**
* @brief System Clock Configuration
* @retval None
*/
void
SystemClock_Config
(
void
)
{
RCC_OscInitTypeDef
RCC_OscInitStruct
=
{
0
};
RCC_ClkInitTypeDef
RCC_ClkInitStruct
=
{
0
};
RCC_PeriphCLKInitTypeDef
PeriphClkInitStruct
=
{
0
};
/** Supply configuration update enable
*/
HAL_PWREx_ConfigSupply
(
PWR_LDO_SUPPLY
);
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG
(
PWR_REGULATOR_VOLTAGE_SCALE0
);
while
(
!
__HAL_PWR_GET_FLAG
(
PWR_FLAG_VOSRDY
))
{}
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_HSE
;
RCC_OscInitStruct
.
HSEState
=
RCC_HSE_ON
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_ON
;
RCC_OscInitStruct
.
PLL
.
PLLSource
=
RCC_PLLSOURCE_HSE
;
RCC_OscInitStruct
.
PLL
.
PLLM
=
5
;
RCC_OscInitStruct
.
PLL
.
PLLN
=
192
;
RCC_OscInitStruct
.
PLL
.
PLLP
=
2
;
RCC_OscInitStruct
.
PLL
.
PLLQ
=
2
;
RCC_OscInitStruct
.
PLL
.
PLLR
=
2
;
RCC_OscInitStruct
.
PLL
.
PLLRGE
=
RCC_PLL1VCIRANGE_2
;
RCC_OscInitStruct
.
PLL
.
PLLVCOSEL
=
RCC_PLL1VCOWIDE
;
RCC_OscInitStruct
.
PLL
.
PLLFRACN
=
0
;
if
(
HAL_RCC_OscConfig
(
&
RCC_OscInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct
.
ClockType
=
RCC_CLOCKTYPE_HCLK
|
RCC_CLOCKTYPE_SYSCLK
|
RCC_CLOCKTYPE_PCLK1
|
RCC_CLOCKTYPE_PCLK2
|
RCC_CLOCKTYPE_D3PCLK1
|
RCC_CLOCKTYPE_D1PCLK1
;
RCC_ClkInitStruct
.
SYSCLKSource
=
RCC_SYSCLKSOURCE_PLLCLK
;
RCC_ClkInitStruct
.
SYSCLKDivider
=
RCC_SYSCLK_DIV1
;
RCC_ClkInitStruct
.
AHBCLKDivider
=
RCC_HCLK_DIV2
;
RCC_ClkInitStruct
.
APB3CLKDivider
=
RCC_APB3_DIV2
;
RCC_ClkInitStruct
.
APB1CLKDivider
=
RCC_APB1_DIV2
;
RCC_ClkInitStruct
.
APB2CLKDivider
=
RCC_APB2_DIV2
;
RCC_ClkInitStruct
.
APB4CLKDivider
=
RCC_APB4_DIV2
;
if
(
HAL_RCC_ClockConfig
(
&
RCC_ClkInitStruct
,
FLASH_LATENCY_4
)
!=
HAL_OK
)
{
Error_Handler
();
}
PeriphClkInitStruct
.
PeriphClockSelection
=
RCC_PERIPHCLK_USART3
|
RCC_PERIPHCLK_UART4
;
PeriphClkInitStruct
.
Usart234578ClockSelection
=
RCC_USART234578CLKSOURCE_D2PCLK1
;
if
(
HAL_RCCEx_PeriphCLKConfig
(
&
PeriphClkInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
}
/**
* @brief UART4 Initialization Function
* @param None
* @retval None
*/
static
void
MX_UART4_Init
(
void
)
{
/* USER CODE BEGIN UART4_Init 0 */
/* USER CODE END UART4_Init 0 */
/* USER CODE BEGIN UART4_Init 1 */
/* USER CODE END UART4_Init 1 */
huart4
.
Instance
=
UART4
;
huart4
.
Init
.
BaudRate
=
115200
;
huart4
.
Init
.
WordLength
=
UART_WORDLENGTH_8B
;
huart4
.
Init
.
StopBits
=
UART_STOPBITS_1
;
huart4
.
Init
.
Parity
=
UART_PARITY_NONE
;
huart4
.
Init
.
Mode
=
UART_MODE_TX_RX
;
huart4
.
Init
.
HwFlowCtl
=
UART_HWCONTROL_NONE
;
huart4
.
Init
.
OverSampling
=
UART_OVERSAMPLING_16
;
huart4
.
Init
.
OneBitSampling
=
UART_ONE_BIT_SAMPLE_DISABLE
;
huart4
.
Init
.
ClockPrescaler
=
UART_PRESCALER_DIV1
;
huart4
.
AdvancedInit
.
AdvFeatureInit
=
UART_ADVFEATURE_NO_INIT
;
if
(
HAL_UART_Init
(
&
huart4
)
!=
HAL_OK
)
{
Error_Handler
();
}
if
(
HAL_UARTEx_SetTxFifoThreshold
(
&
huart4
,
UART_TXFIFO_THRESHOLD_1_8
)
!=
HAL_OK
)
{
Error_Handler
();
}
if
(
HAL_UARTEx_SetRxFifoThreshold
(
&
huart4
,
UART_RXFIFO_THRESHOLD_1_8
)
!=
HAL_OK
)
{
Error_Handler
();
}
if
(
HAL_UARTEx_DisableFifoMode
(
&
huart4
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN UART4_Init 2 */
/* USER CODE END UART4_Init 2 */
}
/**
* @brief USART3 Initialization Function
* @param None
* @retval None
*/
static
void
MX_USART3_UART_Init
(
void
)
{
/* USER CODE BEGIN USART3_Init 0 */
/* USER CODE END USART3_Init 0 */
/* USER CODE BEGIN USART3_Init 1 */
/* USER CODE END USART3_Init 1 */
huart3
.
Instance
=
USART3
;
huart3
.
Init
.
BaudRate
=
115200
;
huart3
.
Init
.
WordLength
=
UART_WORDLENGTH_8B
;
huart3
.
Init
.
StopBits
=
UART_STOPBITS_1
;
huart3
.
Init
.
Parity
=
UART_PARITY_NONE
;
huart3
.
Init
.
Mode
=
UART_MODE_TX_RX
;
huart3
.
Init
.
HwFlowCtl
=
UART_HWCONTROL_RTS_CTS
;
huart3
.
Init
.
OverSampling
=
UART_OVERSAMPLING_16
;
huart3
.
Init
.
OneBitSampling
=
UART_ONE_BIT_SAMPLE_DISABLE
;
huart3
.
Init
.
ClockPrescaler
=
UART_PRESCALER_DIV1
;
huart3
.
AdvancedInit
.
AdvFeatureInit
=
UART_ADVFEATURE_NO_INIT
;
if
(
HAL_UART_Init
(
&
huart3
)
!=
HAL_OK
)
{
Error_Handler
();
}
if
(
HAL_UARTEx_SetTxFifoThreshold
(
&
huart3
,
UART_TXFIFO_THRESHOLD_1_8
)
!=
HAL_OK
)
{
Error_Handler
();
}
if
(
HAL_UARTEx_SetRxFifoThreshold
(
&
huart3
,
UART_RXFIFO_THRESHOLD_1_8
)
!=
HAL_OK
)
{
Error_Handler
();
}
if
(
HAL_UARTEx_DisableFifoMode
(
&
huart3
)
!=
HAL_OK
)
{
Error_Handler
();
}
/* USER CODE BEGIN USART3_Init 2 */
/* USER CODE END USART3_Init 2 */
}
/**
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static
void
MX_GPIO_Init
(
void
)
{
GPIO_InitTypeDef
GPIO_InitStruct
=
{
0
};
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOI_CLK_ENABLE
();
__HAL_RCC_GPIOH_CLK_ENABLE
();
__HAL_RCC_GPIOA_CLK_ENABLE
();
__HAL_RCC_GPIOB_CLK_ENABLE
();
__HAL_RCC_GPIOD_CLK_ENABLE
();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin
(
GPIOI
,
GPIO_PIN_8
,
GPIO_PIN_RESET
);
/*Configure GPIO pin : PI8 */
GPIO_InitStruct
.
Pin
=
GPIO_PIN_8
;
GPIO_InitStruct
.
Mode
=
GPIO_MODE_OUTPUT_PP
;
GPIO_InitStruct
.
Pull
=
GPIO_NOPULL
;
GPIO_InitStruct
.
Speed
=
GPIO_SPEED_FREQ_LOW
;
HAL_GPIO_Init
(
GPIOI
,
&
GPIO_InitStruct
);
}
/* USER CODE BEGIN 4 */
/* USER CODE END 4 */
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void
Error_Handler
(
void
)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
/* USER CODE END Error_Handler_Debug */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void
assert_failed
(
uint8_t
*
file
,
uint32_t
line
)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif
/* USE_FULL_ASSERT */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Src/stm32h7xx_it.c
已删除
100644 → 0
浏览文件 @
3e9c2e02
/* USER CODE BEGIN Header */
/**
******************************************************************************
* @file stm32h7xx_it.c
* @brief Interrupt Service Routines.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* USER CODE END Header */
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "stm32h7xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN TD */
/* USER CODE END TD */
/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
/* USER CODE END PD */
/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
/* External variables --------------------------------------------------------*/
extern
UART_HandleTypeDef
huart4
;
extern
UART_HandleTypeDef
huart3
;
/* USER CODE BEGIN EV */
/* USER CODE END EV */
/******************************************************************************/
/* Cortex Processor Interruption and Exception Handlers */
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void
NMI_Handler
(
void
)
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
/* USER CODE END NonMaskableInt_IRQn 1 */
}
/**
* @brief This function handles Hard fault interrupt.
*/
void
HardFault_Handler
(
void
)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while
(
1
)
{
/* USER CODE BEGIN W1_HardFault_IRQn 0 */
/* USER CODE END W1_HardFault_IRQn 0 */
}
}
/**
* @brief This function handles Memory management fault.
*/
void
MemManage_Handler
(
void
)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while
(
1
)
{
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
/* USER CODE END W1_MemoryManagement_IRQn 0 */
}
}
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void
BusFault_Handler
(
void
)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while
(
1
)
{
/* USER CODE BEGIN W1_BusFault_IRQn 0 */
/* USER CODE END W1_BusFault_IRQn 0 */
}
}
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void
UsageFault_Handler
(
void
)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while
(
1
)
{
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */
/* USER CODE END W1_UsageFault_IRQn 0 */
}
}
/**
* @brief This function handles System service call via SWI instruction.
*/
void
SVC_Handler
(
void
)
{
/* USER CODE BEGIN SVCall_IRQn 0 */
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
/**
* @brief This function handles Debug monitor.
*/
void
DebugMon_Handler
(
void
)
{
/* USER CODE BEGIN DebugMonitor_IRQn 0 */
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
/**
* @brief This function handles Pendable request for system service.
*/
void
PendSV_Handler
(
void
)
{
/* USER CODE BEGIN PendSV_IRQn 0 */
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
/**
* @brief This function handles System tick timer.
*/
void
SysTick_Handler
(
void
)
{
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick
();
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
/******************************************************************************/
/* STM32H7xx Peripheral Interrupt Handlers */
/* Add here the Interrupt Handlers for the used peripherals. */
/* For the available peripheral interrupt handler names, */
/* please refer to the startup file (startup_stm32h7xx.s). */
/******************************************************************************/
/**
* @brief This function handles USART3 global interrupt.
*/
void
USART3_IRQHandler
(
void
)
{
/* USER CODE BEGIN USART3_IRQn 0 */
/* USER CODE END USART3_IRQn 0 */
HAL_UART_IRQHandler
(
&
huart3
);
/* USER CODE BEGIN USART3_IRQn 1 */
/* USER CODE END USART3_IRQn 1 */
}
/**
* @brief This function handles UART4 global interrupt.
*/
void
UART4_IRQHandler
(
void
)
{
/* USER CODE BEGIN UART4_IRQn 0 */
/* USER CODE END UART4_IRQn 0 */
HAL_UART_IRQHandler
(
&
huart4
);
/* USER CODE BEGIN UART4_IRQn 1 */
/* USER CODE END UART4_IRQn 1 */
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/stm32/stm32h750-artpi-h750/board/CubeMX_Config/Core/Src/system_stm32h7xx.c
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/**
******************************************************************************
* @file system_stm32h7xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32h7xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock, it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32h7xx_system
* @{
*/
/** @addtogroup STM32H7xx_System_Private_Includes
* @{
*/
#include "stm32h7xx.h"
#include <math.h>
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000)
/*!< Value of the External oscillator in Hz */
#endif
/* HSE_VALUE */
#if !defined (CSI_VALUE)
#define CSI_VALUE ((uint32_t)4000000)
/*!< Value of the Internal oscillator in Hz*/
#endif
/* CSI_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)64000000)
/*!< Value of the Internal oscillator in Hz*/
#endif
/* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
/* #define DATA_IN_D2_SRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00000000UL
/*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t
SystemCoreClock
=
64000000
;
uint32_t
SystemD2Clock
=
64000000
;
const
uint8_t
D1CorePrescTable
[
16
]
=
{
0
,
0
,
0
,
0
,
1
,
2
,
3
,
4
,
1
,
2
,
3
,
4
,
6
,
7
,
8
,
9
};
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32H7xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting and vector table location
* configuration.
* @param None
* @retval None
*/
void
SystemInit
(
void
)
{
#if defined (DATA_IN_D2_SRAM)
__IO
uint32_t
tmpreg
;
#endif
/* DATA_IN_D2_SRAM */
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB
->
CPACR
|=
((
3UL
<<
(
10
*
2
))
|
(
3UL
<<
(
11
*
2
)));
/* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Increasing the CPU frequency */
if
(
FLASH_LATENCY_DEFAULT
>
(
READ_BIT
((
FLASH
->
ACR
),
FLASH_ACR_LATENCY
)))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
MODIFY_REG
(
FLASH
->
ACR
,
FLASH_ACR_LATENCY
,
(
uint32_t
)(
FLASH_LATENCY_DEFAULT
));
}
/* Set HSION bit */
RCC
->
CR
|=
RCC_CR_HSION
;
/* Reset CFGR register */
RCC
->
CFGR
=
0x00000000
;
/* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
RCC
->
CR
&=
0xEAF6ED7FU
;
/* Decreasing the number of wait states because of lower CPU frequency */
if
(
FLASH_LATENCY_DEFAULT
<
(
READ_BIT
((
FLASH
->
ACR
),
FLASH_ACR_LATENCY
)))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
MODIFY_REG
(
FLASH
->
ACR
,
FLASH_ACR_LATENCY
,
(
uint32_t
)(
FLASH_LATENCY_DEFAULT
));
}
#if defined(D3_SRAM_BASE)
/* Reset D1CFGR register */
RCC
->
D1CFGR
=
0x00000000
;
/* Reset D2CFGR register */
RCC
->
D2CFGR
=
0x00000000
;
/* Reset D3CFGR register */
RCC
->
D3CFGR
=
0x00000000
;
#else
/* Reset CDCFGR1 register */
RCC
->
CDCFGR1
=
0x00000000
;
/* Reset CDCFGR2 register */
RCC
->
CDCFGR2
=
0x00000000
;
/* Reset SRDCFGR register */
RCC
->
SRDCFGR
=
0x00000000
;
#endif
/* Reset PLLCKSELR register */
RCC
->
PLLCKSELR
=
0x02020200
;
/* Reset PLLCFGR register */
RCC
->
PLLCFGR
=
0x01FF0000
;
/* Reset PLL1DIVR register */
RCC
->
PLL1DIVR
=
0x01010280
;
/* Reset PLL1FRACR register */
RCC
->
PLL1FRACR
=
0x00000000
;
/* Reset PLL2DIVR register */
RCC
->
PLL2DIVR
=
0x01010280
;
/* Reset PLL2FRACR register */
RCC
->
PLL2FRACR
=
0x00000000
;
/* Reset PLL3DIVR register */
RCC
->
PLL3DIVR
=
0x01010280
;
/* Reset PLL3FRACR register */
RCC
->
PLL3FRACR
=
0x00000000
;
/* Reset HSEBYP bit */
RCC
->
CR
&=
0xFFFBFFFFU
;
/* Disable all interrupts */
RCC
->
CIER
=
0x00000000
;
#if (STM32H7_DEV_ID == 0x450UL)
/* dual core CM7 or single core line */
if
((
DBGMCU
->
IDCODE
&
0xFFFF0000U
)
<
0x20000000U
)
{
/* if stm32h7 revY*/
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
*
((
__IO
uint32_t
*
)
0x51008108
)
=
0x000000001U
;
}
#endif
#if defined (DATA_IN_D2_SRAM)
/* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
#if defined(RCC_AHB2ENR_D2SRAM3EN)
RCC
->
AHB2ENR
|=
(
RCC_AHB2ENR_D2SRAM1EN
|
RCC_AHB2ENR_D2SRAM2EN
|
RCC_AHB2ENR_D2SRAM3EN
);
#elif defined(RCC_AHB2ENR_D2SRAM2EN)
RCC
->
AHB2ENR
|=
(
RCC_AHB2ENR_D2SRAM1EN
|
RCC_AHB2ENR_D2SRAM2EN
);
#else
RCC
->
AHB2ENR
|=
(
RCC_AHB2ENR_AHBSRAM1EN
|
RCC_AHB2ENR_AHBSRAM2EN
);
#endif
/* RCC_AHB2ENR_D2SRAM3EN */
tmpreg
=
RCC
->
AHB2ENR
;
(
void
)
tmpreg
;
#endif
/* DATA_IN_D2_SRAM */
#if defined(DUAL_CORE) && defined(CORE_CM4)
/* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
#ifdef VECT_TAB_SRAM
SCB
->
VTOR
=
D2_AXISRAM_BASE
|
VECT_TAB_OFFSET
;
/* Vector Table Relocation in Internal SRAM */
#else
SCB
->
VTOR
=
FLASH_BANK2_BASE
|
VECT_TAB_OFFSET
;
/* Vector Table Relocation in Internal FLASH */
#endif
/* VECT_TAB_SRAM */
#else
/*
* Disable the FMC bank1 (enabled after reset).
* This, prevents CPU speculation access on this bank which blocks the use of FMC during
* 24us. During this time the others FMC master (such as LTDC) cannot use it!
*/
FMC_Bank1_R
->
BTCR
[
0
]
=
0x000030D2
;
/* Configure the Vector Table location add offset address for cortex-M7 ------------------*/
#ifdef VECT_TAB_SRAM
SCB
->
VTOR
=
D1_AXISRAM_BASE
|
VECT_TAB_OFFSET
;
/* Vector Table Relocation in Internal AXI-RAM */
#else
SCB
->
VTOR
=
FLASH_BANK1_BASE
|
VECT_TAB_OFFSET
;
/* Vector Table Relocation in Internal FLASH */
#endif
#endif
/*DUAL_CORE && CORE_CM4*/
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock , it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
* - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
*
* (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 4 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
* (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 64 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
* @param None
* @retval None
*/
void
SystemCoreClockUpdate
(
void
)
{
uint32_t
pllp
,
pllsource
,
pllm
,
pllfracen
,
hsivalue
,
tmp
;
uint32_t
common_system_clock
;
float_t
fracn1
,
pllvco
;
/* Get SYSCLK source -------------------------------------------------------*/
switch
(
RCC
->
CFGR
&
RCC_CFGR_SWS
)
{
case
RCC_CFGR_SWS_HSI
:
/* HSI used as system clock source */
common_system_clock
=
(
uint32_t
)
(
HSI_VALUE
>>
((
RCC
->
CR
&
RCC_CR_HSIDIV
)
>>
3
));
break
;
case
RCC_CFGR_SWS_CSI
:
/* CSI used as system clock source */
common_system_clock
=
CSI_VALUE
;
break
;
case
RCC_CFGR_SWS_HSE
:
/* HSE used as system clock source */
common_system_clock
=
HSE_VALUE
;
break
;
case
RCC_CFGR_SWS_PLL1
:
/* PLL1 used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource
=
(
RCC
->
PLLCKSELR
&
RCC_PLLCKSELR_PLLSRC
);
pllm
=
((
RCC
->
PLLCKSELR
&
RCC_PLLCKSELR_DIVM1
)
>>
4
)
;
pllfracen
=
((
RCC
->
PLLCFGR
&
RCC_PLLCFGR_PLL1FRACEN
)
>>
RCC_PLLCFGR_PLL1FRACEN_Pos
);
fracn1
=
(
float_t
)(
uint32_t
)(
pllfracen
*
((
RCC
->
PLL1FRACR
&
RCC_PLL1FRACR_FRACN1
)
>>
3
));
if
(
pllm
!=
0U
)
{
switch
(
pllsource
)
{
case
RCC_PLLCKSELR_PLLSRC_HSI
:
/* HSI used as PLL clock source */
hsivalue
=
(
HSI_VALUE
>>
((
RCC
->
CR
&
RCC_CR_HSIDIV
)
>>
3
))
;
pllvco
=
(
(
float_t
)
hsivalue
/
(
float_t
)
pllm
)
*
((
float_t
)(
uint32_t
)(
RCC
->
PLL1DIVR
&
RCC_PLL1DIVR_N1
)
+
(
fracn1
/
(
float_t
)
0x2000
)
+
(
float_t
)
1
);
break
;
case
RCC_PLLCKSELR_PLLSRC_CSI
:
/* CSI used as PLL clock source */
pllvco
=
((
float_t
)
CSI_VALUE
/
(
float_t
)
pllm
)
*
((
float_t
)(
uint32_t
)(
RCC
->
PLL1DIVR
&
RCC_PLL1DIVR_N1
)
+
(
fracn1
/
(
float_t
)
0x2000
)
+
(
float_t
)
1
);
break
;
case
RCC_PLLCKSELR_PLLSRC_HSE
:
/* HSE used as PLL clock source */
pllvco
=
((
float_t
)
HSE_VALUE
/
(
float_t
)
pllm
)
*
((
float_t
)(
uint32_t
)(
RCC
->
PLL1DIVR
&
RCC_PLL1DIVR_N1
)
+
(
fracn1
/
(
float_t
)
0x2000
)
+
(
float_t
)
1
);
break
;
default:
pllvco
=
((
float_t
)
CSI_VALUE
/
(
float_t
)
pllm
)
*
((
float_t
)(
uint32_t
)(
RCC
->
PLL1DIVR
&
RCC_PLL1DIVR_N1
)
+
(
fracn1
/
(
float_t
)
0x2000
)
+
(
float_t
)
1
);
break
;
}
pllp
=
(((
RCC
->
PLL1DIVR
&
RCC_PLL1DIVR_P1
)
>>
9
)
+
1U
)
;
common_system_clock
=
(
uint32_t
)(
float_t
)(
pllvco
/
(
float_t
)
pllp
);
}
else
{
common_system_clock
=
0U
;
}
break
;
default:
common_system_clock
=
CSI_VALUE
;
break
;
}
/* Compute SystemClock frequency --------------------------------------------------*/
#if defined (RCC_D1CFGR_D1CPRE)
tmp
=
D1CorePrescTable
[(
RCC
->
D1CFGR
&
RCC_D1CFGR_D1CPRE
)
>>
RCC_D1CFGR_D1CPRE_Pos
];
/* common_system_clock frequency : CM7 CPU frequency */
common_system_clock
>>=
tmp
;
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
SystemD2Clock
=
(
common_system_clock
>>
((
D1CorePrescTable
[(
RCC
->
D1CFGR
&
RCC_D1CFGR_HPRE
)
>>
RCC_D1CFGR_HPRE_Pos
])
&
0x1FU
));
#else
tmp
=
D1CorePrescTable
[(
RCC
->
CDCFGR1
&
RCC_CDCFGR1_CDCPRE
)
>>
RCC_CDCFGR1_CDCPRE_Pos
];
/* common_system_clock frequency : CM7 CPU frequency */
common_system_clock
>>=
tmp
;
/* SystemD2Clock frequency : AXI and AHBs Clock frequency */
SystemD2Clock
=
(
common_system_clock
>>
((
D1CorePrescTable
[(
RCC
->
CDCFGR1
&
RCC_CDCFGR1_HPRE
)
>>
RCC_CDCFGR1_HPRE_Pos
])
&
0x1FU
));
#endif
#if defined(DUAL_CORE) && defined(CORE_CM4)
SystemCoreClock
=
SystemD2Clock
;
#else
SystemCoreClock
=
common_system_clock
;
#endif
/* DUAL_CORE && CORE_CM4 */
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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