1.add can and on-chip-flash drivers 2.fixed c++ compiler error

bsp/at32/Libraries/AT32_Std_Driver/AT32F4xx_StdPeriph_Driver/inc/at32f4xx_ertc.h

@@ -11,6 +11,9 @@
 #ifndef __AT32F4xx_ERTC_H
 #define __AT32F4xx_ERTC_H
 
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 /* Includes ------------------------------------------------------------------*/
 #include "at32f4xx.h"

bsp/at32/Libraries/rt_drivers/SConscript

@@ -43,9 +43,15 @@ if GetDepend('BSP_USING_SRAM'):
 if GetDepend('BSP_USING_RTC'):
     src += ['drv_rtc.c']
 
+if GetDepend('BSP_USING_ON_CHIP_FLASH'):
+    src += ['drv_flash.c']
+
 if GetDepend(['BSP_USING_WDT']):
     src += ['drv_wdt.c']
 
+if GetDepend(['BSP_USING_CAN']):
+    src += ['drv_can.c']
+
 if GetDepend(['BSP_USING_SDIO']):
     src += ['drv_sdio.c']
 

bsp/at32/Libraries/rt_drivers/drv_can.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-02-09     shelton      the first version
+ */
+
+#ifndef __DRV_CAN_H__
+#define __DRV_CAN_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <board.h>
+#include <rtdevice.h>
+#include <rtthread.h>
+
+#define CAN_TX_MAILBOX0             (0x00000001U)  /*!< Tx Mailbox 0  */
+#define CAN_TX_MAILBOX1             (0x00000002U)  /*!< Tx Mailbox 1  */
+#define CAN_TX_MAILBOX2             (0x00000004U)  /*!< Tx Mailbox 2  */
+  
+struct at32_baud_rate_tab
+{
+    rt_uint32_t baud_rate;
+    rt_uint32_t sjw;
+    rt_uint32_t bs1;
+    rt_uint32_t bs2;
+    rt_uint32_t psc;
+};
+
+struct CAN_Handler
+{
+    CAN_Type *Instance;
+    CAN_InitType CanInit;
+    CAN_FilterInitType FilterConfig;
+};
+
+/* at32 can device */
+struct at32_can
+{
+    char *name;
+    struct CAN_Handler CanConfig;
+    struct rt_can_device device;     /* inherit from can device */
+};
+
+int rt_hw_can_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__DRV_CAN_H__ */
+
+/************************** end of file ******************/

bsp/at32/Libraries/rt_drivers/drv_flash.c

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-02-09     shelton      the first version
+ */
+
+#include <board.h>
+#include <rtthread.h>
+
+#ifdef BSP_USING_ON_CHIP_FLASH
+#include "drv_flash.h"
+
+#if defined(PKG_USING_FAL)
+#include "fal.h"
+#endif
+
+//#define DRV_DEBUG
+#define LOG_TAG                "drv.flash"
+#include <drv_log.h>
+
+/**
+  * @brief  Gets the page of a given address
+  * @param  addr: address of the flash memory
+  * @retval The page of a given address
+  */
+static rt_uint32_t get_page(uint32_t addr)
+{
+    rt_uint32_t page = 0;
+
+    page = RT_ALIGN_DOWN(addr, FLASH_PAGE_SIZE);
+
+    return page;
+}
+
+/**
+ * Read data from flash.
+ * @note This operation's units is word.
+ *
+ * @param addr flash address
+ * @param buf buffer to store read data
+ * @param size read bytes size
+ *
+ * @return result
+ */
+int at32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
+{
+    size_t i;
+
+    if ((addr + size) > AT32_FLASH_END_ADDRESS)
+    {
+        LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    for (i = 0; i < size; i++, buf++, addr++)
+    {
+        *buf = *(rt_uint8_t *) addr;
+    }
+
+    return size;
+}
+
+/**
+ * Write data to flash.
+ * @note This operation's units is word.
+ * @note This operation must after erase. @see flash_erase.
+ *
+ * @param addr flash address
+ * @param buf the write data buffer
+ * @param size write bytes size
+ *
+ * @return result
+ */
+int at32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
+{
+    rt_err_t result        = RT_EOK;
+    rt_uint32_t end_addr   = addr + size;
+
+    if (addr % 4 != 0)
+    {
+        LOG_E("write addr must be 4-byte alignment");
+        return -RT_EINVAL;
+    }
+
+    if ((end_addr) > AT32_FLASH_END_ADDRESS)
+    {
+        LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    FLASH_Unlock();
+
+    while (addr < end_addr)
+    {
+        if (FLASH_ProgramWord(addr, *((rt_uint32_t *)buf)) == FLASH_PRC_DONE)
+        {
+            if (*(rt_uint32_t *)addr != *(rt_uint32_t *)buf)
+            {
+                result = -RT_ERROR;
+                break;
+            }
+            addr += 4;
+            buf  += 4;
+        }
+        else
+        {
+            result = -RT_ERROR;
+            break;
+        }
+    }
+
+    FLASH_Lock();
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    return size;
+}
+
+/**
+ * Erase data on flash .
+ * @note This operation is irreversible.
+ * @note This operation's units is different which on many chips.
+ *
+ * @param addr flash address
+ * @param size erase bytes size
+ *
+ * @return result
+ */
+int at32_flash_erase(rt_uint32_t addr, size_t size)
+{
+    rt_err_t result = RT_EOK;
+    rt_uint32_t end_addr = addr + size;
+    rt_uint32_t page_addr = 0;
+
+    FLASH_Unlock();
+
+    if ((end_addr) > AT32_FLASH_END_ADDRESS)
+    {
+        LOG_E("erase outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    while(addr < end_addr)
+    {
+        page_addr = get_page(addr);
+
+        if(FLASH_ErasePage(page_addr) != FLASH_PRC_DONE)
+        {
+            result = -RT_ERROR;
+            goto __exit;
+        }
+
+        addr += FLASH_PAGE_SIZE;
+    }
+
+		FLASH_Lock();
+		
+__exit:    
+    if(result != RT_EOK)
+    {
+        return result;
+    }
+    
+    return size;
+}
+
+#if defined(PKG_USING_FAL)
+
+static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
+static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
+static int fal_flash_erase(long offset, size_t size);
+
+const struct fal_flash_dev at32_onchip_flash = 
+{
+    "onchip_flash",
+    AT32_FLASH_START_ADRESS,
+    AT32_FLASH_SIZE,
+    FLASH_PAGE_SIZE,
+    {
+        NULL,
+        fal_flash_read,
+        fal_flash_write,
+        fal_flash_erase
+    }
+};
+
+static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
+{
+    return at32_flash_read(at32_onchip_flash.addr + offset, buf, size);
+}
+
+static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size)
+{
+    return at32_flash_write(at32_onchip_flash.addr + offset, buf, size);
+}
+
+static int fal_flash_erase(long offset, size_t size)
+{
+    return at32_flash_erase(at32_onchip_flash.addr + offset, size);
+}
+
+#endif
+#endif /* BSP_USING_ON_CHIP_FLASH */

bsp/at32/Libraries/rt_drivers/drv_flash.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-02-09     shelton      the first version
+ */
+
+#ifndef __DRV_FLASH_H__
+#define __DRV_FLASH_H__
+
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int at32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size);
+int at32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size);
+int at32_flash_erase(rt_uint32_t addr, size_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __DRV_FLASH_H__ */

bsp/at32/at32f403a-start/README.md

@@ -46,8 +46,10 @@ AT32F403A-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
 | PWM       | 支持     | TMR1/2                     |
 | HWTIMER   | 支持     | TMR3/4/5                   |
 | SDIO      | 支持     | SDIO1                      |
+| CAN       | 支持     | CAN1/2                     |
 | WDT       | 支持     |                            |
 | RTC       | 支持     |                            |
+| FLASH     | 支持     |                            |
 
 ### IO在板级支持包中的映射情况
 
@@ -88,6 +90,10 @@ AT32F403A-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
 | PC3  | ADC1/2_IN13    |
 | PC4  | ADC1/2_IN14    |
 | PC5  | ADC1/2_IN15    |
+| PA11 | CAN1_RX        |
+| PA12 | CAN1_TX        |
+| PB5  | CAN2_RX        |
+| PB6  | CAN2_TX        |
 
 ## 使用说明
 

bsp/at32/at32f403a-start/board/Kconfig

@@ -24,6 +24,10 @@ menu "On-chip Peripheral Drivers"
         select RT_USING_PIN
         default y
 
+    config BSP_USING_ON_CHIP_FLASH
+        bool "Enable on-chip FLASH"
+        default n 
+
     menuconfig BSP_USING_RTC
         bool "Enable RTC"
         select RT_USING_RTC
@@ -151,6 +155,19 @@ menu "On-chip Peripheral Drivers"
                 default n
         endif
 
+    menuconfig BSP_USING_CAN
+        bool "Enable CAN"
+        default n
+        select RT_USING_CAN
+        if BSP_USING_CAN
+            config BSP_USING_CAN1
+                bool "using CAN1"
+                default n
+            config BSP_USING_CAN2
+                bool "using CAN2"
+                default n
+        endif
+
     menuconfig BSP_USING_SDIO
         bool "Enable SDIO"
         default n

bsp/at32/at32f403a-start/board/board.h

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2020-01-15     shelton      first version
+ * 2021-02-09     shelton      add flash macros
  */
 
 #ifndef __BOARD_H__
@@ -18,6 +19,12 @@
 extern "C" {
 #endif
 
+/* Just only support for AT32F40xxG */
+#define AT32_FLASH_START_ADRESS     ((uint32_t)0x08000000)
+#define FLASH_PAGE_SIZE             (2 * 1024)
+#define AT32_FLASH_SIZE             (1024 * 1024)
+#define AT32_FLASH_END_ADDRESS      ((uint32_t)(AT32_FLASH_START_ADRESS + AT32_FLASH_SIZE))
+
 /* Internal SRAM memory size[Kbytes] <96>, Default: 96*/
 #define AT32_SRAM_SIZE      96
 #define AT32_SRAM_END       (0x20000000 + AT32_SRAM_SIZE * 1024)

bsp/at32/at32f403a-start/board/msp/at32_msp.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    at32_msp.c
   * @author  Artery Technology
-  * @version V1.0.0
-  * @date    2020-01-10
+  * @version V1.0.1
+  * @date    2021-02-09
   * @brief   Msp source file
   ******************************************************************************
   * @attention
@@ -256,3 +256,44 @@ void at32_msp_hwtmr_init(void *Instance)
 #endif
 }
 #endif
+
+#ifdef BSP_USING_CAN
+void at32_msp_can_init(void *Instance)
+{
+    GPIO_InitType GPIO_InitStruct;
+    CAN_Type *CANx = (CAN_Type *)Instance;
+
+    GPIO_StructInit(&GPIO_InitStruct);
+    GPIO_InitStruct.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
+#ifdef BSP_USING_CAN1
+    if(CAN1 == CANx)
+    {
+        RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_CAN1, ENABLE);
+        RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_GPIOA, ENABLE);
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+        GPIO_InitStruct.GPIO_Pins = GPIO_Pins_12;
+        GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+        GPIO_InitStruct.GPIO_Pins = GPIO_Pins_11;
+        GPIO_Init(GPIOA, &GPIO_InitStruct);
+    }
+#endif
+#ifdef BSP_USING_CAN2
+    if(CAN2 == CANx)
+    {
+        RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_CAN2, ENABLE);
+        RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_AFIO, ENABLE);
+        RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_GPIOB, ENABLE);
+        GPIO_PinsRemapConfig(AFIO_MAP6_CAN2_0001, ENABLE);
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+        GPIO_InitStruct.GPIO_Pins = GPIO_Pins_6;
+        GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+        GPIO_InitStruct.GPIO_Pins = GPIO_Pins_5;
+        GPIO_Init(GPIOB, &GPIO_InitStruct);
+    }
+#endif
+}
+#endif /* BSP_USING_CAN */

bsp/at32/at32f403a-start/board/msp/at32_msp.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    at32_msp.h
   * @author  Artery Technology
-  * @version V1.0.0
-  * @date    2020-01-10
+  * @version V1.0.1
+  * @date    2021-02-09
   * @brief   Msp header file
   ******************************************************************************
   * @attention
@@ -29,5 +29,6 @@ void at32_msp_i2c_init(void *Instance);
 void at32_msp_sdio_init(void *Instance);
 void at32_msp_adc_init(void *Instance);
 void at32_msp_hwtmr_init(void *Instance);
+void at32_msp_can_init(void *Instance);
 
 #endif /* __AT32_MSP_H__ */

bsp/at32/at32f407-start/README.md

@@ -46,8 +46,10 @@ AT32F407-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
 | PWM       | 支持     | TMR1/2                     |
 | HWTIMER   | 支持     | TMR3/4/5                   |
 | SDIO      | 支持     | SDIO1                      |
+| CAN       | 支持     | CAN1/2                     |
 | WDT       | 支持     |                            |
 | RTC       | 支持     |                            |
+| FLASH     | 支持     |                            |
 | ETH       | 支持     |                            |
 
 ### IO在板级支持包中的映射情况
@@ -89,6 +91,10 @@ AT32F407-START板级包支持MDK4﹑MDK5﹑IAR开发环境和GCC编译器，以
 | PC3  | ADC1/2_IN13    |
 | PC4  | ADC1/2_IN14    |
 | PC5  | ADC1/2_IN15    |
+| PA11 | CAN1_RX        |
+| PA12 | CAN1_TX        |
+| PB5  | CAN2_RX        |
+| PB6  | CAN2_TX        |
 | PB11 | ETH_RMII_TX_EN |
 | PB12 | ETH_RMII_TX0   |
 | PB13 | ETH_RMII_TX1   |

bsp/at32/at32f407-start/board/Kconfig

@@ -24,6 +24,10 @@ menu "On-chip Peripheral Drivers"
         select RT_USING_PIN
         default y
 
+    config BSP_USING_ON_CHIP_FLASH
+        bool "Enable on-chip FLASH"
+        default n 
+
     config BSP_USING_ETH
         bool "Enable Ethernet"
         default n
@@ -157,6 +161,19 @@ menu "On-chip Peripheral Drivers"
                 default n
         endif
 
+    menuconfig BSP_USING_CAN
+        bool "Enable CAN"
+        default n
+        select RT_USING_CAN
+        if BSP_USING_CAN
+            config BSP_USING_CAN1
+                bool "using CAN1"
+                default n
+            config BSP_USING_CAN2
+                bool "using CAN2"
+                default n
+        endif
+
     menuconfig BSP_USING_SDIO
         bool "Enable SDIO"
         default n

bsp/at32/at32f407-start/board/board.h

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2020-01-15     shelton      first version
+ * 2021-02-09     shelton      add flash macros
  */
 
 #ifndef __BOARD_H__
@@ -18,6 +19,12 @@
 extern "C" {
 #endif
 
+/* Just only support for AT32F40xxG */
+#define AT32_FLASH_START_ADRESS     ((uint32_t)0x08000000)
+#define FLASH_PAGE_SIZE             (2 * 1024)
+#define AT32_FLASH_SIZE             (1024 * 1024)
+#define AT32_FLASH_END_ADDRESS      ((uint32_t)(AT32_FLASH_START_ADRESS + AT32_FLASH_SIZE))
+
 /* Internal SRAM memory size[Kbytes] <96>, Default: 96*/
 #define AT32_SRAM_SIZE      96
 #define AT32_SRAM_END       (0x20000000 + AT32_SRAM_SIZE * 1024)

bsp/at32/at32f407-start/board/msp/at32_msp.c

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    at32_msp.c
   * @author  Artery Technology
-  * @version V1.0.0
-  * @date    2020-01-10
+  * @version V1.0.1
+  * @date    2021-02-09
   * @brief   Msp source file
   ******************************************************************************
   * @attention
@@ -256,3 +256,44 @@ void at32_msp_hwtmr_init(void *Instance)
 #endif
 }
 #endif
+
+#ifdef BSP_USING_CAN
+void at32_msp_can_init(void *Instance)
+{
+    GPIO_InitType GPIO_InitStruct;
+    CAN_Type *CANx = (CAN_Type *)Instance;
+
+    GPIO_StructInit(&GPIO_InitStruct);
+    GPIO_InitStruct.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
+#ifdef BSP_USING_CAN1
+    if(CAN1 == CANx)
+    {
+        RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_CAN1, ENABLE);
+        RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_GPIOA, ENABLE);
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+        GPIO_InitStruct.GPIO_Pins = GPIO_Pins_12;
+        GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+        GPIO_InitStruct.GPIO_Pins = GPIO_Pins_11;
+        GPIO_Init(GPIOA, &GPIO_InitStruct);
+    }
+#endif
+#ifdef BSP_USING_CAN2
+    if(CAN2 == CANx)
+    {
+        RCC_APB1PeriphClockCmd(RCC_APB1PERIPH_CAN2, ENABLE);
+        RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_AFIO, ENABLE);
+        RCC_APB2PeriphClockCmd(RCC_APB2PERIPH_GPIOB, ENABLE);
+        GPIO_PinsRemapConfig(AFIO_MAP6_CAN2_0001, ENABLE);
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+        GPIO_InitStruct.GPIO_Pins = GPIO_Pins_6;
+        GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+        GPIO_InitStruct.GPIO_Pins = GPIO_Pins_5;
+        GPIO_Init(GPIOB, &GPIO_InitStruct);
+    }
+#endif
+}
+#endif /* BSP_USING_CAN */

bsp/at32/at32f407-start/board/msp/at32_msp.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    at32_msp.h
   * @author  Artery Technology
-  * @version V1.0.0
-  * @date    2020-01-10
+  * @version V1.0.1
+  * @date    2021-02-09
   * @brief   Msp header file
   ******************************************************************************
   * @attention
@@ -29,5 +29,6 @@ void at32_msp_i2c_init(void *Instance);
 void at32_msp_sdio_init(void *Instance);
 void at32_msp_adc_init(void *Instance);
 void at32_msp_hwtmr_init(void *Instance);
+void at32_msp_can_init(void *Instance);
 
 #endif /* __AT32_MSP_H__ */