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rt-thread

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提交 aebdcacc 编写于 作者: L LYH-ux
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first commit of tm4c123bsp, validate on MDK5

上级 3408c57d
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bsp/tm4c123bsp/.config 0 → 100644
浏览文件 @ aebdcacc
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_MEMHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x40003
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
# CONFIG_FINSH_USING_MSH_ONLY is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN=y
CONFIG_RT_USING_ADC=y
CONFIG_RT_USING_PWM=y
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_QSPI is not set
# CONFIG_RT_USING_SPI_MSD is not set
# CONFIG_RT_USING_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_URLENCODE is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_BSP_USING_SPI1 is not set
# CONFIG_BSP_USING_SPI2 is not set
# CONFIG_BSP_USING_SPI3 is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
#
# Hardware Drivers Config
#
CONFIG_tm4c123=y
#
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_USB_TO_USART=y
# CONFIG_BSP_USING_RS485_OR_RS232 is not set
# CONFIG_BSP_USING_SPI_FLASH is not set
# CONFIG_BSP_USING_RGB is not set
# CONFIG_BSP_USING_POT is not set
# CONFIG_BSP_USING_EEPROM is not set
# CONFIG_BSP_USING_ETH is not set
# CONFIG_BSP_USING_SDCARD is not set
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART0=y
CONFIG_BSP_USING_UART1=y
# CONFIG_BSP_UART1_RX_USING_DMA is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
CONFIG_BSP_USING_SPI=y
CONFIG_BSP_USING_SPI0=y
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_TIM is not set
CONFIG_BSP_USING_PWM=y
# CONFIG_BSP_USING_PWM0 is not set
# CONFIG_BSP_USING_PWM1 is not set
# CONFIG_BSP_USING_PWM2 is not set
# CONFIG_BSP_USING_PWM3 is not set
# CONFIG_BSP_USING_PWM4 is not set
# CONFIG_BSP_USING_PWM5 is not set
# CONFIG_BSP_USING_PWM6 is not set
CONFIG_BSP_USING_PWM7=y
CONFIG_BSP_USING_ADC=y
CONFIG_BSP_USING_ADC0=y
# CONFIG_BSP_USING_ADC1 is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_SDIO is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_USBD is not set
# CONFIG_BSP_USING_CRC is not set
#
# Board extended module Drivers
#
bsp/tm4c123bsp/Kconfig 0 → 100644
浏览文件 @ aebdcacc
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "board/Kconfig"
bsp/tm4c123bsp/README.md 0 → 100644
浏览文件 @ aebdcacc
# BSP README 模板
## 简介
本文档为ek-tm4c123gxl开发板的 BSP (板级支持包) 说明。
主要内容如下：
- 开发板资源介绍
- BSP 快速上手
- 进阶使用方法
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
## 开发板介绍
【此处简单介绍一下开发板】
开发板外观如下图所示：
![](E:\00MyWorkSpace\tm4c123_rtos\tm4c123bsp\figures\board.jpg)
该开发板常用 **板载资源** 如下：
- MCU：TM4C123Gh6PM，主频 80MHz，256KB FLASH ，32KB RAM
- 外部 RAM：型号，xMB
- 外部 FLASH：型号，xMB
- 常用外设
- LED：1个三色，（红色，PF1），（蓝色，PF2）,（绿色，PF3）
- 按键：2个，SW1（PF4），SW2（兼具唤醒功能，PF0）
- 常用接口：ICDI（具串口功能）、USB接口
- 调试接口，ICDI
开发板更多详细信息请参考【TI】 [TM4C123G开发板介绍](https://www.ti.com/tool/EK-TM4C123GXL?DCMP=stellaris-launchpad&HQS=tm4c123g-launchpad)。
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **板载外设** | **支持情况** | **备注** |
| :----------------- | :----------: | :------------------------------------- |
| USB 转串口 | 支持 | |
| SPI Flash | 暂不支持 | |
| 以太网 | 暂不支持 | |
| SD卡 | 暂不支持 | |
| CAN | 暂不支持 | |
| **片上外设** | **支持情况** | **备注** |
| GPIO | 支持 | PF0, PF1... PF4---> PIN: 0, 1...4 |
| UART | 支持 | UART0/1/2/3 |
| SPI | 支持 | SPI0/1/2 |
| I2C | 支持 | 软件 I2C |
| SDIO | 暂不支持 | 即将支持 |
| RTC | 暂不支持 | 即将支持 |
| PWM | 支持 | PWM0/1/2/3/4/5/6/7 |
| USB Device | 暂不支持 | 即将支持 |
| USB Host | 暂不支持 | 即将支持 |
| IWG | 暂不支持 | 即将支持 |
| **扩展模块** | **支持情况** | **备注** |
| xxx 模块 | 支持 | |
## 使用说明
使用说明分为如下两个章节：
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
### 快速上手
本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
#### 硬件连接
使用数据线连接开发板到 PC，打开电源开关。
#### 编译下载
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
> 工程默认配置使用 ICDI 仿真器下载程序，在通过USB连接开发板的基础上，点击下载按钮即可下载程序到开发板
#### 运行结果
下载程序成功之后，系统会自动运行，【这里写开发板运行起来之后的现象，如：LED 闪烁等】。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
```bash
\ | /
- RT - Thread Operating System
/ | \ 3.1.1 build Nov 19 2018
2006 - 2018 Copyright by rt-thread team
msh >
```
### 进阶使用
此 BSP 默认只开启了 GPIO 和 串口0 的功能，如果需使用 SD 卡、Flash 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
本章节更多详细的介绍请结合 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)学习使用。
## 注意事项
- 本BSP配置片上外设在board/tm4c123gh6pz_config.c/h中进行配置。配置时钟在board.c文件中进行
## 联系人信息
维护人:
- [AHTYDHD](https://github.com/LYH-ux), 邮箱：<1780328728@qq.com>
\ No newline at end of file
bsp/tm4c123bsp/SConscript 0 → 100644
浏览文件 @ aebdcacc
# for module compiling
import os
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
bsp/tm4c123bsp/SConstruct 0 → 100644
浏览文件 @ aebdcacc
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
# set RTT_ROOT
#if not os.getenv("RTT_ROOT"):
#RTT_ROOT="rt-thread"
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
tm4c123_library = 'TivaWare_C_series'
rtconfig.BSP_LIBRARY_TYPE = tm4c123_library
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, tm4c123_library, 'SConscript')))
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'Drivers', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)
bsp/tm4c123bsp/applications/SConscript 0 → 100644
浏览文件 @ aebdcacc
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/tm4c123bsp/applications/main.c 0 → 100644
浏览文件 @ aebdcacc
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-06 SummerGift first version
*/
#include <rtthread.h>
#include <rtdevice.h>
int main(void)
{
int count = 1;
/* set LED0 pin mode to output */
rt_pin_mode(2, PIN_MODE_OUTPUT);
while (count++)
{
rt_pin_write(2, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(2, PIN_LOW);
rt_thread_mdelay(500);
}
return RT_EOK;
}
bsp/tm4c123bsp/board/Kconfig 0 → 100644
浏览文件 @ aebdcacc
menu "Hardware Drivers Config"
config tm4c123
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_USB_TO_USART
bool "Enable USB TO USART (uart1)"
select BSP_USING_UART
select BSP_USING_UART1
default y
config BSP_USING_RS485_OR_RS232
bool "Enable RS485/RS232 (uart2 be shared)"
select BSP_USING_UART2
default n
config BSP_USING_SPI_FLASH
bool "Enable SPI FLASH (W25Q64 spi1)"
select BSP_USING_SPI
select BSP_USING_SPI1
select RT_USING_SFUD
select RT_SFUD_USING_SFDP
default n
config BSP_USING_RGB
bool "Enable RGB LED (timer3 channel2 - 4)"
select RT_USING_PWM
select BSP_USING_PWM
select BSP_USING_PWM3
select BSP_USING_PWM3_CH2
select BSP_USING_PWM3_CH3
select BSP_USING_PWM3_CH4
default n
config BSP_USING_POT
bool "Enable potentiometer"
select BSP_USING_ADC
select BSP_USING_ADC1
default n
config BSP_USING_EEPROM
bool "Enable I2C EEPROM (i2c1)"
select BSP_USING_I2C1
default n
config BSP_USING_ETH
bool "Enable Ethernet Driver (spi2)"
default n
select PKG_USING_WIZNET
select WIZNET_DEVICE_EXTERN_CONFIG
select BSP_USING_SPI2
if BSP_USING_ETH
if WIZNET_DEVICE_EXTERN_CONFIG
config WIZ_SPI_DEVICE
string
default "spi20"
config WIZ_RST_PIN
int
default 111
config WIZ_IRQ_PIN
int
default 104
endif
config EXTERNAL_PHY_ADDRESS
hex
default 0x00
endif
config BSP_USING_SDCARD
bool "Enable SDCARD (sdio)"
select BSP_USING_SDIO
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
default n
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART0
bool "Enable UART0"
default y
config BSP_USING_UART1
bool "Enable UART1"
default n
config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART2
bool "Enable UART2"
default n
config BSP_UART2_RX_USING_DMA
bool "Enable UART2 RX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_USING_UART3
bool "Enable UART3"
default n
config BSP_UART3_RX_USING_DMA
bool "Enable UART3 RX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
endif
config BSP_USING_ON_CHIP_FLASH
bool "Enable on-chip FLASH"
default n
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_SPI0
bool "Enable SPI0 BUS"
default n
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_SPI1_TX_USING_DMA
bool "Enable SPI1 TX DMA"
depends on BSP_USING_SPI1
default n
config BSP_SPI1_RX_USING_DMA
bool "Enable SPI1 RX DMA"
depends on BSP_USING_SPI1
select BSP_SPI1_TX_USING_DMA
default n
config BSP_USING_SPI2
bool "Enable SPI2 BUS"
default n
config BSP_SPI2_TX_USING_DMA
bool "Enable SPI2 TX DMA"
depends on BSP_USING_SPI2
default n
config BSP_SPI2_RX_USING_DMA
bool "Enable SPI2 RX DMA"
depends on BSP_USING_SPI2
select BSP_SPI2_TX_USING_DMA
default n
config BSP_USING_SPI3
bool "Enable SPI3 BUS"
default n
config BSP_SPI3_TX_USING_DMA
bool "Enable SPI3 TX DMA"
depends on BSP_USING_SPI3
default n
config BSP_SPI3_RX_USING_DMA
bool "Enable SPI3 RX DMA"
depends on BSP_USING_SPI3
select BSP_SPI3_TX_USING_DMA
default n
endif
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"
default n
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C1
config BSP_I2C1_SCL_PIN
int "i2c1 scl pin number"
range 0 175
default 22
config BSP_I2C1_SDA_PIN
int "I2C1 sda pin number"
range 0 175
default 23
endif
menuconfig BSP_USING_TIM
bool "Enable timer"
default n
select RT_USING_HWTIMER
if BSP_USING_TIM
config BSP_USING_TIM2
bool "Enable TIM2"
default n
config BSP_USING_TIM3
bool "Enable TIM3"
default n
config BSP_USING_TIM4
bool "Enable TIM4"
default n
config BSP_USING_TIM5
bool "Enable TIM5"
default n
endif
menuconfig BSP_USING_PWM
bool "Enable pwm"
default n
select RT_USING_PWM
if BSP_USING_PWM
menuconfig BSP_USING_PWM0
bool "Enable pwm0"
default n
if BSP_USING_PWM0
config BSP_USING_PWM0_CH1
bool "Enable PWM0 channel1"
default y
config BSP_USING_PWM0_CH2
bool "Enable PWM0 channel2"
default n
endif
config BSP_USING_PWM1
bool "Enable pwm1"
default n
config BSP_USING_PWM2
bool "Enable pwm2"
default n
config BSP_USING_PWM3
bool "Enable pwm3"
default n
config BSP_USING_PWM4
bool "Enable pwm4"
default n
config BSP_USING_PWM5
bool "Enable pwm5"
default n
config BSP_USING_PWM6
bool "Enable pwm6"
default n
config BSP_USING_PWM7
bool "Enable pwm7"
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC0
bool "Enable ADC0"
default n
config BSP_USING_ADC1
bool "Enable ADC1"
default n
endif
menuconfig BSP_USING_ONCHIP_RTC
bool "Enable RTC"
select RT_USING_RTC
select RT_USING_LIBC
default n
if BSP_USING_ONCHIP_RTC
choice
prompt "Select clock source"
default BSP_RTC_USING_LSE
config BSP_RTC_USING_LSE
bool "RTC USING LSE"
config BSP_RTC_USING_LSI
bool "RTC USING LSI"
endchoice
endif
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_SDIO
bool "Enable SDIO"
select RT_USING_SDIO
select RT_USING_DFS
default n
menuconfig BSP_USING_CAN
bool "Enable CAN"
default n
select RT_USING_CAN
if BSP_USING_CAN
config BSP_USING_CAN1
bool "using CAN1"
default n
endif
config BSP_USING_USBD
bool "Enable USB device"
select RT_USING_USB_DEVICE
default n
if BSP_USING_USBD
config BSP_USB_CONNECT_PIN
int "USB connect pin"
default 67
config BSP_USB_PULL_UP_STATUS
int "USB PULL UP STATUS"
default 0
endif
config BSP_USING_CRC
bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)"
select RT_USING_HWCRYPTO
select RT_HWCRYPTO_USING_CRC
# "Crypto device frame dose not support above 8-bits granularity"
# "Reserve progress, running well, about 32-bits granularity, such as stm32f1, stm32f4"
default n
endmenu
menu "Board extended module Drivers"
endmenu
endmenu
bsp/tm4c123bsp/board/SConscript 0 → 100644
浏览文件 @ aebdcacc
import os
import rtconfig
from building import *
Import('SDK_LIB')
cwd = GetCurrentDir()
# add general drivers
src = Split('''
board.c
tm4c123_config.c
''')
path = [cwd]
#path += [cwd + '/CubeMX_Config/Inc']
startup_path_prefix = SDK_LIB
if rtconfig.CROSS_TOOL == 'gcc':
src += [startup_path_prefix + '/TivaWare_C_series/tm4c123_driverlib/startup/gcc/startup_gcc.c']
elif rtconfig.CROSS_TOOL == 'keil':
src += [startup_path_prefix + '/TivaWare_C_series/tm4c123_driverlib/startup/arm/startup_rvmdk.S']
elif rtconfig.CROSS_TOOL == 'iar':
src += [startup_path_prefix + '/TivaWare_C_series/tm4c123_driverlib/startup/iar/startup_rvmdk.S']
CPPDEFINES = ['PART_TM4C123GH6PM']
CPPDEFINES += ['TARGET_IS_TM4C123_RB1']
CPPDEFINES += ['rvmdk']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')
bsp/tm4c123bsp/board/board.c 0 → 100644
浏览文件 @ aebdcacc
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2017-07-24 Tanek the first version
* 2018-11-12 Ernest Chen modify copyright
*/
#include <stdint.h>
#include <stdbool.h>
#include "hw_ints.h"
#include "hw_sysctl.h"
#include "hw_memmap.h"
#include "hw_types.h"
#include "fpu.h"
#include "debug.h"
#include "pin_map.h"
#include "rom.h"
#include "sysctl.h"
#include "systick.h"
#include "hw_ints.h"
#include "board.h"
// Holds the system core clock, which is the system clock
// frequency supplied to the SysTick timer and the processor
// core clock.
uint32_t SystemCoreClock;
void SystemCoreClockUpdate(void)
{
FPULazyStackingEnable();
//
// Set the clocking to run directly from the crystal.
//
SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ |
SYSCTL_OSC_MAIN);
SystemCoreClock = SysCtlClockGet();
}
void SysTickConfig()
{
SysTickDisable();
SysTickPeriodSet(SystemCoreClock/RT_TICK_PER_SECOND);
SysTickIntEnable();
SysTickEnable();
}
/**
* This function will initial your board.
*/
void rt_hw_board_init()
{
/* System Clock Update */
SystemCoreClockUpdate();
/* System Tick Configuration */
SysTickConfig();
#ifdef RT_USING_SERIAL
rt_hw_usart_init();
#endif
#ifdef RT_USING_PIN
rt_hw_pin_init();
#endif
#ifdef RT_USING_PWM
rt_hw_pwm_init();
#endif
/* Call components board initial (use INIT_BOARD_EXPORT()) */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
}
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
bsp/tm4c123bsp/board/board.h 0 → 100644
浏览文件 @ aebdcacc
#ifndef _BOARD_H_
#define _BOARD_H_
#include <rthw.h>
#include <rtthread.h>
#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
#define TM4C123_SRAM1_START (0x20000000)
#define TM4C123_SRAM1_END (TM4C123_SRAM1_START + 32 * 1024) // end address = 0x20000000(base adddress) + 32K(RAM size)
#if defined(__CC_ARM) || defined(__CLANG_ARM)
extern int Image$$RW_IRAM$$ZI$$Limit; // RW_IRAM
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM$$ZI$$Limit)
#endif
#define HEAP_END TM4C123_SRAM1_END
#endif
#ifdef RT_USING_PIN
#include "drv_gpio.h"
#endif /* RT_USING_PIN */
#ifdef RT_USING_SERIAL
#include "drv_uart.h"
#endif /* RT_USING_SERIAL */
#ifdef RT_USING_PWM
#include "drv_pwm.h"
#endif /* RT_USING_PWM*/
#ifdef RT_USING_SPI
#include "drv_spi.h"
#endif /* RT_USING_SPI*/
#endif /*_BOARD_H_*/
bsp/tm4c123bsp/board/linker_scripts/link.icf 0 → 100644
浏览文件 @ aebdcacc
//*****************************************************************************
//
// hello.icf - Linker configuration file for hello.
//
// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2.1.4.178 of the EK-TM4C123GXL Firmware Package.
//
//*****************************************************************************
//
// Define a memory region that covers the entire 4 GB addressible space of the
// processor.
//
define memory mem with size = 4G;
//
// Define a region for the on-chip flash.
//
define region FLASH = mem:[from 0x00000000 to 0x0003ffff];
//
// Define a region for the on-chip SRAM.
//
define region SRAM = mem:[from 0x20000000 to 0x20007fff];
//
// Define a block for the heap. The size should be set to something other
// than zero if things in the C library that require the heap are used.
//
define block HEAP with alignment = 8, size = 0x00000000 { };
//
// Indicate that the read/write values should be initialized by copying from
// flash.
//
initialize by copy { readwrite };
//
// Indicate that the noinit values should be left alone. This includes the
// stack, which if initialized will destroy the return address from the
// initialization code, causing the processor to branch to zero and fault.
//
do not initialize { section .noinit };
//
// Place the interrupt vectors at the start of flash.
//
place at start of FLASH { readonly section .intvec };
//
// Place the remainder of the read-only items into flash.
//
place in FLASH { readonly };
//
// Place the RAM vector table at the start of SRAM.
//
place at start of SRAM { section VTABLE };
//
// Place all read/write items into SRAM.
//
place in SRAM { readwrite, block HEAP };
bsp/tm4c123bsp/board/linker_scripts/link.ld 0 → 100644
浏览文件 @ aebdcacc
/******************************************************************************
*
* hello.ld - Linker configuration file for hello.
*
* Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
* Software License Agreement
*
* Texas Instruments (TI) is supplying this software for use solely and
* exclusively on TI's microcontroller products. The software is owned by
* TI and/or its suppliers, and is protected under applicable copyright
* laws. You may not combine this software with "viral" open-source
* software in order to form a larger program.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
* NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
* NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
* CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
* DAMAGES, FOR ANY REASON WHATSOEVER.
*
* This is part of revision 2.1.4.178 of the EK-TM4C123GXL Firmware Package.
*
*****************************************************************************/
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
}
SECTIONS
{
.text :
{
_text = .;
KEEP(*(.isr_vector))
*(.text*)
*(.rodata*)
_etext = .;
} > FLASH
.data : AT(ADDR(.text) + SIZEOF(.text))
{
_data = .;
_ldata = LOADADDR (.data);
*(vtable)
*(.data*)
_edata = .;
} > SRAM
.bss :
{
_bss = .;
*(.bss*)
*(COMMON)
_ebss = .;
} > SRAM
}
bsp/tm4c123bsp/board/linker_scripts/link.sct 0 → 100644
浏览文件 @ aebdcacc
;******************************************************************************
;
; hello.sct - Linker configuration file for hello.
;
; Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
; Software License Agreement
;
; Texas Instruments (TI) is supplying this software for use solely and
; exclusively on TI's microcontroller products. The software is owned by
; TI and/or its suppliers, and is protected under applicable copyright
; laws. You may not combine this software with "viral" open-source
; software in order to form a larger program.
;
; THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
; NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
; NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
; A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
; CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
; DAMAGES, FOR ANY REASON WHATSOEVER.
;
; This is part of revision 2.1.4.178 of the EK-TM4C123GXL Firmware Package.
;
;******************************************************************************
LR_IROM 0x00000000 0x00040000
{
;
; Specify the Execution Address of the code and the size.
;
ER_IROM 0x00000000 0x00040000
{
*.o (RESET, +First)
* (InRoot$$Sections, +RO)
}
;
; Specify the Execution Address of the data area.
;
RW_IRAM 0x20000000 0x00008000
{
;
; Uncomment the following line in order to use IntRegister().
;
;* (vtable, +First)
* (+RW, +ZI)
}
}
bsp/tm4c123bsp/board/tm4c123_config.c 0 → 100644
浏览文件 @ aebdcacc
#include "stdbool.h"
#include "stdint.h"
#include "hw_memmap.h"
#include "pin_map.h"
#include "sysctl.h"
#include "pwm.h"
#include "gpio.h"
#include "uart.h"
#include "adc.h"
#include "ssi.h"
#include "tm4c123_config.h"
void uart_hw_config(void)
{
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
GPIOPinConfigure(GPIO_PA0_U0RX);
GPIOPinConfigure(GPIO_PA1_U0TX);
GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
GPIOPinConfigure(GPIO_PC4_U1RX);
GPIOPinConfigure(GPIO_PC5_U1TX);
GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_4 | GPIO_PIN_5);
}
void pwm_hw_config(void)
{
SysCtlPWMClockSet(SYSCTL_PWMDIV_2);
//GPIO port D needs to be enabled so these pins can be used.
SysCtlPeripheralEnable(SYSCTL_PERIPH_PWM1);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
// Configure the GPIO pin muxing to select PWM functions for these pins.
GPIOPinConfigure(GPIO_PF2_M1PWM6);
GPIOPinConfigure(GPIO_PF3_M1PWM7);
// Configure the GPIO pad for PWM function on pins PF2 and PF3
GPIOPinTypePWM(GPIO_PORTF_BASE, GPIO_PIN_2|GPIO_PIN_3);
}
void adc_hw_config(void)
{
// The ADC0 peripheral must be enabled for use.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
// GPIO port D needs to be enabled
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
// Select the analog ADC function for these pins.
GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3);
}
void spi_hw_config(void)
{
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
GPIOPinConfigure(GPIO_PA2_SSI0CLK);
//GPIOPinConfigure(GPIO_PA3_SSI0FSS);
GPIOPinConfigure(GPIO_PA4_SSI0RX);
GPIOPinConfigure(GPIO_PA5_SSI0TX);
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_2);
}
bsp/tm4c123bsp/board/tm4c123_config.h 0 → 100644
浏览文件 @ aebdcacc
#ifndef _TM4C123GH6PZ_CONFIG_H_
#define _TM4C123GH6PZ_CONFIG_H_
#ifdef __cplusplus
extern "C" {
#endif
void uart_hw_config(void);
void pwm_hw_config(void);
void adc_hw_config(void);
void spi_hw_config(void);
#ifdef __cplusplus
}
#endif
#endif /*_TM4C123GH6PZ_CONFIG_H_*/
bsp/tm4c123bsp/libraries/Drivers/SConscript 0 → 100644
浏览文件 @ aebdcacc
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
# add the general drivers.
src = Split("""
""")
if GetDepend(['RT_USING_PIN']):
src += ['drv_gpio.c']
if GetDepend(['RT_USING_SERIAL']):
src += ['drv_uart.c']
if GetDepend(['RT_USING_HWTIMER']):
src += ['drv_hwtimer.c']
if GetDepend(['RT_USING_PWM']):
src += ['drv_pwm.c']
if GetDepend(['RT_USING_SPI']):
src += ['drv_spi.c']
if GetDepend(['RT_USING_QSPI']):
src += ['drv_qspi.c']
if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'):
src += ['drv_soft_i2c.c']
if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']):
src += ['drv_eth.c']
if GetDepend(['RT_USING_ADC']):
src += Glob('drv_adc.c')
if GetDepend(['RT_USING_CAN']):
src += ['drv_can.c']
if GetDepend(['RT_USING_PM', 'SOC_SERIES_STM32L4']):
src += ['drv_pm.c']
src += ['drv_lptim.c']
if GetDepend('BSP_USING_SDRAM'):
src += ['drv_sdram.c']
if GetDepend('BSP_USING_LCD'):
src += ['drv_lcd.c']
if GetDepend('BSP_USING_LCD_MIPI'):
src += ['drv_lcd_mipi.c']
if GetDepend('BSP_USING_ONCHIP_RTC'):
src += ['drv_rtc.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F0']):
src += ['drv_flash/drv_flash_f0.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F1']):
src += ['drv_flash/drv_flash_f1.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F2']):
src += ['drv_flash/drv_flash_f2.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F4']):
src += ['drv_flash/drv_flash_f4.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F7']):
src += ['drv_flash/drv_flash_f7.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32L4']):
src += ['drv_flash/drv_flash_l4.c']
if GetDepend('RT_USING_HWCRYPTO'):
src += ['drv_crypto.c']
if GetDepend(['BSP_USING_WDT']):
src += ['drv_wdt.c']
if GetDepend(['BSP_USING_SDIO']):
src += ['drv_sdio.c']
if GetDepend(['BSP_USING_USBD']):
src += ['drv_usbd.c']
if GetDepend(['BSP_USING_PULSE_ENCODER']):
src += ['drv_pulse_encoder.c']
#src += ['drv_common.c']
path = [cwd]
path += [cwd + '/config']
if GetDepend('BSP_USING_ON_CHIP_FLASH'):
path += [cwd + '/drv_flash']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
Return('group')
bsp/tm4c123bsp/libraries/Drivers/config/adc_config.h 0 → 100644
浏览文件 @ aebdcacc
#ifndef _ADC_CONFIG_H_
#define _ADC_CONFIG_H_
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_ADC0
#ifndef ADC0_CONFIG
#define ADC0_CONFIG \
{ \
.name ="adc0", \
.adcbase = ADC0_BASE, \
.channel = 0 , \
.sequence = 2 , \
.trigermode = ADC_TRIGGER_PROCESSOR, \
.sequencepriority = 0 \
}
#endif /* ADC0_CONFIG */
#endif /* BSP_USING_ADC0 */
#ifdef BSP_USING_ADC1
#ifndef ADC1_CONFIG
#define ADC1_CONFIG \
{ \
.name = "adc1", \
.adcbase = ADC1_BASE, \
.channel = 0 , \
.sequence = 3 , \
.syncMode = ADC_TRIGGER_PROCESSOR, \
.sequencepriority = 0 \
}
#endif /* ADC1_CONFIG */
#endif /* BSP_USING_ADC1 */
#ifdef __cplusplus
}
#endif
#endif /*_ADC_CONFIG_H_*/
bsp/tm4c123bsp/libraries/Drivers/config/pwm_config.h 0 → 100644
浏览文件 @ aebdcacc
#ifndef _PWM_CONFIG_H_
#define _PWM_CONFIG_H_
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_PWM0
#ifndef PWM0_CONFIG
#define PWM0_CONFIG \
{ \
.name = "pwm0", \
.channel = 0 , \
.counterMode = PWM_GEN_MODE_UP_DOWN , \
.syncMode = PWM_GEN_MODE_NO_SYNC \
}
#endif /* PWM0_CONFIG */
#endif /* BSP_USING_PWM0 */
#ifdef BSP_USING_PWM1
#ifndef PWM1_CONFIG
#define PWM1_CONFIG \
{ \
.name = "pwm1", \
.channel = 0 , \
.counterMode = PWM_GEN_MODE_UP_DOWN , \
.syncMode = PWM_GEN_MODE_NO_SYNC \
}
#endif /* PWM1_CONFIG */
#endif /* BSP_USING_PWM1 */
#ifdef BSP_USING_PWM2
#ifndef PWM2_CONFIG
#define PWM2_CONFIG \
{ \
.name = "pwm2", \
.channel = 0 , \
.counterMode = PWM_GEN_MODE_UP_DOWN , \
.syncMode = PWM_GEN_MODE_NO_SYNC \
}
#endif /* PWM2_CONFIG */
#endif /* BSP_USING_PWM2 */
#ifdef BSP_USING_PWM3
#ifndef PWM3_CONFIG
#define PWM3_CONFIG \
{ \
.name = "pwm3", \
.channel = 0 , \
.counterMode = PWM_GEN_MODE_UP_DOWN , \
.syncMode = PWM_GEN_MODE_NO_SYNC \
}
#endif /* PWM3_CONFIG */
#endif /* BSP_USING_PWM3 */
#ifdef BSP_USING_PWM4
#ifndef PWM4_CONFIG
#define PWM4_CONFIG \
{ \
.name = "pwm4", \
.channel = 0 , \
.counterMode = PWM_GEN_MODE_UP_DOWN , \
.syncMode = PWM_GEN_MODE_NO_SYNC \
}
#endif /* PWM4_CONFIG */
#endif /* BSP_USING_PWM4 */
#ifdef BSP_USING_PWM5
#ifndef PWM5_CONFIG
#define PWM5_CONFIG \
{ \
.name = "pwm5", \
.channel = 0 , \
.counterMode = PWM_GEN_MODE_UP_DOWN , \
.syncMode = PWM_GEN_MODE_NO_SYNC \
}
#endif /* PWM5_CONFIG */
#endif /* BSP_USING_PWM5 */
#ifdef BSP_USING_PWM6
#ifndef PWM6_CONFIG
#define PWM6_CONFIG \
{ \
.name = "pwm6", \
.channel = 0 , \
.counterMode = PWM_GEN_MODE_UP_DOWN , \
.syncMode = PWM_GEN_MODE_NO_SYNC \
}
#endif /* PWM6_CONFIG */
#endif /* BSP_USING_PWM6 */
#ifdef BSP_USING_PWM7
#ifndef PWM7_CONFIG
#define PWM7_CONFIG \
{ \
.name = "pwm7", \
.channel = 0 , \
.counterMode = PWM_GEN_MODE_UP_DOWN , \
.syncMode = PWM_GEN_MODE_NO_SYNC \
}
#endif /* PWM7_CONFIG */
#endif /* BSP_USING_PWM7 */
#ifdef __cplusplus
}
#endif
#endif /*_PWM_CONFIG_H_*/
bsp/tm4c123bsp/libraries/Drivers/config/spi_config.h 0 → 100644
浏览文件 @ aebdcacc
#ifndef __SPI_CONFIG_H__
#define __SPI_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_SPI0
#ifndef SPI0_BUS_CONFIG
#define SPI0_BUS_CONFIG \
{ \
.base = SSI0_BASE, \
.bus_name = "spi0", \
}
#endif /* SPI0_BUS_CONFIG */
#endif /* BSP_USING_SPI0 */
#ifdef BSP_USING_SPI1
#ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \
{ \
.base = SSI1_BASE, \
.bus_name = "spi1", \
}
#endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */
#ifdef BSP_USING_SPI2
#ifndef SPI2_BUS_CONFIG
#define SPI2_BUS_CONFIG \
{ \
.base = SSI2_BASE, \
.bus_name = "spi2", \
}
#endif /* SPI2_BUS_CONFIG */
#endif /* BSP_USING_SPI2 */
#ifdef BSP_USING_SPI3
#ifndef SPI3_BUS_CONFIG
#define SPI3_BUS_CONFIG \
{ \
.base = SSI3_BASE, \
.bus_name = "spi3", \
}
#endif /* SPI3_BUS_CONFIG */
#endif /* BSP_USING_SPI3 */
#ifdef __cplusplus
}
#endif
#endif /*__SPI_CONFIG_H__ */
bsp/tm4c123bsp/libraries/Drivers/config/uart_config.h 0 → 100644
浏览文件 @ aebdcacc
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART0)
#ifndef UART0_CONFIG
#define UART0_CONFIG \
{ \
.name = "uart0", \
.uartbase = UART0_BASE, \
.baudrate = 115200, \
.mode = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | \
UART_CONFIG_PAR_NONE \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1*/
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.uartbase = UART1_BASE, \
.baudrate = 115200, \
.mode = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | \
UART_CONFIG_PAR_NONE \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1*/
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.uartbase = UART2_BASE, \
.baudrate = 115200, \
.mode = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | \
UART_CONFIG_PAR_NONE \
}
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2*/
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.uartbase = UART3_BASE, \
.baudrate = 115200, \
.mode = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | \
UART_CONFIG_PAR_NONE \
}
#endif /* UART3_CONFIG */
#endif /* BSP_USING_UART3*/
#ifdef __cplusplus
}
#endif
#endif
bsp/tm4c123bsp/libraries/Drivers/drv_adc.c 0 → 100644
浏览文件 @ aebdcacc
#include "drv_adc.h"
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "hw_memmap.h"
#include "adc.h"
#include "sysctl.h"
#ifdef RT_USING_ADC
#include "adc_config.h"
#include "tm4c123_config.h"
#define LOG_TAG "drv.adc"
#include <drv_log.h>
static struct tm4c123_adc_config adc_config[] =
{
#ifdef BSP_USING_ADC0
ADC0_CONFIG,
#endif
#ifdef BSP_USING_ADC1
ADC1_CONFIG,
#endif
};
struct tm4c123_adc
{
struct tm4c123_adc_config *config;
struct rt_adc_device adc_device;
};
static struct tm4c123_adc adc_obj[sizeof(adc_config) / sizeof(adc_config[0])]={0};
static rt_err_t tm4c123_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
{
RT_ASSERT(device != RT_NULL);
//stm32_adc_handler = device->parent.user_data;
if (enabled)
{
ADCSequenceEnable(ADC0_BASE, 2);
ADCIntClear(ADC0_BASE, 2);
}
else
{
ADCSequenceDisable(ADC0_BASE, 2);
}
return RT_EOK;
}
static rt_err_t tm4c123_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(value != RT_NULL);
uint32_t pui32ADC0Value[4]={0};
// Trigger the ADC conversion.
//
ADCProcessorTrigger(ADC0_BASE, 2);
//
// Wait for conversion to be completed.
//
while(!ADCIntStatus(ADC0_BASE, 2, false))
{
}
//
// Clear the ADC interrupt flag.
//
ADCIntClear(ADC0_BASE, 2);
//
// Read ADC Value.
//
ADCSequenceDataGet(ADC0_BASE, 2, pui32ADC0Value);
/* get ADC value */
*value = (rt_uint32_t)pui32ADC0Value[channel];
return RT_EOK;
}
static const struct rt_adc_ops tm4c123_adc_ops =
{
.enabled = tm4c123_adc_enabled,
.convert = tm4c123_get_adc_value,
};
static rt_err_t tm4c123_hw_adc_init(struct tm4c123_adc *device)
{
uint32_t adcbase = device->config->adcbase;
uint32_t sequencenum = device->config->sequence;
ADCSequenceConfigure(adcbase, sequencenum,
device->config->trigermode, 0);
ADCSequenceStepConfigure(ADC0_BASE, 2, 0, ADC_CTL_CH7 );
ADCSequenceStepConfigure(ADC0_BASE, 2, 1, ADC_CTL_CH6 | ADC_CTL_IE );
ADCSequenceStepConfigure(ADC0_BASE, 2, 2, ADC_CTL_CH5 );
//Tell the ADC logic
// that this is the last conversion on sequence 3 (ADC_CTL_END).
ADCSequenceStepConfigure(ADC0_BASE, 2, 3, ADC_CTL_CH4 | ADC_CTL_IE |
ADC_CTL_END);
return RT_EOK;
}
static int tm4c123_adc_init(void)
{
int i = 0;
rt_size_t obj_num = sizeof(adc_obj) / sizeof(struct tm4c123_adc);
rt_err_t result = RT_EOK;
adc_hw_config();
for (i = 0; i < obj_num; i++)
{
/* ADC init */
adc_obj[i].config = &adc_config[i];
if(tm4c123_hw_adc_init(&adc_obj[i])!= RT_EOK)
{
LOG_E("%s init failed", adc_obj[i].config->name);
result = -RT_ERROR;
return result;
}
else
{
LOG_D("%s init success", adc_obj[i].config->name);
/* register adc device */
if (rt_hw_adc_register(&adc_obj[i].adc_device, adc_obj[i].config->name, &tm4c123_adc_ops,RT_NULL) == RT_EOK)
{
LOG_D("%s register success", adc_obj[i].config->name);
}
else
{
LOG_E("%s register failed", adc_obj[i].config->name);
result = -RT_ERROR;
}
}
}
return result;
}
INIT_APP_EXPORT(tm4c123_adc_init);
#endif /*RT_UING_ADC*/
bsp/tm4c123bsp/libraries/Drivers/drv_adc.h 0 → 100644
浏览文件 @ aebdcacc
#ifndef _DRV_ADC_H_
#define _DRV_ADC_H_
#include<stdint.h>
#include<rtthread.h>
#include<rtdevice.h>
#include<rthw.h>
struct tm4c123_adc_config
{
const char *name;
uint32_t adcbase;
uint32_t channel;
uint32_t sequence;
uint32_t trigermode;
uint32_t sequencepriority;
};
#endif /*_DRV_ADC_H_*/
bsp/tm4c123bsp/libraries/Drivers/drv_flash/drv_flash.h 0 → 100644
浏览文件 @ aebdcacc
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-5 SummerGift first version
*/
#ifndef __DRV_FLASH_H__
#define __DRV_FLASH_H__
#include <rtthread.h>
#include "rtdevice.h"
#include <rthw.h>
#include <drv_common.h>
#ifdef __cplusplus
extern "C" {
#endif
int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size);
int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size);
int stm32_flash_erase(rt_uint32_t addr, size_t size);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_FLASH_H__ */
bsp/tm4c123bsp/libraries/Drivers/drv_flash/drv_flash_f1.c 0 → 100644
浏览文件 @ aebdcacc
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-5 SummerGift first version
*/
#include "board.h"
#ifdef BSP_USING_ON_CHIP_FLASH
#include "drv_config.h"
#include "drv_flash.h"
#if defined(PKG_USING_FAL)
#include "fal.h"
#endif
//#define DRV_DEBUG
#define LOG_TAG "drv.flash"
#include <drv_log.h>
/**
* @brief Gets the page of a given address
* @param Addr: Address of the FLASH Memory
* @retval The page of a given address
*/
static uint32_t GetPage(uint32_t addr)
{
uint32_t page = 0;
page = RT_ALIGN_DOWN(addr, FLASH_PAGE_SIZE);
return page;
}
/**
* Read data from flash.
* @note This operation's units is word.
*
* @param addr flash address
* @param buf buffer to store read data
* @param size read bytes size
*
* @return result
*/
int stm32_flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
{
size_t i;
if ((addr + size) > STM32_FLASH_END_ADDRESS)
{
LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -RT_EINVAL;
}
for (i = 0; i < size; i++, buf++, addr++)
{
*buf = *(rt_uint8_t *) addr;
}
return size;
}
/**
* Write data to flash.
* @note This operation's units is word.
* @note This operation must after erase. @see flash_erase.
*
* @param addr flash address
* @param buf the write data buffer
* @param size write bytes size
*
* @return result
*/
int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
{
rt_err_t result = RT_EOK;
rt_uint32_t end_addr = addr + size;
if (addr % 4 != 0)
{
LOG_E("write addr must be 4-byte alignment");
return -RT_EINVAL;
}
if ((end_addr) > STM32_FLASH_END_ADDRESS)
{
LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
return -RT_EINVAL;
}
HAL_FLASH_Unlock();
while (addr < end_addr)
{
if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, addr, *((rt_uint32_t *)buf)) == HAL_OK)
{
if (*(rt_uint32_t *)addr != *(rt_uint32_t *)buf)
{
result = -RT_ERROR;
break;
}
addr += 4;
buf += 4;
}
else
{
result = -RT_ERROR;
break;
}
}
HAL_FLASH_Lock();
if (result != RT_EOK)
{
return result;
}
return size;
}
/**
* Erase data on flash.
* @note This operation is irreversible.
* @note This operation's units is different which on many chips.
*
* @param addr flash address
* @param size erase bytes size
*
* @return result
*/
int stm32_flash_erase(rt_uint32_t addr, size_t size)
{
rt_err_t result = RT_EOK;
uint32_t PAGEError = 0;
/*Variable used for Erase procedure*/
FLASH_EraseInitTypeDef EraseInitStruct;
if ((addr + size) > STM32_FLASH_END_ADDRESS)
{
LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
return -RT_EINVAL;
}
HAL_FLASH_Unlock();
/* Fill EraseInit structure*/
EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES;
EraseInitStruct.PageAddress = GetPage(addr);
EraseInitStruct.NbPages = (size + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE;
if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK)
{
result = -RT_ERROR;
goto __exit;
}
__exit:
HAL_FLASH_Lock();
if (result != RT_EOK)
{
return result;
}
LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
return size;
}
#if defined(PKG_USING_FAL)
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
static int fal_flash_erase(long offset, size_t size);
const struct fal_flash_dev stm32_onchip_flash = { "onchip_flash", STM32_FLASH_START_ADRESS, STM32_FLASH_SIZE, FLASH_PAGE_SIZE, {NULL, fal_flash_read, fal_flash_write, fal_flash_erase} };
static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size)
{
return stm32_flash_read(stm32_onchip_flash.addr + offset, buf, size);
}
static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size)
{
return stm32_flash_write(stm32_onchip_flash.addr + offset, buf, size);
}
static int fal_flash_erase(long offset, size_t size)
{
return stm32_flash_erase(stm32_onchip_flash.addr + offset, size);
}
#endif
#endif /* BSP_USING_ON_CHIP_FLASH */
bsp/tm4c123bsp/libraries/Drivers/drv_gpio.c 0 → 100644
浏览文件 @ aebdcacc
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include <stdint.h>
#include <stdbool.h>
#include "hw_memmap.h"
#include "sysctl.h"
#include "gpio.h"
#include "pin_map.h"
#include "interrupt.h"
#include "rom_map.h"
#include "drv_gpio.h"
#ifdef RT_USING_PIN
static const struct pin_index pins[] =
{
_TM4C_PIN(0 ,F, 0 ),
_TM4C_PIN(1 ,F, 1 ),
_TM4C_PIN(2 ,F, 2 ),
_TM4C_PIN(3 ,F, 3 ),
_TM4C_PIN(4 ,F, 4 )
};
static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
{
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL},
{-1, 0, RT_NULL, RT_NULL}
};
static uint32_t pin_irq_enable_mask=0;
#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
static const struct pin_index *get_pin(uint8_t pin)
{
const struct pin_index *index;
if (pin < ITEM_NUM(pins))
{
index = &pins[pin];
if (index->index == -1)
index = RT_NULL;
}
else
{
index = RT_NULL;
}
return index;
};
static void tm4c123_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
const struct pin_index *index;
index = get_pin(pin);
if (index == RT_NULL)
{
return;
}
if(mode == PIN_MODE_INPUT)
{
GPIOPinTypeGPIOInput(index ->gpioBaseAddress, index->pin);
}
else if(mode == PIN_MODE_OUTPUT)
{
GPIOPinTypeGPIOOutput(index->gpioBaseAddress, index->pin);
}
else if(mode == PIN_MODE_INPUT_PULLUP)
{
//
// Make the pin(s) be inputs.
//
GPIODirModeSet(index->gpioBaseAddress, index->pin, GPIO_DIR_MODE_IN);
//
// Set the pad(s) for standard pullup operation.
//
GPIOPadConfigSet(index->gpioBaseAddress, index->pin, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);
}
else if(mode == PIN_MODE_INPUT_PULLDOWN)
{
//
// Make the pin(s) be inputs.
//
GPIODirModeSet(index->gpioBaseAddress, index->pin, GPIO_DIR_MODE_IN);
//
// Set the pad(s) for standard pulldown operation.
//
GPIOPadConfigSet(index->gpioBaseAddress, index->pin, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPD);
}
else if(mode == PIN_MODE_OUTPUT_OD)
{
//
// Set the pad(s) for standard push-pull operation.
GPIOPadConfigSet(index->gpioBaseAddress, index->pin, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_OD);
//
// Make the pin(s) be outputs.
GPIODirModeSet(index->gpioBaseAddress, index->pin, GPIO_DIR_MODE_OUT);
}
}
static void tm4c123_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t ui8Val)
{
const struct pin_index *index;
index = get_pin(pin);
if( index == RT_NULL)
{
return;
}
if(ui8Val)
{
GPIOPinWrite(index ->gpioBaseAddress, index->pin, index->pin );
}
else
{
GPIOPinWrite(index ->gpioBaseAddress, index->pin, 0 );
}
}
static int tm4c123_pin_read(rt_device_t dev, rt_base_t pin)
{
const struct pin_index *index;
int value = 0;
index = get_pin(pin);
if( index == RT_NULL)
{
return value;
}
value = GPIOPinRead(index ->gpioBaseAddress , index ->pin );
return value;
}
static rt_err_t tm4c123_pin_attach_irq(rt_device_t device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args )
{
//const struct pin_index *index;
return RT_EOK;
}
static rt_err_t tm4c123_pin_dettach_irq(rt_device_t device, rt_int32_t pin)
{
//const struct pin_index *index;
return RT_EOK;
}
static rt_err_t tm4c123_pin_irq_enable(rt_device_t device, rt_base_t pin,
rt_uint32_t enabled)
{
//const struct pin_index *index;
//const struct pin_irq_map *irqmap;
return RT_EOK;
}
const static struct rt_pin_ops _tm4c123_pin_ops =
{
tm4c123_pin_mode,
tm4c123_pin_write,
tm4c123_pin_read,
tm4c123_pin_attach_irq,
tm4c123_pin_dettach_irq,
tm4c123_pin_irq_enable,
};
int rt_hw_pin_init(void)
{
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
return rt_device_pin_register("pin", &_tm4c123_pin_ops, RT_NULL);
}
INIT_BOARD_EXPORT(rt_hw_pin_init);
#endif /*RT_USING_PIN*/
bsp/tm4c123bsp/libraries/Drivers/drv_gpio.h 0 → 100644
浏览文件 @ aebdcacc
#ifndef _DRV_GPIO_H_
#define _DRV_GPIO_H_
#include <stdint.h>
#include <rtthread.h>
#define _TM4C_PIN(index, gpioport, gpio_index) \
{ \
index, GPIO_PORT##gpioport##_BASE, GPIO_PIN_##gpio_index \
}
#define _TM4C_PIN_RESERVE \
{ \
-1, 0, 0 \
}
/* TM4C123 GPIO driver*/
struct pin_index
{
int index;
uint32_t gpioBaseAddress;
uint32_t pin;
};
extern int rt_hw_pin_init(void);
#endif /*_DRV_GPIO_H_*/
bsp/tm4c123bsp/libraries/Drivers/drv_log.h 0 → 100644
浏览文件 @ aebdcacc
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-11-15 SummerGift first version
*/
/*
* NOTE: DO NOT include this file on the header file.
*/
#ifndef LOG_TAG
#define DBG_TAG "drv"
#else
#define DBG_TAG LOG_TAG
#endif /* LOG_TAG */
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>
bsp/tm4c123bsp/libraries/Drivers/drv_pwm.c 0 → 100644
浏览文件 @ aebdcacc
#include "drv_pwm.h"
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "hw_memmap.h"
#include "pwm.h"
#include "sysctl.h"
#ifdef RT_USING_PWM
#include "pwm_config.h"
#include "tm4c123_config.h"
#define LOG_TAG "drv.pwm"
#include <drv_log.h>
enum
{
#ifdef BSP_USING_PWM0
PWM0_INDEX,
#endif
#ifdef BSP_USING_PWM1
PWM1_INDEX,
#endif
#ifdef BSP_USING_PWM2
PWM2_INDEX,
#endif
#ifdef BSP_USING_PWM3
PWM3_INDEX,
#endif
#ifdef BSP_USING_PWM4
PWM4_INDEX,
#endif
#ifdef BSP_USING_PWM5
PWM5_INDEX,
#endif
#ifdef BSP_USING_PWM6
PWM6_INDEX,
#endif
#ifdef BSP_USING_PWM7
PWM7_INDEX,
#endif
};
static struct tm4c123_pwm_config pwm_config[] =
{
#ifdef BSP_USING_PWM0
PWM0_CONFIG,
#endif
#ifdef BSP_USING_PWM1
PWM1_CONFIG,
#endif
#ifdef BSP_USING_PWM2
PWM2_CONFIG,
#endif
#ifdef BSP_USING_PWM3
PWM3_CONFIG,
#endif
#ifdef BSP_USING_PWM4
PWM4_CONFIG,
#endif
#ifdef BSP_USING_PWM5
PWM5_CONFIG,
#endif
#ifdef BSP_USING_PWM6
PWM6_CONFIG,
#endif
#ifdef BSP_USING_PWM7
PWM7_CONFIG,
#endif
};
static struct tm4c123_pwm pwm_obj[sizeof(pwm_config) / sizeof(pwm_config[0])] = {0};
static rt_err_t tm4c123_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
static struct rt_pwm_ops drv_ops =
{
tm4c123_pwm_control
};
static rt_err_t drv_pwm_enable(char* name, struct rt_pwm_configuration *configuration, rt_bool_t enable)
{
/* Converts the channel number to the channel number of Hal library */
int num = name[3]-0x30;
if (!enable)
{
if( num<=3 )
{
PWMOutputState(PWM0_BASE, PWM_OUT_0_BIT<<(num*2+(configuration->channel-1)), false);
}
else
{
PWMOutputState(PWM1_BASE, PWM_OUT_0_BIT<<((num%4)*2+(configuration->channel-1)), false);
}
}
else
{
if( num<=3 )
{
PWMOutputState(PWM0_BASE, PWM_OUT_0_BIT<<(num*2+(configuration->channel-1)), true);
}
else
{
PWMOutputState(PWM1_BASE, PWM_OUT_0_BIT<<((num%4)*2+(configuration->channel-1)), true);
}
}
return RT_EOK;
}
static rt_err_t drv_pwm_get(char* name, struct rt_pwm_configuration *configuration)
{
switch(name[3])
{
case '0':
configuration->period = PWMGenPeriodGet(PWM0_BASE, PWM_GEN_0);
configuration->pulse= PWMPulseWidthGet(PWM0_BASE, PWM_OUT_0+(uint32_t)(configuration->channel-1));
break;
case '1':
configuration->period = PWMGenPeriodGet(PWM0_BASE, PWM_GEN_1);
configuration->pulse= PWMPulseWidthGet(PWM0_BASE, PWM_OUT_2+(uint32_t)(configuration->channel-1));
break;
case '2':
configuration->period = PWMGenPeriodGet(PWM0_BASE, PWM_GEN_2);
configuration->pulse= PWMPulseWidthGet(PWM0_BASE, PWM_OUT_4+(uint32_t)(configuration->channel-1));
break;
case '3':
configuration->period = PWMGenPeriodGet(PWM0_BASE, PWM_GEN_3);
configuration->pulse= PWMPulseWidthGet(PWM0_BASE, PWM_OUT_6+(uint32_t)(configuration->channel-1));
break;
case '4':
configuration->period = PWMGenPeriodGet(PWM1_BASE, PWM_GEN_0);
configuration->pulse= PWMPulseWidthGet(PWM1_BASE, PWM_OUT_0+(uint32_t)(configuration->channel-1));
break;
case '5':
configuration->period = PWMGenPeriodGet(PWM1_BASE, PWM_GEN_1);
configuration->pulse= PWMPulseWidthGet(PWM1_BASE, PWM_OUT_2+(uint32_t)(configuration->channel-1));
break;
case '6':
configuration->period = PWMGenPeriodGet(PWM1_BASE, PWM_GEN_2);
configuration->pulse= PWMPulseWidthGet(PWM1_BASE, PWM_OUT_4+(uint32_t)(configuration->channel-1));
break;
case '7':
configuration->period = PWMGenPeriodGet(PWM1_BASE, PWM_GEN_3);
configuration->pulse= PWMPulseWidthGet(PWM1_BASE, PWM_OUT_6+(uint32_t)(configuration->channel-1));
break;
default:
break;
}
return RT_EOK;
}
static rt_err_t drv_pwm_set(char *name, struct rt_pwm_configuration *configuration)
{
uint32_t sysPwmClock = SysCtlPWMClockGet();
switch(name[3])
{
case '0':
PWMGenPeriodSet(PWM0_BASE, PWM_GEN_0, configuration->period/1000*(sysPwmClock/1000000)); // t(s)/(1/f) = ticks ns/1000/1000000
PWMPulseWidthSet(PWM0_BASE, PWM_OUT_0+(uint32_t)(configuration->channel-1),configuration->pulse/1000*(sysPwmClock/1000000));
PWMGenEnable(PWM0_BASE, PWM_GEN_0);
break;
case '1':
PWMGenPeriodSet(PWM0_BASE, PWM_GEN_1, configuration->period/1000*(sysPwmClock/1000000));
PWMPulseWidthSet(PWM0_BASE, PWM_OUT_0+(uint32_t)(configuration->channel-1),configuration->pulse/1000*(sysPwmClock/1000000));
PWMGenEnable(PWM0_BASE, PWM_GEN_1);
break;
case '2':
PWMGenPeriodSet(PWM0_BASE, PWM_GEN_2, configuration->period/1000*(sysPwmClock/1000000));
PWMPulseWidthSet(PWM0_BASE, PWM_OUT_0+(uint32_t)(configuration->channel-1),configuration->pulse/1000*(sysPwmClock/1000000));
PWMGenEnable(PWM0_BASE, PWM_GEN_2);
break;
case '3':
PWMGenPeriodSet(PWM0_BASE, PWM_GEN_3, configuration->period/1000*(sysPwmClock/1000000));
PWMPulseWidthSet(PWM0_BASE, PWM_OUT_0+(uint32_t)(configuration->channel-1),configuration->pulse/1000*(sysPwmClock/1000000));
PWMGenEnable(PWM0_BASE, PWM_GEN_3);
break;
case '4':
PWMGenPeriodSet(PWM1_BASE, PWM_GEN_0, configuration->period/1000*(sysPwmClock/1000000));
PWMPulseWidthSet(PWM1_BASE, PWM_OUT_0+(uint32_t)(configuration->channel-1),configuration->pulse/1000*(sysPwmClock/1000000));
PWMGenEnable(PWM1_BASE, PWM_GEN_0);
break;
case '5':
PWMGenPeriodSet(PWM1_BASE, PWM_GEN_1, configuration->period/1000*(sysPwmClock/1000000));
PWMPulseWidthSet(PWM1_BASE, PWM_OUT_2+(uint32_t)(configuration->channel-1),configuration->pulse/1000*(sysPwmClock/1000000));
PWMGenEnable(PWM1_BASE, PWM_GEN_1);
break;
case '6':
PWMGenPeriodSet(PWM1_BASE, PWM_GEN_2, configuration->period/1000*(sysPwmClock/1000000));
PWMPulseWidthSet(PWM1_BASE, PWM_OUT_4+(uint32_t)(configuration->channel-1),configuration->pulse/1000*(sysPwmClock/1000000));
PWMGenEnable(PWM1_BASE, PWM_GEN_2);
break;
case '7':
PWMGenPeriodSet(PWM1_BASE, PWM_GEN_3, configuration->period/1000*(sysPwmClock/1000000));
PWMPulseWidthSet(PWM1_BASE, PWM_OUT_6+(uint32_t)(configuration->channel-1),configuration->pulse/1000*(sysPwmClock/1000000));
PWMGenEnable(PWM1_BASE, PWM_GEN_3);
break;
default:
break;
}
return RT_EOK;
}
static rt_err_t tm4c123_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
{
struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
switch (cmd)
{
case PWM_CMD_ENABLE:
return drv_pwm_enable(device->parent.parent.name, configuration, RT_TRUE);
case PWM_CMD_DISABLE:
return drv_pwm_enable(device->parent.parent.name, configuration, RT_FALSE);
case PWM_CMD_SET:
return drv_pwm_set(device->parent.parent.name, configuration);
case PWM_CMD_GET:
return drv_pwm_get(device->parent.parent.name, configuration);
default:
return RT_EINVAL;
}
}
static rt_err_t tm4c123_hw_pwm_init(struct tm4c123_pwm *device)
{
rt_err_t result = RT_EOK;
RT_ASSERT(device != RT_NULL);
pwm_hw_config();
switch( device->config->name[3])
{
case '0':
PWMGenConfigure(PWM0_BASE, PWM_GEN_0, device->config->counterMode |
device->config->syncMode);
break;
case '1':
PWMGenConfigure(PWM0_BASE, PWM_GEN_1, device->config->counterMode |
device->config->syncMode);
break;
case '2':
PWMGenConfigure(PWM0_BASE, PWM_GEN_2, device->config->counterMode |
device->config->syncMode);
break;
case '3':
PWMGenConfigure(PWM0_BASE, PWM_GEN_3, device->config->counterMode |
device->config->syncMode);
break;
case '4':
PWMGenConfigure(PWM1_BASE, PWM_GEN_0, device->config->counterMode |
device->config->syncMode);
break;
case '5':
PWMGenConfigure(PWM1_BASE, PWM_GEN_1, device->config->counterMode |
device->config->syncMode);
break;
case '6':
PWMGenConfigure(PWM1_BASE, PWM_GEN_2, device->config->counterMode |
device->config->syncMode);
break;
case '7':
PWMGenConfigure(PWM1_BASE, PWM_GEN_3, device->config->counterMode |
device->config->syncMode);
break;
default:
LOG_E("%s PWMGenConfigure failed", device->config->name);
result = -RT_ERROR;
return result;
}
return result;
}
int rt_hw_pwm_init(void)
{
int i = 0;
rt_size_t obj_num = sizeof(pwm_obj) / sizeof(struct tm4c123_pwm);
rt_err_t result = RT_EOK;
for(i=0 ; i< obj_num;i++)
{
pwm_obj[i].config = &pwm_config[i];
pwm_obj[i].pwm_device.ops = &drv_ops;
/*pwm_init*/
if(tm4c123_hw_pwm_init(&pwm_obj[i])!= RT_EOK)
{
LOG_E("%s init failed", pwm_obj[i].config->name);
result = -RT_ERROR;
return result;
}
else
{
LOG_D("%s init success", pwm_obj[i].config->name);
/* register pwm device */
if (rt_device_pwm_register(&pwm_obj[i].pwm_device, pwm_obj[i].config->name, &drv_ops,RT_NULL) == RT_EOK)
{
LOG_D("%s register success", pwm_obj[i].config->name);
}
else
{
LOG_E("%s register failed", pwm_obj[i].config->name);
result = -RT_ERROR;
}
}
}
return result;
}
#endif
bsp/tm4c123bsp/libraries/Drivers/drv_pwm.h 0 → 100644
浏览文件 @ aebdcacc
#ifndef _DRV_PWM_H_
#define _DRV_PWM_H_
#include<rtdevice.h>
#include<rthw.h>
struct tm4c123_pwm
{
struct tm4c123_pwm_config *config;
struct rt_device_pwm pwm_device;
};
/* tm4c123 config class */
struct tm4c123_pwm_config
{
rt_uint8_t channel;
char *name;
uint32_t counterMode;
uint32_t syncMode;
};
int rt_hw_pwm_init(void);
#endif /*_DRV_PWM_H_*/
bsp/tm4c123bsp/libraries/Drivers/drv_spi.c 0 → 100644
浏览文件 @ aebdcacc
#include "drv_spi.h"
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include "hw_memmap.h"
#include "ssi.h"
#include "gpio.h"
#include "sysctl.h"
#ifdef RT_USING_SPI
#if defined(BSP_USING_SPI0) || defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3)
/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
#include "tm4c123_config.h"
#include "spi_config.h"
#include <string.h>
//#define DRV_DEBUG
#define LOG_TAG "drv.spi"
#include <drv_log.h>
enum
{
#ifdef BSP_USING_SPI0
SPI0_INDEX,
#endif
#ifdef BSP_USING_SPI1
SPI1_INDEX,
#endif
#ifdef BSP_USING_SPI2
SPI2_INDEX,
#endif
#ifdef BSP_USING_SPI3
SPI3_INDEX,
#endif
};
static struct tm4c123_spi_config spi_config[] =
{
#ifdef BSP_USING_SPI0
SPI0_BUS_CONFIG,
#endif
#ifdef BSP_USING_SPI1
SPI1_BUS_CONFIG,
#endif
#ifdef BSP_USING_SPI2
SPI2_BUS_CONFIG,
#endif
#ifdef BSP_USING_SPI3
SPI3_BUS_CONFIG,
#endif
};
static struct tm4c123_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0};
static rt_err_t tm4c123_spi_configure(struct tm4c123_spi *spi_drv, struct rt_spi_configuration *cfg)
{
RT_ASSERT(spi_drv != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uint32_t ui32Protocol,ui32Mode;
uint32_t ui32BitRate = (uint32_t)cfg->max_hz;
uint32_t ui32DataWidth = (uint32_t)cfg->data_width;
uint32_t pui32DataRx[1];
rt_uint8_t ui8Protocol = 0;
if (cfg->mode & RT_SPI_SLAVE)
{
ui32Mode = SSI_MODE_SLAVE;
}
else
{
ui32Mode = SSI_MODE_MASTER;
}
if (cfg->mode & RT_SPI_CPHA)
{
ui8Protocol += 1;
}
else
{
ui8Protocol += 0;
}
if (cfg->mode & RT_SPI_CPOL)
{
ui8Protocol += 2;
}
else
{
ui8Protocol += 0;
}
switch( ui8Protocol)
{
case 0:
ui32Protocol = SSI_FRF_MOTO_MODE_0;
break;
case 1:
ui32Protocol = SSI_FRF_MOTO_MODE_1;
break;
case 2:
ui32Protocol = SSI_FRF_MOTO_MODE_2;
break;
case 3:
ui32Protocol = SSI_FRF_MOTO_MODE_3;
break;
default:
ui32Protocol = SSI_FRF_MOTO_MODE_0;
break;
}
SSIConfigSetExpClk(spi_drv->config->base, SysCtlClockGet(), ui32Protocol,
ui32Mode, ui32BitRate, ui32DataWidth);
LOG_D("ssiclk freq: %d, SPI limiting freq: %d",SysCtlClockGet(),cfg->max_hz);
/* DMA configuration */
SSIEnable(spi_drv->config->base);
while(SSIDataGetNonBlocking(SSI0_BASE, &pui32DataRx[0]))
{
}
LOG_D("%s init done", spi_drv->config->bus_name);
return RT_EOK;
}
static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
rt_size_t message_length;
rt_uint8_t *recv_buf;
const rt_uint8_t *send_buf;
uint32_t ReadData=0;
int i = 0;
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device->bus != RT_NULL);
RT_ASSERT(device->bus->parent.user_data != RT_NULL);
RT_ASSERT(message != RT_NULL);
struct tm4c123_spi *spi_drv = rt_container_of(device->bus, struct tm4c123_spi, spi_bus);
struct tm4c123_hw_spi_cs *cs = device->parent.user_data;
if (message->cs_take)
{
GPIOPinWrite(cs->portbase, cs->GPIO_Pin, 0);
}
LOG_D("%s transfer prepare and start", spi_drv->config->bus_name);
LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d",
spi_drv->config->bus_name,
(uint32_t)message->send_buf,
(uint32_t)message->recv_buf, message->length);
message_length = message->length;
recv_buf = message->recv_buf;
send_buf = message->send_buf;
if (message->send_buf && message->recv_buf)
{
for(i=0; i< message_length; i++)
{
SSIDataPut(spi_drv->config->base, (uint32_t)send_buf[i]);
while(SSIBusy(spi_drv->config->base))
{
}
SSIDataGet(spi_drv->config->base, &ReadData);
recv_buf[i] = (unsigned char)ReadData;
}
}
else if (message->send_buf)
{
for(i=0; i< message_length; i++)
{
SSIDataPut(spi_drv->config->base, (uint32_t)send_buf[i]);
while(SSIBusy(spi_drv->config->base))
{
}
SSIDataGet(spi_drv->config->base, &ReadData);
}
}
else
{
for(i=0; i< message_length; i++)
{
SSIDataPut(spi_drv->config->base, (uint32_t)0xff);
while(SSIBusy(spi_drv->config->base))
{
}
SSIDataGet(spi_drv->config->base, &ReadData);
recv_buf[i] = (unsigned char)ReadData;
}
}
LOG_D("%s transfer done", spi_drv->config->bus_name);
if (message->cs_release)
{
GPIOPinWrite(cs->portbase, cs->GPIO_Pin, cs->GPIO_Pin);
}
return message->length;
}
static rt_err_t spi_configure(struct rt_spi_device *device,
struct rt_spi_configuration *configuration)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(configuration != RT_NULL);
struct tm4c123_spi *spi_drv = rt_container_of(device->bus, struct tm4c123_spi, spi_bus);
spi_drv->cfg = configuration;
return tm4c123_spi_configure(spi_drv, configuration);
}
static const struct rt_spi_ops tm4c123_spi_ops =
{
.configure = spi_configure,
.xfer = spixfer,
};
static int rt_hw_spi_bus_init(void)
{
rt_err_t result;
for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++)
{
spi_bus_obj[i].config = &spi_config[i];
spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i];
result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &tm4c123_spi_ops);
RT_ASSERT(result == RT_EOK);
LOG_D("%s bus init done", spi_config[i].bus_name);
}
return result;
}
/**
* Attach the spi device to SPI bus, this function must be used after initialization.
*/
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint32_t portindex ,uint32_t cs_gpiobase, uint32_t cs_gpio_pin)
{
RT_ASSERT(bus_name != RT_NULL);
RT_ASSERT(device_name != RT_NULL);
rt_err_t result;
struct rt_spi_device *spi_device;
struct tm4c123_hw_spi_cs *cs_pin;
/* initialize the cs pin && select the slave*/
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA+portindex);
GPIOPinTypeGPIOOutput(cs_gpiobase, cs_gpio_pin);
GPIOPinWrite(cs_gpiobase, cs_gpio_pin, cs_gpio_pin);
/* attach the device to spi bus*/
spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
RT_ASSERT(spi_device != RT_NULL);
cs_pin = (struct tm4c123_hw_spi_cs *)rt_malloc(sizeof(struct tm4c123_hw_spi_cs));
RT_ASSERT(cs_pin != RT_NULL);
cs_pin->portbase = cs_gpiobase;
cs_pin->GPIO_Pin = cs_gpio_pin;
result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
if (result != RT_EOK)
{
LOG_E("%s attach to %s faild, %d\n", device_name, bus_name, result);
}
RT_ASSERT(result == RT_EOK);
LOG_D("%s attach to %s done", device_name, bus_name);
return result;
}
int rt_hw_spi_init(void)
{
spi_hw_config();
return rt_hw_spi_bus_init();
}
INIT_BOARD_EXPORT(rt_hw_spi_init);
#endif /* defined(BSP_USING_SPI0) || defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) || defined(BSP_USING_SPI3) */
#endif /*RT_USING_SPI*/
bsp/tm4c123bsp/libraries/Drivers/drv_spi.h 0 → 100644
浏览文件 @ aebdcacc
#ifndef __DRV_SPI_H_
#define __DRV_SPI_H_
#include <rtdevice.h>
#include <rthw.h>
#include "drivers/spi.h"
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint32_t portindex, uint32_t cs_gpiobase, uint32_t cs_gpio_pin);
struct tm4c123_hw_spi_cs
{
uint32_t portbase;
uint32_t GPIO_Pin;
};
struct tm4c123_spi_config
{
uint32_t base;
char * bus_name;
};
/* tm4c123 spi dirver class */
struct tm4c123_spi
{
struct tm4c123_spi_config *config;
struct rt_spi_configuration *cfg;
struct rt_spi_bus spi_bus;
};
struct tm4c123_spi_device
{
rt_uint32_t pin;
char *bus_name;
char *device_name;
};
#define SPI_USING_RX_DMA_FLAG (1<<0)
#define SPI_USING_TX_DMA_FLAG (1<<1)
#endif /*__DRV_SPI_H_ */
bsp/tm4c123bsp/libraries/Drivers/drv_uart.c 0 → 100644
浏览文件 @ aebdcacc
#include <stdint.h>
#include <stdbool.h>
#include "hw_memmap.h"
#include "hw_ints.h"
#include "sysctl.h"
#include "gpio.h"
#include "pin_map.h"
#include "interrupt.h"
#include "rom_map.h"
#include "uart.h"
#include "drv_uart.h"
#include "uart_config.h"
#include "tm4c123_config.h"
#ifdef RT_USING_SERIAL
#define LOG_TAG "drv.uart"
#include <drv_log.h>
#if !defined(BSP_USING_UART0)&&!defined(BSP_USING_UART1)&&!defined(BSP_USING_UART2)&&!defined(BSP_USING_UART3)
#error "Please define at least one BSP_USING_UARTx"
#endif
enum {
#ifdef BSP_USING_UART0
UART0_INDEX,
#endif
#ifdef BSP_USING_UART1
UART1_INDEX,
#endif
#ifdef BSP_USING_UART2
UART2_INDEX,
#endif
#ifdef BSP_USING_UART3
UART3_INDEX,
#endif
};
uint32_t uart_intbase[]=
{
#ifdef BSP_USING_UART0
INT_UART0,
#endif
#ifdef BSP_USING_UART1
INT_UART1,
#endif
#ifdef BSP_USING_UART2
INT_UART2,
#endif
#ifdef BSP_USING_UART3
INT_UART3
#endif
};
static struct tm4c123_uart_config uart_config[] =
{
#ifdef BSP_USING_UART0
UART0_CONFIG,
#endif
#ifdef BSP_USING_UART1
UART1_CONFIG,
#endif
#ifdef BSP_USING_UART2
UART2_CONFIG,
#endif
#ifdef BSP_USING_UART3
UART3_CONFIG,
#endif
};
static struct tm4c123_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
//struct serial_configure
//{
// rt_uint32_t baud_rate; /* ??? */
// rt_uint32_t data_bits :4; /* ??? */
// rt_uint32_t stop_bits :2; /* ??? */
// rt_uint32_t parity :2; /* ????? */
// rt_uint32_t bit_order :1; /* ?????????? */
// rt_uint32_t invert :1; /* ?? */
// rt_uint32_t bufsz :16; /* ????????? */
// rt_uint32_t reserved :4; /* ??? */
//};
//rtservice.h
//#define rt_container_of(ptr, type, member) ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member)))
static rt_err_t tm4c123_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
struct tm4c123_uart *uart;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart = rt_container_of(serial, struct tm4c123_uart, serial);
UARTFIFOLevelSet(uart->config->uartbase, UART_FIFO_TX1_8, UART_FIFO_RX1_8);
UARTConfigSetExpClk(uart->config->uartbase, SysCtlClockGet(), uart->config->baudrate,
uart->config->mode);
return RT_EOK;
}
static rt_err_t tm4c123_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct tm4c123_uart *uart;
#ifdef RT_SERIAL_USING_DMA
rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
#endif
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct tm4c123_uart, serial);
switch (cmd)
{
/* disable interrupt */
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
IntDisable(uart->uartintbase);
/* disable interrupt */
//UARTIntDisable(UART0_BASE, UART_INT_RX | UART_INT_RT);
UARTIntDisable(uart->config->uartbase, UART_INT_RX);
break;
/* enable interrupt */
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
IntEnable(uart->uartintbase);
//UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT);
UARTIntEnable(uart->config->uartbase, UART_INT_RX);
break;
#ifdef RT_SERIAL_USING_DMA
case RT_DEVICE_CTRL_CONFIG:
break;
#endif
}
return RT_EOK;
}
static int tm4c123_putc(struct rt_serial_device *serial, char c)
{
struct tm4c123_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct tm4c123_uart, serial);
UARTCharPut(uart->config->uartbase, c);
return 1;
}
static int tm4c123_getc(struct rt_serial_device *serial)
{
int ch;
struct tm4c123_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct tm4c123_uart, serial);
ch = -1;
ch = UARTCharGetNonBlocking(uart->config->uartbase);
return ch;
}
static rt_size_t tm4c123_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
{
struct tm4c123_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct tm4c123_uart, serial);
if (size == 0)
{
return 0;
}
// if (RT_SERIAL_DMA_TX == direction)
// {
// if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK)
// {
// return size;
// }
// else
// {
// return 0;
// }
// }
return 0;
}
static const struct rt_uart_ops tm4c123_uart_ops =
{
.configure = tm4c123_configure,
.control = tm4c123_control,
.putc = tm4c123_putc,
.getc = tm4c123_getc,
.dma_transmit = tm4c123_dma_transmit
};
/**
* Uart common interrupt process. This need add to uart ISR.
*
* @param serial serial device
*/
static void uart_isr(struct rt_serial_device *serial)
{
struct tm4c123_uart *uart;
uint32_t ui32Ints;
#ifdef RT_SERIAL_USING_DMA
rt_size_t recv_total_index, recv_len;
rt_base_t level;
#endif
RT_ASSERT(serial != RT_NULL);
uart = rt_container_of(serial, struct tm4c123_uart, serial);
ui32Ints = UARTIntStatus(uart->config->uartbase, true);
UARTIntClear(uart->config->uartbase, ui32Ints);
/* UART in mode Receiver -------------------------------------------------*/
if(ui32Ints & (UART_INT_RX | UART_INT_RT))
{
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
}
}
#if defined(BSP_USING_UART0)
void UART0IntHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&(uart_obj[UART0_INDEX].serial));
/* leave interrupt */
rt_interrupt_leave();
}
#endif
#if defined(BSP_USING_UART1)
void UART1IntHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
uart_isr(&(uart_obj[UART1_INDEX].serial));
/* leave interrupt */
rt_interrupt_leave();
}
//#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
//void UART1_DMA_RX_IRQHandler(void)
//{
// /* enter interrupt */
// rt_interrupt_enter();
// HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle);
// /* leave interrupt */
// rt_interrupt_leave();
//}
//#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
//#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
//void UART1_DMA_TX_IRQHandler(void)
//{
// /* enter interrupt */
// rt_interrupt_enter();
// HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle);
// /* leave interrupt */
// rt_interrupt_leave();
//}
//#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
#endif /* BSP_USING_UART1 */
static void tm4c123_uart_get_dma_config(void)
{
#ifdef BSP_USING_UART1
#endif
}
int rt_hw_usart_init(void)
{
rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct tm4c123_uart);
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
rt_err_t result = 0;
//tm4c123_uart_get_dma_config();
uart_hw_config();
for (int i = 0; i < obj_num; i++)
{
uart_obj[i].config = &uart_config[i];
uart_obj[i].uartintbase = uart_intbase[i];
uart_obj[i].serial.ops = &tm4c123_uart_ops;
uart_obj[i].serial.config = config;
/* register UART device */
result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
RT_DEVICE_FLAG_RDWR
| RT_DEVICE_FLAG_INT_RX
| RT_DEVICE_FLAG_INT_TX
| uart_obj[i].uart_dma_flag
, NULL);
RT_ASSERT(result == RT_EOK);
}
return result;
}
#endif /* RT_USING_SERIAL */
bsp/tm4c123bsp/libraries/Drivers/drv_uart.h 0 → 100644
浏览文件 @ aebdcacc
#ifndef _DRV_UART_H_
#define _DRV_UART_H_
#include <stdint.h>
#include <rthw.h>
#include <rtthread.h>
#include "rtdevice.h"
/* tm4c123 config class */
struct tm4c123_uart_config
{
const char *name;
uint32_t uartbase;
uint32_t baudrate;
uint32_t mode;
//struct dma_config *dma_rx;
//struct dma_config *dma_tx;
};
/* tm4c123 uart dirver class */
struct tm4c123_uart
{
struct tm4c123_uart_config *config;
uint32_t uartintbase;
#ifdef RT_SERIAL_USING_DMA
#endif
rt_uint16_t uart_dma_flag;
struct rt_serial_device serial;
};
extern int rt_hw_usart_init(void);
#endif /*_DRV_UART_H_*/
bsp/tm4c123bsp/libraries/TivaWare_C_series/SConscript 0 → 100644
浏览文件 @ aebdcacc
import rtconfig
Import('RTT_ROOT')
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Split("""
tm4c123_driverlib/src/sysctl.c
tm4c123_driverlib/src/systick.c
tm4c123_driverlib/src/interrupt.c
tm4c123_driverlib/src/fpu.c
tm4c123_driverlib/src/cpu.c
tm4c123_driverlib/src/gpio.c
""")
#if GetDepend(['RT_USING_PIN']):
if GetDepend(['RT_USING_SERIAL']):
src += ['tm4c123_driverlib/src/uart.c']
#if GetDepend(['RT_USING_I2C']):
if GetDepend(['RT_USING_SPI']):
src += ['tm4c123_driverlib/src/ssi.c']
#if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']):
#if GetDepend(['RT_USING_CAN']):
#if GetDepend(['RT_USING_HWTIMER'])
if GetDepend(['RT_USING_PWM']) or GetDepend(['RT_USING_PULSE_ENCODER']):
src += ['tm4c123_driverlib/src/pwm.c']
#if GetDepend(['BSP_USING_ETH']):
if GetDepend(['RT_USING_ADC']):
src += ['tm4c123_driverlib/src/adc.c']
#if GetDepend(['RT_USING_RTC']):
#if GetDepend(['RT_USING_WDT']):
#if GetDepend(['RT_USING_SDIO']):
#if GetDepend(['RT_USING_AUDIO']):
#if GetDepend(['RT_USING_MTD_NOR']):
#if GetDepend(['RT_USING_MTD_NAND']):
#if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
path = [cwd + '/tm4c123_driverlib',
cwd + '/tm4c123_driverlib/driverlib',
cwd + '/tm4c123_driverlib/driverlib/inc']
group = DefineGroup('TM4C123_HAL', src, depend = [''], CPPPATH = path)
Return('group')
bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/adc.h 0 → 100644
浏览文件 @ aebdcacc
//*****************************************************************************
//
// adc.h - ADC headers for using the ADC driver functions.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_ADC_H__
#define __DRIVERLIB_ADC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ADCSequenceConfigure as the ui32Trigger
// parameter.
//
//*****************************************************************************
#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event
#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event
#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event
#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event
#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event
#define ADC_TRIGGER_TIMER 0x00000005 // Timer event
#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event
#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event
#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event
#define ADC_TRIGGER_PWM3 0x00000009 // PWM3 event
#define ADC_TRIGGER_NEVER 0x0000000E // Never Trigger
#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event
#define ADC_TRIGGER_PWM_MOD0 0x00000000 // PWM triggers from PWM0
#define ADC_TRIGGER_PWM_MOD1 0x00000010 // PWM triggers from PWM1
//*****************************************************************************
//
// Values that can be passed to ADCSequenceStepConfigure as the ui32Config
// parameter.
//
//*****************************************************************************
#define ADC_CTL_TS 0x00000080 // Temperature sensor select
#define ADC_CTL_IE 0x00000040 // Interrupt enable
#define ADC_CTL_END 0x00000020 // Sequence end select
#define ADC_CTL_D 0x00000010 // Differential select
#define ADC_CTL_CH0 0x00000000 // Input channel 0
#define ADC_CTL_CH1 0x00000001 // Input channel 1
#define ADC_CTL_CH2 0x00000002 // Input channel 2
#define ADC_CTL_CH3 0x00000003 // Input channel 3
#define ADC_CTL_CH4 0x00000004 // Input channel 4
#define ADC_CTL_CH5 0x00000005 // Input channel 5
#define ADC_CTL_CH6 0x00000006 // Input channel 6
#define ADC_CTL_CH7 0x00000007 // Input channel 7
#define ADC_CTL_CH8 0x00000008 // Input channel 8
#define ADC_CTL_CH9 0x00000009 // Input channel 9
#define ADC_CTL_CH10 0x0000000A // Input channel 10
#define ADC_CTL_CH11 0x0000000B // Input channel 11
#define ADC_CTL_CH12 0x0000000C // Input channel 12
#define ADC_CTL_CH13 0x0000000D // Input channel 13
#define ADC_CTL_CH14 0x0000000E // Input channel 14
#define ADC_CTL_CH15 0x0000000F // Input channel 15
#define ADC_CTL_CH16 0x00000100 // Input channel 16
#define ADC_CTL_CH17 0x00000101 // Input channel 17
#define ADC_CTL_CH18 0x00000102 // Input channel 18
#define ADC_CTL_CH19 0x00000103 // Input channel 19
#define ADC_CTL_CH20 0x00000104 // Input channel 20
#define ADC_CTL_CH21 0x00000105 // Input channel 21
#define ADC_CTL_CH22 0x00000106 // Input channel 22
#define ADC_CTL_CH23 0x00000107 // Input channel 23
#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0
#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1
#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2
#define ADC_CTL_CMP3 0x000B0000 // Select Comparator 3
#define ADC_CTL_CMP4 0x000C0000 // Select Comparator 4
#define ADC_CTL_CMP5 0x000D0000 // Select Comparator 5
#define ADC_CTL_CMP6 0x000E0000 // Select Comparator 6
#define ADC_CTL_CMP7 0x000F0000 // Select Comparator 7
#define ADC_CTL_SHOLD_4 0x00000000 // Sample and hold 4 ADC clocks
#define ADC_CTL_SHOLD_8 0x00200000 // Sample and hold 8 ADC clocks
#define ADC_CTL_SHOLD_16 0x00400000 // Sample and hold 16 ADC clocks
#define ADC_CTL_SHOLD_32 0x00600000 // Sample and hold 32 ADC clocks
#define ADC_CTL_SHOLD_64 0x00800000 // Sample and hold 64 ADC clocks
#define ADC_CTL_SHOLD_128 0x00A00000 // Sample and hold 128 ADC clocks
#define ADC_CTL_SHOLD_256 0x00C00000 // Sample and hold 256 ADC clocks
//*****************************************************************************
//
// Values that can be passed to ADCComparatorConfigure as part of the
// ui32Config parameter.
//
//*****************************************************************************
#define ADC_COMP_TRIG_NONE 0x00000000 // Trigger Disabled
#define ADC_COMP_TRIG_LOW_ALWAYS \
0x00001000 // Trigger Low Always
#define ADC_COMP_TRIG_LOW_ONCE 0x00001100 // Trigger Low Once
#define ADC_COMP_TRIG_LOW_HALWAYS \
0x00001200 // Trigger Low Always (Hysteresis)
#define ADC_COMP_TRIG_LOW_HONCE 0x00001300 // Trigger Low Once (Hysteresis)
#define ADC_COMP_TRIG_MID_ALWAYS \
0x00001400 // Trigger Mid Always
#define ADC_COMP_TRIG_MID_ONCE 0x00001500 // Trigger Mid Once
#define ADC_COMP_TRIG_HIGH_ALWAYS \
0x00001C00 // Trigger High Always
#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00 // Trigger High Once
#define ADC_COMP_TRIG_HIGH_HALWAYS \
0x00001E00 // Trigger High Always (Hysteresis)
#define ADC_COMP_TRIG_HIGH_HONCE \
0x00001F00 // Trigger High Once (Hysteresis)
#define ADC_COMP_INT_NONE 0x00000000 // Interrupt Disabled
#define ADC_COMP_INT_LOW_ALWAYS \
0x00000010 // Interrupt Low Always
#define ADC_COMP_INT_LOW_ONCE 0x00000011 // Interrupt Low Once
#define ADC_COMP_INT_LOW_HALWAYS \
0x00000012 // Interrupt Low Always
// (Hysteresis)
#define ADC_COMP_INT_LOW_HONCE 0x00000013 // Interrupt Low Once (Hysteresis)
#define ADC_COMP_INT_MID_ALWAYS \
0x00000014 // Interrupt Mid Always
#define ADC_COMP_INT_MID_ONCE 0x00000015 // Interrupt Mid Once
#define ADC_COMP_INT_HIGH_ALWAYS \
0x0000001C // Interrupt High Always
#define ADC_COMP_INT_HIGH_ONCE 0x0000001D // Interrupt High Once
#define ADC_COMP_INT_HIGH_HALWAYS \
0x0000001E // Interrupt High Always
// (Hysteresis)
#define ADC_COMP_INT_HIGH_HONCE \
0x0000001F // Interrupt High Once (Hysteresis)
//*****************************************************************************
//
// Values that can be used to modify the sequence number passed to
// ADCProcessorTrigger in order to get cross-module synchronous processor
// triggers.
//
//*****************************************************************************
#define ADC_TRIGGER_WAIT 0x08000000 // Wait for the synchronous trigger
#define ADC_TRIGGER_SIGNAL 0x80000000 // Signal the synchronous trigger
//*****************************************************************************
//
// Values that can be passed to ADCPhaseDelaySet as the ui32Phase parameter and
// returned from ADCPhaseDelayGet.
//
//*****************************************************************************
#define ADC_PHASE_0 0x00000000 // 0 degrees
#define ADC_PHASE_22_5 0x00000001 // 22.5 degrees
#define ADC_PHASE_45 0x00000002 // 45 degrees
#define ADC_PHASE_67_5 0x00000003 // 67.5 degrees
#define ADC_PHASE_90 0x00000004 // 90 degrees
#define ADC_PHASE_112_5 0x00000005 // 112.5 degrees
#define ADC_PHASE_135 0x00000006 // 135 degrees
#define ADC_PHASE_157_5 0x00000007 // 157.5 degrees
#define ADC_PHASE_180 0x00000008 // 180 degrees
#define ADC_PHASE_202_5 0x00000009 // 202.5 degrees
#define ADC_PHASE_225 0x0000000A // 225 degrees
#define ADC_PHASE_247_5 0x0000000B // 247.5 degrees
#define ADC_PHASE_270 0x0000000C // 270 degrees
#define ADC_PHASE_292_5 0x0000000D // 292.5 degrees
#define ADC_PHASE_315 0x0000000E // 315 degrees
#define ADC_PHASE_337_5 0x0000000F // 337.5 degrees
//*****************************************************************************
//
// Values that can be passed to ADCReferenceSet as the ui32Ref parameter.
//
//*****************************************************************************
#define ADC_REF_INT 0x00000000 // Internal reference
#define ADC_REF_EXT_3V 0x00000001 // External 3V reference
//*****************************************************************************
//
// Values that can be passed to ADCIntDisableEx(), ADCIntEnableEx(),
// ADCIntClearEx() and ADCIntStatusEx().
//
//*****************************************************************************
#define ADC_INT_SS0 0x00000001
#define ADC_INT_SS1 0x00000002
#define ADC_INT_SS2 0x00000004
#define ADC_INT_SS3 0x00000008
#define ADC_INT_DMA_SS0 0x00000100
#define ADC_INT_DMA_SS1 0x00000200
#define ADC_INT_DMA_SS2 0x00000400
#define ADC_INT_DMA_SS3 0x00000800
#define ADC_INT_DCON_SS0 0x00010000
#define ADC_INT_DCON_SS1 0x00020000
#define ADC_INT_DCON_SS2 0x00040000
#define ADC_INT_DCON_SS3 0x00080000
//*****************************************************************************
//
// Values that can be passed to ADCClockConfigSet() and ADCClockConfigGet().
//
//*****************************************************************************
#define ADC_CLOCK_RATE_FULL 0x00000070
#define ADC_CLOCK_RATE_HALF 0x00000050
#define ADC_CLOCK_RATE_FOURTH 0x00000030
#define ADC_CLOCK_RATE_EIGHTH 0x00000010
#define ADC_CLOCK_SRC_PLL 0x00000000
#define ADC_CLOCK_SRC_PIOSC 0x00000001
#define ADC_CLOCK_SRC_ALTCLK 0x00000001
#define ADC_CLOCK_SRC_MOSC 0x00000002
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ADCIntRegister(uint32_t ui32Base, uint32_t ui32SequenceNum,
void (*pfnHandler)(void));
extern void ADCIntUnregister(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern uint32_t ADCIntStatus(uint32_t ui32Base, uint32_t ui32SequenceNum,
bool bMasked);
extern void ADCIntClear(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCSequenceEnable(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCSequenceDisable(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum,
uint32_t ui32Trigger, uint32_t ui32Priority);
extern void ADCSequenceStepConfigure(uint32_t ui32Base,
uint32_t ui32SequenceNum,
uint32_t ui32Step, uint32_t ui32Config);
extern int32_t ADCSequenceOverflow(uint32_t ui32Base,
uint32_t ui32SequenceNum);
extern void ADCSequenceOverflowClear(uint32_t ui32Base,
uint32_t ui32SequenceNum);
extern int32_t ADCSequenceUnderflow(uint32_t ui32Base,
uint32_t ui32SequenceNum);
extern void ADCSequenceUnderflowClear(uint32_t ui32Base,
uint32_t ui32SequenceNum);
extern int32_t ADCSequenceDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum,
uint32_t *pui32Buffer);
extern void ADCProcessorTrigger(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCSoftwareOversampleConfigure(uint32_t ui32Base,
uint32_t ui32SequenceNum,
uint32_t ui32Factor);
extern void ADCSoftwareOversampleStepConfigure(uint32_t ui32Base,
uint32_t ui32SequenceNum,
uint32_t ui32Step,
uint32_t ui32Config);
extern void ADCSoftwareOversampleDataGet(uint32_t ui32Base,
uint32_t ui32SequenceNum,
uint32_t *pui32Buffer,
uint32_t ui32Count);
extern void ADCHardwareOversampleConfigure(uint32_t ui32Base,
uint32_t ui32Factor);
extern void ADCClockConfigSet(uint32_t ui32Base, uint32_t ui32Config,
uint32_t ui32ClockDiv);
extern uint32_t ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv);
extern void ADCComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp,
uint32_t ui32Config);
extern void ADCComparatorRegionSet(uint32_t ui32Base, uint32_t ui32Comp,
uint32_t ui32LowRef, uint32_t ui32HighRef);
extern void ADCComparatorReset(uint32_t ui32Base, uint32_t ui32Comp,
bool bTrigger, bool bInterrupt);
extern void ADCComparatorIntDisable(uint32_t ui32Base,
uint32_t ui32SequenceNum);
extern void ADCComparatorIntEnable(uint32_t ui32Base,
uint32_t ui32SequenceNum);
extern uint32_t ADCComparatorIntStatus(uint32_t ui32Base);
extern void ADCComparatorIntClear(uint32_t ui32Base, uint32_t ui32Status);
extern void ADCIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void ADCIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags);
extern uint32_t ADCIntStatusEx(uint32_t ui32Base, bool bMasked);
extern void ADCIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void ADCSequenceDMAEnable(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern void ADCSequenceDMADisable(uint32_t ui32Base, uint32_t ui32SequenceNum);
extern bool ADCBusy(uint32_t ui32Base);
extern void ADCReferenceSet(uint32_t ui32Base, uint32_t ui32Ref);
extern uint32_t ADCReferenceGet(uint32_t ui32Base);
extern void ADCPhaseDelaySet(uint32_t ui32Base, uint32_t ui32Phase);
extern uint32_t ADCPhaseDelayGet(uint32_t ui32Base);
extern void ADCSampleRateSet(uint32_t ui32Base, uint32_t ui32ADCClock,
uint32_t ui32Rate);
extern uint32_t ADCSampleRateGet(uint32_t ui32Base);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_ADC_H__
bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/aes.h 0 → 100644
浏览文件 @ aebdcacc
//*****************************************************************************
//
// aes.h - Defines and Macros for the AES module.
//
// Copyright (c) 2012-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_AES_H__
#define __DRIVERLIB_AES_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are used to specify the operation direction in the
// ui32Config argument in the AESConfig function. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_DIR_ENCRYPT 0x00000004
#define AES_CFG_DIR_DECRYPT 0x00000000
//*****************************************************************************
//
// The following defines are used to specify the key size in the ui32Config
// argument in the AESConfig function. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_KEY_SIZE_128BIT 0x00000008
#define AES_CFG_KEY_SIZE_192BIT 0x00000010
#define AES_CFG_KEY_SIZE_256BIT 0x00000018
//*****************************************************************************
//
// The following defines are used to specify the mode of operation in the
// ui32Config argument in the AESConfig function. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_MODE_M 0x2007fe60
#define AES_CFG_MODE_ECB 0x00000000
#define AES_CFG_MODE_CBC 0x00000020
#define AES_CFG_MODE_CTR 0x00000040
#define AES_CFG_MODE_ICM 0x00000200
#define AES_CFG_MODE_CFB 0x00000400
#define AES_CFG_MODE_XTS_TWEAKJL \
0x00000800
#define AES_CFG_MODE_XTS_K2IJL \
0x00001000
#define AES_CFG_MODE_XTS_K2ILJ0 \
0x00001800
#define AES_CFG_MODE_F8 0x00002000
#define AES_CFG_MODE_F9 0x20004000
#define AES_CFG_MODE_CBCMAC 0x20008000
#define AES_CFG_MODE_GCM_HLY0ZERO \
0x20010000
#define AES_CFG_MODE_GCM_HLY0CALC \
0x20020040
#define AES_CFG_MODE_GCM_HY0CALC \
0x20030040
#define AES_CFG_MODE_CCM 0x20040040
//*****************************************************************************
//
// The following defines are used to specify the counter width in the
// ui32Config argument in the AESConfig function. It is only required to
// be defined when using CTR, CCM, or GCM modes. Only one length is permitted.
//
//*****************************************************************************
#define AES_CFG_CTR_WIDTH_32 0x00000000
#define AES_CFG_CTR_WIDTH_64 0x00000080
#define AES_CFG_CTR_WIDTH_96 0x00000100
#define AES_CFG_CTR_WIDTH_128 0x00000180
//*****************************************************************************
//
// The following defines are used to define the width of the length field for
// CCM operation through the ui32Config argument in the AESConfig function.
// This value is also known as L. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_CCM_L_1 0x00000000
#define AES_CFG_CCM_L_2 0x00080000
#define AES_CFG_CCM_L_3 0x00100000
#define AES_CFG_CCM_L_4 0x00180000
#define AES_CFG_CCM_L_5 0x00200000
#define AES_CFG_CCM_L_6 0x00280000
#define AES_CFG_CCM_L_7 0x00300000
#define AES_CFG_CCM_L_8 0x00380000
//*****************************************************************************
//
// The following defines are used to define the length of the authentication
// field for CCM operations through the ui32Config argument in the AESConfig
// function. This value is also known as M. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_CCM_M_4 0x00400000
#define AES_CFG_CCM_M_6 0x00800000
#define AES_CFG_CCM_M_8 0x00c00000
#define AES_CFG_CCM_M_10 0x01000000
#define AES_CFG_CCM_M_12 0x01400000
#define AES_CFG_CCM_M_14 0x01800000
#define AES_CFG_CCM_M_16 0x01c00000
//*****************************************************************************
//
// Interrupt flags for use with the AESIntEnable, AESIntDisable, and
// AESIntStatus functions.
//
//*****************************************************************************
#define AES_INT_CONTEXT_IN 0x00000001
#define AES_INT_CONTEXT_OUT 0x00000008
#define AES_INT_DATA_IN 0x00000002
#define AES_INT_DATA_OUT 0x00000004
#define AES_INT_DMA_CONTEXT_IN 0x00010000
#define AES_INT_DMA_CONTEXT_OUT 0x00080000
#define AES_INT_DMA_DATA_IN 0x00020000
#define AES_INT_DMA_DATA_OUT 0x00040000
//*****************************************************************************
//
// Defines used when enabling and disabling DMA requests in the
// AESEnableDMA and AESDisableDMA functions.
//
//*****************************************************************************
#define AES_DMA_DATA_IN 0x00000020
#define AES_DMA_DATA_OUT 0x00000040
#define AES_DMA_CONTEXT_IN 0x00000080
#define AES_DMA_CONTEXT_OUT 0x00000100
//*****************************************************************************
//
// Function prototypes.
//
//*****************************************************************************
extern void AESAuthLengthSet(uint32_t ui32Base, uint32_t ui32Length);
extern void AESConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void AESDataRead(uint32_t ui32Base, uint32_t *pui32Dest);
extern bool AESDataReadNonBlocking(uint32_t ui32Base, uint32_t *pui32Dest);
extern bool AESDataProcess(uint32_t ui32Base, uint32_t *pui32Src,
uint32_t *pui32Dest, uint32_t ui32Length);
extern bool AESDataAuth(uint32_t ui32Base, uint32_t *pui32Src,
uint32_t ui32Length, uint32_t *pui32Tag);
extern bool AESDataProcessAuth(uint32_t ui32Base, uint32_t *pui32Src,
uint32_t *pui32Dest, uint32_t ui32Length,
uint32_t *pui32AuthSrc,
uint32_t ui32AuthLength, uint32_t *pui32Tag);
extern void AESDataWrite(uint32_t ui32Base, uint32_t *pui32Src);
extern bool AESDataWriteNonBlocking(uint32_t ui32Base, uint32_t *pui32Src);
extern void AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags);
extern void AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags);
extern void AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void AESIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
extern uint32_t AESIntStatus(uint32_t ui32Base, bool bMasked);
extern void AESIntUnregister(uint32_t ui32Base);
extern void AESIVSet(uint32_t ui32Base, uint32_t *pui32IVdata);
extern void AESIVRead(uint32_t ui32Base, uint32_t *pui32IVdata);
extern void AESKey1Set(uint32_t ui32Base, uint32_t *pui32Key,
uint32_t ui32Keysize);
extern void AESKey2Set(uint32_t ui32Base, uint32_t *pui32Key,
uint32_t ui32Keysize);
extern void AESKey3Set(uint32_t ui32Base, uint32_t *pui32Key);
extern void AESLengthSet(uint32_t ui32Base, uint64_t ui64Length);
extern void AESReset(uint32_t ui32Base);
extern void AESTagRead(uint32_t ui32Base, uint32_t *pui32TagData);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_AES_H__
bsp/tm4c123bsp/libraries/TivaWare_C_series/tm4c123_driverlib/driverlib/can.h 0 → 100644
浏览文件 @ aebdcacc
//*****************************************************************************
//
// can.h - Defines and Macros for the CAN controller.
//
// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_CAN_H__
#define __DRIVERLIB_CAN_H__
//*****************************************************************************
//
//! \addtogroup can_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Miscellaneous defines for Message ID Types
//
//*****************************************************************************
//*****************************************************************************
//
// These are the flags used by the tCANMsgObject.ui32Flags value when calling
// the CANMessageSet() and CANMessageGet() functions.
//
//*****************************************************************************
//
//! This indicates that transmit interrupts are enabled.
//
#define MSG_OBJ_TX_INT_ENABLE 0x00000001
//
//! This indicates that receive interrupts are enabled.
//
#define MSG_OBJ_RX_INT_ENABLE 0x00000002
//
//! This indicates that a message object is using an extended identifier.
//
#define MSG_OBJ_EXTENDED_ID 0x00000004
//
//! This indicates that a message object is using filtering based on the
//! object's message identifier.
//
#define MSG_OBJ_USE_ID_FILTER 0x00000008
//
//! This indicates that new data was available in the message object.
//
#define MSG_OBJ_NEW_DATA 0x00000080
//
//! This indicates that data was lost since this message object was last
//! read.
//
#define MSG_OBJ_DATA_LOST 0x00000100
//
//! This indicates that a message object uses or is using filtering
//! based on the direction of the transfer. If the direction filtering is
//! used, then ID filtering must also be enabled.
//
#define MSG_OBJ_USE_DIR_FILTER (0x00000010 | MSG_OBJ_USE_ID_FILTER)
//
//! This indicates that a message object uses or is using message
//! identifier filtering based on the extended identifier. If the extended
//! identifier filtering is used, then ID filtering must also be enabled.
//
#define MSG_OBJ_USE_EXT_FILTER (0x00000020 | MSG_OBJ_USE_ID_FILTER)
//
//! This indicates that a message object is a remote frame.
//
#define MSG_OBJ_REMOTE_FRAME 0x00000040
//
//! This indicates that this message object is part of a FIFO structure and
//! not the final message object in a FIFO.
//
#define MSG_OBJ_FIFO 0x00000200
//
//! This indicates that a message object has no flags set.
//
#define MSG_OBJ_NO_FLAGS 0x00000000
//*****************************************************************************
//
//! This define is used with the flag values to allow checking only status
//! flags and not configuration flags.
//
//*****************************************************************************
#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST)
//*****************************************************************************
//
//! The structure used for encapsulating all the items associated with a CAN
//! message object in the CAN controller.
//
//*****************************************************************************
typedef struct
{
//
//! The CAN message identifier used for 11 or 29 bit identifiers.
//
uint32_t ui32MsgID;
//
//! The message identifier mask used when identifier filtering is enabled.
//
uint32_t ui32MsgIDMask;
//
//! This value holds various status flags and settings specified by
//! tCANObjFlags.
//
uint32_t ui32Flags;
//
//! This value is the number of bytes of data in the message object.
//
uint32_t ui32MsgLen;
//
//! This is a pointer to the message object's data.
//
uint8_t *pui8MsgData;
}
tCANMsgObject;
//*****************************************************************************
//
//! This structure is used for encapsulating the values associated with setting
//! up the bit timing for a CAN controller. The structure is used when calling
//! the CANGetBitTiming and CANSetBitTiming functions.
//
//*****************************************************************************
typedef struct
{
//
//! This value holds the sum of the Synchronization, Propagation, and Phase
//! Buffer 1 segments, measured in time quanta. The valid values for this
//! setting range from 2 to 16.
//
uint32_t ui32SyncPropPhase1Seg;
//
//! This value holds the Phase Buffer 2 segment in time quanta. The valid
//! values for this setting range from 1 to 8.
//
uint32_t ui32Phase2Seg;
//
//! This value holds the Resynchronization Jump Width in time quanta. The
//! valid values for this setting range from 1 to 4.
//
uint32_t ui32SJW;
//
//! This value holds the CAN_CLK divider used to determine time quanta.
//! The valid values for this setting range from 1 to 1023.
//
uint32_t ui32QuantumPrescaler;
}
tCANBitClkParms;
//*****************************************************************************
//
//! This data type is used to identify the interrupt status register. This is
//! used when calling the CANIntStatus() function.
//
//*****************************************************************************
typedef enum
{
//
//! Read the CAN interrupt status information.
//
CAN_INT_STS_CAUSE,
//
//! Read a message object's interrupt status.
//
CAN_INT_STS_OBJECT
}
tCANIntStsReg;
//*****************************************************************************
//
//! This data type is used to identify which of several status registers to
//! read when calling the CANStatusGet() function.
//
//*****************************************************************************
typedef enum
{
//
//! Read the full CAN controller status.
//
CAN_STS_CONTROL,
//
//! Read the full 32-bit mask of message objects with a transmit request
//! set.
//
CAN_STS_TXREQUEST,
//
//! Read the full 32-bit mask of message objects with new data available.
//
CAN_STS_NEWDAT,
//
//! Read the full 32-bit mask of message objects that are enabled.
//
CAN_STS_MSGVAL
}
tCANStsReg;
//*****************************************************************************
//
// These definitions are used to specify interrupt sources to CANIntEnable()
// and CANIntDisable().
//
//*****************************************************************************
//
//! This flag is used to allow a CAN controller to generate error
//! interrupts.
//
#define CAN_INT_ERROR 0x00000008
//
//! This flag is used to allow a CAN controller to generate status
//! interrupts.
//
#define CAN_INT_STATUS 0x00000004
//
//! This flag is used to allow a CAN controller to generate any CAN
//! interrupts. If this is not set, then no interrupts are generated
//! by the CAN controller.
//
#define CAN_INT_MASTER 0x00000002
//*****************************************************************************
//
//! This definition is used to determine the type of message object that is
//! set up via a call to the CANMessageSet() API.
//
//*****************************************************************************
typedef enum
{
//
//! Transmit message object.
//
MSG_OBJ_TYPE_TX,
//
//! Transmit remote request message object
//
MSG_OBJ_TYPE_TX_REMOTE,
//
//! Receive message object.
//
MSG_OBJ_TYPE_RX,
//
//! Receive remote request message object.
//
MSG_OBJ_TYPE_RX_REMOTE,
//
//! Remote frame receive remote, with auto-transmit message object.
//
MSG_OBJ_TYPE_RXTX_REMOTE
}
tMsgObjType;
//*****************************************************************************
//
// The following enumeration contains all error or status indicators that can
// be returned when calling the CANStatusGet() function.
//
//*****************************************************************************
//
//! CAN controller has entered a Bus Off state.
//
#define CAN_STATUS_BUS_OFF 0x00000080
//
//! CAN controller error level has reached warning level.
//
#define CAN_STATUS_EWARN 0x00000040
//
//! CAN controller error level has reached error passive level.
//
#define CAN_STATUS_EPASS 0x00000020
//
//! A message was received successfully since the last read of this status.
//
#define CAN_STATUS_RXOK 0x00000010
//
//! A message was transmitted successfully since the last read of this
//! status.
//
#define CAN_STATUS_TXOK 0x00000008
//
//! This is the mask for the last error code field.
//
#define CAN_STATUS_LEC_MSK 0x00000007
//
//! There was no error.
//
#define CAN_STATUS_LEC_NONE 0x00000000
//
//! A bit stuffing error has occurred.
//
#define CAN_STATUS_LEC_STUFF 0x00000001
//
//! A formatting error has occurred.
//
#define CAN_STATUS_LEC_FORM 0x00000002
//
//! An acknowledge error has occurred.
//
#define CAN_STATUS_LEC_ACK 0x00000003
//
//! The bus remained a bit level of 1 for longer than is allowed.
//
#define CAN_STATUS_LEC_BIT1 0x00000004
//
//! The bus remained a bit level of 0 for longer than is allowed.
//
#define CAN_STATUS_LEC_BIT0 0x00000005
//
//! A CRC error has occurred.
//
#define CAN_STATUS_LEC_CRC 0x00000006
//
//! This is the mask for the CAN Last Error Code (LEC).
//
#define CAN_STATUS_LEC_MASK 0x00000007
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void CANBitTimingGet(uint32_t ui32Base, tCANBitClkParms *psClkParms);
extern void CANBitTimingSet(uint32_t ui32Base, tCANBitClkParms *psClkParms);
extern uint32_t CANBitRateSet(uint32_t ui32Base, uint32_t ui32SourceClock,
uint32_t ui32BitRate);
extern void CANDisable(uint32_t ui32Base);
extern void CANEnable(uint32_t ui32Base);
extern bool CANErrCntrGet(uint32_t ui32Base, uint32_t *pui32RxCount,
uint32_t *pui32TxCount);
extern void CANInit(uint32_t ui32Base);
extern void CANIntClear(uint32_t ui32Base, uint32_t ui32IntClr);
extern void CANIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void CANIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void CANIntRegister(uint32_t ui32Base, void (*pfnHandler)(void));
extern uint32_t CANIntStatus(uint32_t ui32Base, tCANIntStsReg eIntStsReg);
extern void CANIntUnregister(uint32_t ui32Base);
extern void CANMessageClear(uint32_t ui32Base, uint32_t ui32ObjID);
extern void CANMessageGet(uint32_t ui32Base, uint32_t ui32ObjID,
tCANMsgObject *psMsgObject, bool bClrPendingInt);
extern void CANMessageSet(uint32_t ui32Base, uint32_t ui32ObjID,
tCANMsgObject *psMsgObject, tMsgObjType eMsgType);
extern bool CANRetryGet(uint32_t ui32Base);
extern void CANRetrySet(uint32_t ui32Base, bool bAutoRetry);
extern uint32_t CANStatusGet(uint32_t ui32Base, tCANStsReg eStatusReg);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_CAN_H__
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//*****************************************************************************
//
// comp.h - Prototypes for the analog comparator driver.
//
// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_COMP_H__
#define __DRIVERLIB_COMP_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to ComparatorConfigure() as the ui32Config
// parameter. For each group (in other words, COMP_TRIG_xxx, COMP_INT_xxx, and
// so on), one of the values may be selected and combined together with values
// from the other groups via a logical OR.
//
//*****************************************************************************
#define COMP_TRIG_NONE 0x00000000 // No ADC trigger
#define COMP_TRIG_HIGH 0x00000880 // Trigger when high
#define COMP_TRIG_LOW 0x00000800 // Trigger when low
#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge
#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge
#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges
#define COMP_INT_HIGH 0x00000010 // Interrupt when high
#define COMP_INT_LOW 0x00000000 // Interrupt when low
#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge
#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge
#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges
#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin
#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference
#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal
#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted
//*****************************************************************************
//
// Values that can be passed to ComparatorSetRef() as the ui32Ref parameter.
//
//*****************************************************************************
#define COMP_REF_OFF 0x00000000 // Turn off the internal reference
#define COMP_REF_0V 0x00000300 // Internal reference of 0V
#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V
#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V
#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V
#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V
#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V
#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V
#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V
#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V
#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V
#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V
#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V
#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V
#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V
#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V
#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V
#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V
#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V
#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V
#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V
#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V
#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V
#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V
#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V
#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V
#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V
#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V
#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void ComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp,
uint32_t ui32Config);
extern void ComparatorRefSet(uint32_t ui32Base, uint32_t ui32Ref);
extern bool ComparatorValueGet(uint32_t ui32Base, uint32_t ui32Comp);
extern void ComparatorIntRegister(uint32_t ui32Base, uint32_t ui32Comp,
void (*pfnHandler)(void));
extern void ComparatorIntUnregister(uint32_t ui32Base, uint32_t ui32Comp);
extern void ComparatorIntEnable(uint32_t ui32Base, uint32_t ui32Comp);
extern void ComparatorIntDisable(uint32_t ui32Base, uint32_t ui32Comp);
extern bool ComparatorIntStatus(uint32_t ui32Base, uint32_t ui32Comp,
bool bMasked);
extern void ComparatorIntClear(uint32_t ui32Base, uint32_t ui32Comp);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_COMP_H__
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//*****************************************************************************
//
// cpu.h - Prototypes for the CPU instruction wrapper functions.
//
// Copyright (c) 2006-2017 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __DRIVERLIB_CPU_H__
#define __DRIVERLIB_CPU_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern uint32_t CPUcpsid(void);
extern uint32_t CPUcpsie(void);
extern uint32_t CPUprimask(void);
extern void CPUwfi(void);
extern uint32_t CPUbasepriGet(void);
extern void CPUbasepriSet(uint32_t ui32NewBasepri);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_CPU_H__
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