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未验证 提交 ab9a80c4 编写于 作者: wakojosin's avatar wakojosin 提交者： GitHub
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add ra4m2 soc support, add sci spi support for ra4m2 (#6707) 

* add ra4m2 soc support, add sci spi support for ra4m2

* update ra4m2-eco/README.md

* update ra4m2-eco/README.md

* rename board picture name.

* reduce picture size, update README.md, remove file 'Target 1.bat'

* reduce picture size
上级 2e488e04
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Showing with 96585 addition and 14 deletion
bsp/renesas/libraries/HAL_Drivers/SConscript
浏览文件 @ ab9a80c4
......@@ -34,6 +34,7 @@ if GetDepend(['BSP_USING_I2C', 'BSP_USING_HW_I2C']):
if GetDepend(['BSP_USING_SPI']):
src += ['drv_spi.c']
src += ['drv_sci_spi.c']
if GetDepend(['BSP_USING_ADC']):
src += ['drv_adc.c']
......
bsp/renesas/libraries/HAL_Drivers/config/drv_config.h
浏览文件 @ ab9a80c4
......@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2021-07-29 KyleChan first version
* 2022-12-7 Vandoul ADD ra4m2
*/
#ifndef __DRV_CONFIG_H__
......@@ -79,6 +80,26 @@ extern "C"
#endif
#endif /* SOC_SERIES_R7FA2L1 */
#ifdef SOC_SERIES_R7FA4M2
#include "ra4m2/uart_config.h"
#ifdef BSP_USING_ADC
#include "ra4m2/adc_config.h"
#endif
#ifdef BSP_USING_DAC
#include "ra4m2/dac_config.h"
#endif
#ifdef BSP_USING_PWM
#include "ra4m2/pwm_config.h"
#endif
#ifdef BSP_USING_CAN
#include "ra4m2/can_config.h"
#endif
#endif /* SOC_SERIES_R7FA4M2 */
#ifdef __cplusplus
}
#endif
......
bsp/renesas/libraries/HAL_Drivers/config/ra4m2/adc_config.h 0 → 100644
浏览文件 @ ab9a80c4
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-19 Mr.Tiger first version
*/
#ifndef __ADC_CONFIG_H__
#define __ADC_CONFIG_H__
#include <rtthread.h>
#include <rtdevice.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1)
struct ra_adc_map
{
char name;
const adc_cfg_t *g_cfg;
const adc_instance_ctrl_t *g_ctrl;
const adc_channel_cfg_t *g_channel_cfg;
};
struct ra_dev
{
rt_adc_device_t ra_adc_device_t;
struct ra_adc_map *ra_adc_dev;
};
#endif
#endif
#ifdef __cplusplus
}
#endif
bsp/renesas/libraries/HAL_Drivers/config/ra4m2/can_config.h 0 → 100644
浏览文件 @ ab9a80c4
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-29 mazhiyuan first version
*/
#ifndef __CAN_CONFIG_H__
#define __CAN_CONFIG_H__
#include <rtthread.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_CAN0)
#ifndef CAN0_CONFIG
#define CAN0_CONFIG \
{ \
.name = "can0", \
.num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can0, \
.p_api_ctrl = &g_can0_ctrl, \
.p_cfg = &g_can0_cfg, \
}
#endif /* CAN0_CONFIG */
#endif /* BSP_USING_CAN0 */
#if defined(BSP_USING_CAN1)
#ifndef CAN1_CONFIG
#define CAN1_CONFIG \
{ \
.name = "can1", \
.num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can1, \
.p_api_ctrl = &g_can1_ctrl, \
.p_cfg = &g_can1_cfg, \
}
#endif /* CAN1_CONFIG */
#endif /* BSP_USING_CAN1 */
#ifdef __cplusplus
}
#endif
#endif
bsp/renesas/libraries/HAL_Drivers/config/ra4m2/dac_config.h 0 → 100644
浏览文件 @ ab9a80c4
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-19 Mr.Tiger first version
*/
#ifndef __DAC_CONFIG_H__
#define __DAC_CONFIG_H__
#include <rtthread.h>
#include <rtdevice.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_DAC
struct ra_dac_map
{
char name;
const struct st_dac_cfg *g_cfg;
const struct st_dac_instance_ctrl *g_ctrl;
};
struct ra_dac_dev
{
rt_dac_device_t ra_dac_device_t;
struct ra_dac_map *ra_dac_map_dev;
};
#endif
#endif
#ifdef __cplusplus
}
#endif
bsp/renesas/libraries/HAL_Drivers/config/ra4m2/pwm_config.h 0 → 100644
浏览文件 @ ab9a80c4
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-26 KevinXu first version
*/
#ifndef __PWM_CONFIG_H__
#define __PWM_CONFIG_H__
#include <rtthread.h>
#include <drv_config.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
enum
{
#ifdef BSP_USING_PWM0
BSP_PWM0_INDEX,
#endif
#ifdef BSP_USING_PWM1
BSP_PWM1_INDEX,
#endif
#ifdef BSP_USING_PWM2
BSP_PWM2_INDEX,
#endif
#ifdef BSP_USING_PWM3
BSP_PWM3_INDEX,
#endif
#ifdef BSP_USING_PWM4
BSP_PWM4_INDEX,
#endif
#ifdef BSP_USING_PWM5
BSP_PWM5_INDEX,
#endif
#ifdef BSP_USING_PWM6
BSP_PWM6_INDEX,
#endif
#ifdef BSP_USING_PWM7
BSP_PWM7_INDEX,
#endif
#ifdef BSP_USING_PWM8
BSP_PWM8_INDEX,
#endif
#ifdef BSP_USING_PWM9
BSP_PWM9_INDEX,
#endif
BSP_PWMS_NUM
};
#define PWM_DRV_INITIALIZER(num) \
{ \
.name = "pwm"#num , \
.g_cfg = &g_timer##num##_cfg, \
.g_ctrl = &g_timer##num##_ctrl, \
.g_timer = &g_timer##num, \
}
#ifdef __cplusplus
}
#endif
#endif /* __PWM_CONFIG_H__ */
bsp/renesas/libraries/HAL_Drivers/config/ra4m2/uart_config.h 0 → 100644
浏览文件 @ ab9a80c4
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-07-29 KyleChan first version
*/
#ifndef __UART_CONFIG_H__
#define __UART_CONFIG_H__
#include <rtthread.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(BSP_USING_UART0)
#ifndef UART0_CONFIG
#define UART0_CONFIG \
{ \
.name = "uart0", \
.p_api_ctrl = &g_uart0_ctrl, \
.p_cfg = &g_uart0_cfg, \
}
#endif /* UART0_CONFIG */
#endif /* BSP_USING_UART0 */
#if defined(BSP_USING_UART1)
#ifndef UART1_CONFIG
#define UART1_CONFIG \
{ \
.name = "uart1", \
.p_api_ctrl = &g_uart1_ctrl, \
.p_cfg = &g_uart1_cfg, \
}
#endif /* UART1_CONFIG */
#endif /* BSP_USING_UART1 */
#if defined(BSP_USING_UART2)
#ifndef UART2_CONFIG
#define UART2_CONFIG \
{ \
.name = "uart2", \
.p_api_ctrl = &g_uart2_ctrl, \
.p_cfg = &g_uart2_cfg, \
}
#endif /* UART2_CONFIG */
#endif /* BSP_USING_UART2 */
#if defined(BSP_USING_UART3)
#ifndef UART3_CONFIG
#define UART3_CONFIG \
{ \
.name = "uart3", \
.p_api_ctrl = &g_uart3_ctrl, \
.p_cfg = &g_uart3_cfg, \
}
#endif /* UART3_CONFIG */
#endif /* BSP_USING_UART3 */
#if defined(BSP_USING_UART4)
#ifndef UART4_CONFIG
#define UART4_CONFIG \
{ \
.name = "uart4", \
.p_api_ctrl = &g_uart4_ctrl, \
.p_cfg = &g_uart4_cfg, \
}
#endif /* UART4_CONFIG */
#endif /* BSP_USING_UART4 */
#if defined(BSP_USING_UART5)
#ifndef UART5_CONFIG
#define UART5_CONFIG \
{ \
.name = "uart5", \
.p_api_ctrl = &g_uart5_ctrl, \
.p_cfg = &g_uart5_cfg, \
}
#endif /* UART5_CONFIG */
#endif /* BSP_USING_UART5 */
#if defined(BSP_USING_UART6)
#ifndef UART6_CONFIG
#define UART6_CONFIG \
{ \
.name = "uart6", \
.p_api_ctrl = &g_uart6_ctrl, \
.p_cfg = &g_uart6_cfg, \
}
#endif /* UART6_CONFIG */
#endif /* BSP_USING_UART6 */
#if defined(BSP_USING_UART7)
#ifndef UART7_CONFIG
#define UART7_CONFIG \
{ \
.name = "uart7", \
.p_api_ctrl = &g_uart7_ctrl, \
.p_cfg = &g_uart7_cfg, \
}
#endif /* UART7_CONFIG */
#endif /* BSP_USING_UART7 */
#if defined(BSP_USING_UART8)
#ifndef UART8_CONFIG
#define UART8_CONFIG \
{ \
.name = "uart8", \
.p_api_ctrl = &g_uart8_ctrl, \
.p_cfg = &g_uart8_cfg, \
}
#endif /* UART8_CONFIG */
#endif /* BSP_USING_UART8 */
#if defined(BSP_USING_UART9)
#ifndef UART9_CONFIG
#define UART9_CONFIG \
{ \
.name = "uart9", \
.p_api_ctrl = &g_uart9_ctrl, \
.p_cfg = &g_uart9_cfg, \
}
#endif /* UART9_CONFIG */
#endif /* BSP_USING_UART9 */
#ifdef __cplusplus
}
#endif
#endif
bsp/renesas/libraries/HAL_Drivers/drv_sci_spi.c 0 → 100644
浏览文件 @ ab9a80c4
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-23 Mr.Tiger first version
* 2021-11-04 Sherman ADD complete_event
* 2022-12-7 Vandoul ADD sci spi
*/
/**< Note : Turn on any DMA mode and all SPIs will turn on DMA */
#include "drv_sci_spi.h"
#ifdef RT_USING_SPI
//#define DRV_DEBUG
#define DBG_TAG "drv.scispi"
#ifdef DRV_DEBUG
#define DBG_LVL DBG_LOG
#else
#define DBG_LVL DBG_INFO
#endif /* DRV_DEBUG */
#include <rtdbg.h>
#define RA_SCI_SPI0_EVENT 0x0001
#define RA_SCI_SPI1_EVENT 0x0002
#define RA_SCI_SPI2_EVENT 0x0004
#define RA_SCI_SPI3_EVENT 0x0008
#define RA_SCI_SPI4_EVENT 0x0010
#define RA_SCI_SPI5_EVENT 0x0020
#define RA_SCI_SPI6_EVENT 0x0040
#define RA_SCI_SPI7_EVENT 0x0080
#define RA_SCI_SPI8_EVENT 0x0100
#define RA_SCI_SPI9_EVENT 0x0200
static struct rt_event complete_event = {0};
static struct ra_sci_spi_handle spi_handle[] =
{
#ifdef BSP_USING_SCI_SPI0
{.bus_name = "scpi0", .spi_ctrl_t = &g_sci_spi0_ctrl, .spi_cfg_t = &g_sci_spi0_cfg,},
#endif
#ifdef BSP_USING_SCI_SPI1
{.bus_name = "scpi1", .spi_ctrl_t = &g_sci_spi1_ctrl, .spi_cfg_t = &g_sci_spi1_cfg,},
#endif
#ifdef BSP_USING_SCI_SPI2
{.bus_name = "scpi2", .spi_ctrl_t = &g_sci_spi2_ctrl, .spi_cfg_t = &g_sci_spi2_cfg,},
#endif
#ifdef BSP_USING_SCI_SPI3
{.bus_name = "scpi3", .spi_ctrl_t = &g_sci_spi3_ctrl, .spi_cfg_t = &g_sci_spi3_cfg,},
#endif
#ifdef BSP_USING_SCI_SPI4
{.bus_name = "scpi4", .spi_ctrl_t = &g_sci_spi4_ctrl, .spi_cfg_t = &g_sci_spi4_cfg,},
#endif
#ifdef BSP_USING_SCI_SPI5
{.bus_name = "scpi5", .spi_ctrl_t = &g_sci_spi5_ctrl, .spi_cfg_t = &g_sci_spi5_cfg,},
#endif
#ifdef BSP_USING_SCI_SPI6
{.bus_name = "scpi6", .spi_ctrl_t = &g_sci_spi6_ctrl, .spi_cfg_t = &g_sci_spi6_cfg,},
#endif
#ifdef BSP_USING_SCI_SPI7
{.bus_name = "scpi7", .spi_ctrl_t = &g_sci_spi7_ctrl, .spi_cfg_t = &g_sci_spi7_cfg,},
#endif
#ifdef BSP_USING_SCI_SPI8
{.bus_name = "scpi8", .spi_ctrl_t = &g_sci_spi8_ctrl, .spi_cfg_t = &g_sci_spi8_cfg,},
#endif
#ifdef BSP_USING_SCI_SPI9
{.bus_name = "scpi9", .spi_ctrl_t = &g_sci_spi9_ctrl, .spi_cfg_t = &g_sci_spi9_cfg,},
#endif
};
static struct ra_sci_spi spi_config[sizeof(spi_handle) / sizeof(spi_handle[0])] = {0};
#define SCI_SPIx_CALLBACK(n) \
void sci_spi##n##_callback(spi_callback_args_t *p_args) \
{ \
rt_interrupt_enter(); \
if (SPI_EVENT_TRANSFER_COMPLETE == p_args->event) \
{ \
rt_event_send(&complete_event, RA_SCI_SPI##n##_EVENT); \
} \
rt_interrupt_leave(); \
}
SCI_SPIx_CALLBACK(0);
SCI_SPIx_CALLBACK(1);
SCI_SPIx_CALLBACK(2);
SCI_SPIx_CALLBACK(3);
SCI_SPIx_CALLBACK(4);
SCI_SPIx_CALLBACK(5);
SCI_SPIx_CALLBACK(6);
SCI_SPIx_CALLBACK(7);
SCI_SPIx_CALLBACK(8);
SCI_SPIx_CALLBACK(9);
#define SCI_SPIx_EVENT_RECV(n) \
rt_event_recv(event, \
RA_SCI_SPI##n##_EVENT, \
RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, \
RT_WAITING_FOREVER, \
&recved);
static rt_err_t ra_wait_complete(rt_event_t event, const char bus_name[RT_NAME_MAX])
{
rt_uint32_t recved = 0x00;
switch (bus_name[6])
{
case '0':
return SCI_SPIx_EVENT_RECV(0);
case '1':
return SCI_SPIx_EVENT_RECV(1);
case '2':
return SCI_SPIx_EVENT_RECV(2);
case '3':
return SCI_SPIx_EVENT_RECV(3);
case '4':
return SCI_SPIx_EVENT_RECV(4);
case '5':
return SCI_SPIx_EVENT_RECV(5);
case '6':
return SCI_SPIx_EVENT_RECV(6);
case '7':
return SCI_SPIx_EVENT_RECV(7);
case '8':
return SCI_SPIx_EVENT_RECV(8);
case '9':
return SCI_SPIx_EVENT_RECV(9);
}
return -RT_EINVAL;
}
static spi_bit_width_t ra_width_shift(rt_uint8_t data_width)
{
spi_bit_width_t bit_width = SPI_BIT_WIDTH_8_BITS;
if(data_width == 1)
bit_width = SPI_BIT_WIDTH_8_BITS;
else if(data_width == 2)
bit_width = SPI_BIT_WIDTH_16_BITS;
else if(data_width == 4)
bit_width = SPI_BIT_WIDTH_32_BITS;
return bit_width;
}
static rt_err_t ra_write_message(struct rt_spi_device *device, const void *send_buf, const rt_size_t len)
{
RT_ASSERT(device != NULL);
RT_ASSERT(device->parent.user_data != NULL);
RT_ASSERT(send_buf != NULL);
RT_ASSERT(len > 0);
rt_err_t err = RT_EOK;
struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
/**< send msessage */
err = R_SCI_SPI_Write((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, send_buf, len, bit_width);
if (RT_EOK != err)
{
LOG_E("%s write failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
return -RT_ERROR;
}
/* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
return len;
}
static rt_err_t ra_read_message(struct rt_spi_device *device, void *recv_buf, const rt_size_t len)
{
RT_ASSERT(device != NULL);
RT_ASSERT(device->parent.user_data != NULL);
RT_ASSERT(recv_buf != NULL);
RT_ASSERT(len > 0);
rt_err_t err = RT_EOK;
struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
/**< receive message */
err = R_SCI_SPI_Read((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, recv_buf, len, bit_width);
if (RT_EOK != err)
{
LOG_E("%s write failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
return -RT_ERROR;
}
/* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
return len;
}
static rt_err_t ra_write_read_message(struct rt_spi_device *device, struct rt_spi_message *message)
{
RT_ASSERT(device != NULL);
RT_ASSERT(message != NULL);
RT_ASSERT(message->length > 0);
rt_err_t err = RT_EOK;
struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
/**< write and receive message */
err = R_SCI_SPI_WriteRead((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, message->send_buf, message->recv_buf, message->length, bit_width);
if (RT_EOK != err)
{
LOG_E("%s write and read failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
return -RT_ERROR;
}
/* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
return message->length;
}
/**< init spi TODO : MSB does not support modification */
static rt_err_t ra_hw_spi_configure(struct rt_spi_device *device,
struct rt_spi_configuration *configuration)
{
RT_ASSERT(device != NULL);
RT_ASSERT(configuration != NULL);
rt_err_t err = RT_EOK;
struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
spi_dev->cs_pin = (rt_uint32_t)device->parent.user_data;
/**< data_width : 1 -> 8 bits , 2 -> 16 bits, 4 -> 32 bits, default 32 bits*/
rt_uint8_t data_width = configuration->data_width / 8;
RT_ASSERT(data_width == 1 || data_width == 2 || data_width == 4);
configuration->data_width = configuration->data_width / 8;
spi_dev->rt_spi_cfg_t = configuration;
sci_spi_extended_cfg_t *spi_cfg = (sci_spi_extended_cfg_t *)spi_dev->ra_spi_handle_t->spi_cfg_t->p_extend;
/**< Configure Select Line */
rt_pin_write(spi_dev->cs_pin, PIN_HIGH);
/**< config bitrate */
R_SCI_SPI_CalculateBitrate(spi_dev->rt_spi_cfg_t->max_hz, &spi_cfg->clk_div, false);
/**< init */
err = R_SCI_SPI_Open((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, (spi_cfg_t const * const)spi_dev->ra_spi_handle_t->spi_cfg_t);
/* handle error */
if(err == FSP_ERR_IN_USE) {
R_SCI_SPI_Close((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t);
err = R_SCI_SPI_Open((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, (spi_cfg_t const * const)spi_dev->ra_spi_handle_t->spi_cfg_t);
}
if (RT_EOK != err)
{
LOG_E("%s init failed. %d", spi_dev->ra_spi_handle_t->bus_name, err);
return -RT_ERROR;
}
return RT_EOK;
}
static rt_uint32_t ra_spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
{
RT_ASSERT(device != RT_NULL);
RT_ASSERT(device->bus != RT_NULL);
RT_ASSERT(message != RT_NULL);
rt_err_t err = RT_EOK;
struct ra_sci_spi *spi_dev = rt_container_of(device->bus, struct ra_sci_spi, bus);
spi_dev->cs_pin = (rt_uint32_t)device->parent.user_data;
if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS))
{
if (device->config.mode & RT_SPI_CS_HIGH)
rt_pin_write(spi_dev->cs_pin, PIN_HIGH);
else
rt_pin_write(spi_dev->cs_pin, PIN_LOW);
}
if (message->length > 0)
{
if (message->send_buf == RT_NULL && message->recv_buf != RT_NULL)
{
/**< receive message */
err = ra_read_message(device, (void *)message->recv_buf, (const rt_size_t)message->length);
}
else if (message->send_buf != RT_NULL && message->recv_buf == RT_NULL)
{
/**< send message */
err = ra_write_message(device, (const void *)message->send_buf, (const rt_size_t)message->length);
}
else if (message->send_buf != RT_NULL && message->recv_buf != RT_NULL)
{
/**< send and receive message */
err = ra_write_read_message(device, message);
}
}
if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS))
{
if (device->config.mode & RT_SPI_CS_HIGH)
rt_pin_write(spi_dev->cs_pin, PIN_LOW);
else
rt_pin_write(spi_dev->cs_pin, PIN_HIGH);
}
return err;
}
static const struct rt_spi_ops ra_spi_ops =
{
.configure = ra_hw_spi_configure,
.xfer = ra_spixfer,
};
int ra_hw_sci_spi_init(void)
{
for (rt_uint8_t spi_index = 0; spi_index < sizeof(spi_handle) / sizeof(spi_handle[0]); spi_index++)
{
spi_config[spi_index].ra_spi_handle_t = &spi_handle[spi_index];
/**< register spi bus */
rt_err_t err = rt_spi_bus_register(&spi_config[spi_index].bus, spi_handle[spi_index].bus_name, &ra_spi_ops);
if (RT_EOK != err)
{
LOG_E("%s bus register failed. %d", spi_config[spi_index].ra_spi_handle_t->bus_name, err);
return -RT_ERROR;
}
}
if (RT_EOK != rt_event_init(&complete_event, "ra_scispi", RT_IPC_FLAG_PRIO))
{
LOG_E("SPI transfer event init fail!");
return -RT_ERROR;
}
return RT_EOK;
}
INIT_BOARD_EXPORT(ra_hw_sci_spi_init);
#endif /* RT_USING_SPI */
bsp/renesas/libraries/HAL_Drivers/drv_sci_spi.h 0 → 100644
浏览文件 @ ab9a80c4
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-23 Mr.Tiger first version
* 2022-12-7 Vandoul ADD sci spi
*/
#ifndef __DRV_SCI_SPI_H__
#define __DRV_SCI_SPI_H__
#include <rtthread.h>
#include <rtdevice.h>
#include "hal_data.h"
#include "board.h"
#include <rthw.h>
#include <drv_common.h>
#include <drv_config.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef R_SCI_SPI_H
struct ra_sci_spi_handle
{
const char bus_name[RT_NAME_MAX];
const spi_cfg_t *spi_cfg_t;
const sci_spi_instance_ctrl_t *spi_ctrl_t;
};
struct ra_sci_spi
{
rt_uint32_t cs_pin;
struct ra_sci_spi_handle *ra_spi_handle_t;
struct rt_spi_configuration *rt_spi_cfg_t;
struct rt_spi_bus bus;
};
#endif
#ifdef __cplusplus
}
#endif
/* stm32 spi dirver class */
#endif /*__DRV_SPI_H__ */
bsp/renesas/libraries/HAL_Drivers/drv_spi.c
浏览文件 @ ab9a80c4
......@@ -7,6 +7,7 @@
* Date Author Notes
* 2021-08-23 Mr.Tiger first version
* 2021-11-04 Sherman ADD complete_event
* 2022-12-7 Vandoul ADD sci spi support
*/
/**< Note : Turn on any DMA mode and all SPIs will turn on DMA */
......@@ -23,6 +24,7 @@
#endif /* DRV_DEBUG */
#include <rtdbg.h>
#if defined(BSP_USING_SPI0) || defined(BSP_USING_SPI1)
#define RA_SPI0_EVENT 0x00
#define RA_SPI1_EVENT 0x01
static struct rt_event complete_event = {0};
......@@ -250,20 +252,6 @@ static const struct rt_spi_ops ra_spi_ops =
.xfer = ra_spixfer,
};
void rt_hw_spi_device_attach(struct rt_spi_device *device, const char *device_name, const char *bus_name, void *user_data)
{
RT_ASSERT(device != NULL);
RT_ASSERT(device_name != NULL);
RT_ASSERT(bus_name != NULL);
RT_ASSERT(user_data != NULL);
rt_err_t err = rt_spi_bus_attach_device(device, device_name, bus_name, user_data);
if (RT_EOK != err)
{
LOG_E("%s attach failed.", bus_name);
}
}
int ra_hw_spi_init(void)
{
for (rt_uint8_t spi_index = 0; spi_index < sizeof(spi_handle) / sizeof(spi_handle[0]); spi_index++)
......@@ -287,4 +275,18 @@ int ra_hw_spi_init(void)
return RT_EOK;
}
INIT_BOARD_EXPORT(ra_hw_spi_init);
#endif
void rt_hw_spi_device_attach(struct rt_spi_device *device, const char *device_name, const char *bus_name, void *user_data)
{
RT_ASSERT(device != NULL);
RT_ASSERT(device_name != NULL);
RT_ASSERT(bus_name != NULL);
RT_ASSERT(user_data != NULL);
rt_err_t err = rt_spi_bus_attach_device(device, device_name, bus_name, user_data);
if (RT_EOK != err)
{
LOG_E("%s attach failed.", bus_name);
}
}
#endif /* RT_USING_SPI */
bsp/renesas/libraries/Kconfig
浏览文件 @ ab9a80c4
......@@ -25,4 +25,10 @@ config SOC_SERIES_R7FA6M5
bool
select ARCH_ARM_CORTEX_M33
select SOC_FAMILY_RENESAS
default n
config SOC_SERIES_R7FA4M2
bool
select ARCH_ARM_CORTEX_M4
select SOC_FAMILY_RENESAS
default n
\ No newline at end of file
bsp/renesas/ra4m2-eco/.api_xml 0 → 100644
浏览文件 @ ab9a80c4
<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<ddscApi/>
bsp/renesas/ra4m2-eco/.config 0 → 100644
浏览文件 @ ab9a80c4
此差异已折叠。
bsp/renesas/ra4m2-eco/.gitignore 0 → 100644
浏览文件 @ ab9a80c4
/RTE
/Listings
/Objects
/build
ra_cfg.txt
.config.old
*.uvguix.*
Target 1.BAT
bsp/renesas/ra4m2-eco/.ignore_format.yml 0 → 100644
浏览文件 @ ab9a80c4
# files format check exclude path, please follow the instructions below to modify;
# If you need to exclude an entire folder, add the folder path in dir_path;
# If you need to exclude a file, add the path to the file in file_path.
dir_path:
- ra
- ra_gen
- ra_cfg
- RTE
bsp/renesas/ra4m2-eco/.secure_azone 0 → 100644
浏览文件 @ ab9a80c4
<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<azone>
<rzone name="R7FA4M2AD3CFP.rzone"/>
<partition>
<peripheral name="PORT1" group="PORT">
<slot name="P100" secure="false"/>
<slot name="P101" secure="false"/>
<slot name="P108" secure="false"/>
</peripheral>
<peripheral name="PORT2" group="PORT">
<slot name="P206" secure="false"/>
<slot name="P207" secure="false"/>
</peripheral>
<peripheral name="PORT3" group="PORT">
<slot name="P300" secure="false"/>
</peripheral>
<peripheral name="PORT6" group="PORT">
<slot name="P600" secure="false"/>
<slot name="P601" secure="false"/>
<slot name="P602" secure="false"/>
<slot name="P603" secure="false"/>
</peripheral>
<peripheral name="SCI0" group="SCI" security=""/>
<peripheral name="SCI4" group="SCI" security=""/>
<peripheral name="SCI9" group="SCI" security=""/>
<peripheral name="ICU">
<slot name="IRQ0" secure="false"/>
<slot name="IRQ1" secure="false"/>
<slot name="IRQ2" secure="false"/>
<slot name="IRQ3" secure="false"/>
<slot name="IRQ4" secure="false"/>
<slot name="IRQ5" secure="false"/>
<slot name="IRQ6" secure="false"/>
<slot name="IRQ7" secure="false"/>
<slot name="IRQ8" secure="false"/>
<slot name="IRQ9" secure="false"/>
<slot name="IRQ10" secure="false"/>
<slot name="IRQ11" secure="false"/>
</peripheral>
</partition>
</azone>
bsp/renesas/ra4m2-eco/.secure_xml 0 → 100644
浏览文件 @ ab9a80c4
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<raConfiguration version="7">
<generalSettings>
<option key="#Board#" value="board.custom"/>
<option key="CPU" value="RA4M2"/>
<option key="Core" value="CM33"/>
<option key="#TargetName#" value="R7FA4M2AD3CFP"/>
<option key="#TargetARCHITECTURE#" value="cortex-m33"/>
<option key="#DeviceCommand#" value="R7FA4M2AD"/>
<option key="#RTOS#" value="_none"/>
<option key="#pinconfiguration#" value="R7FA4M2AD3CFP.pincfg"/>
<option key="#FSPVersion#" value="4.1.0"/>
<option key="#SELECTED_TOOLCHAIN#" value="com.arm.toolchain"/>
</generalSettings>
<raClockConfiguration>
<node id="board.clock.xtal.freq" mul="24000000" option="_edit"/>
<node id="board.clock.hoco.freq" option="board.clock.hoco.freq.20m"/>
<node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
<node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
<node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
<node id="board.clock.pll.source" option="board.clock.pll.source.xtal"/>
<node id="board.clock.pll.div" option="board.clock.pll.div.3"/>
<node id="board.clock.pll.mul" option="board.clock.pll.mul.250"/>
<node id="board.clock.pll.display" option="board.clock.pll.display.value"/>
<node id="board.clock.pll2.source" option="board.clock.pll2.source.disabled"/>
<node id="board.clock.pll2.div" option="board.clock.pll2.div.2"/>
<node id="board.clock.pll2.mul" option="board.clock.pll2.mul.200"/>
<node id="board.clock.pll2.display" option="board.clock.pll2.display.value"/>
<node id="board.clock.clock.source" option="board.clock.clock.source.pll"/>
<node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
<node id="board.clock.uclk.source" option="board.clock.uclk.source.disabled"/>
<node id="board.clock.iclk.div" option="board.clock.iclk.div.2"/>
<node id="board.clock.pclka.div" option="board.clock.pclka.div.2"/>
<node id="board.clock.pclkb.div" option="board.clock.pclkb.div.4"/>
<node id="board.clock.pclkc.div" option="board.clock.pclkc.div.4"/>
<node id="board.clock.pclkd.div" option="board.clock.pclkd.div.2"/>
<node id="board.clock.fclk.div" option="board.clock.fclk.div.4"/>
<node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
<node id="board.clock.uclk.div" option="board.clock.uclk.div.5"/>
<node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
<node id="board.clock.pclka.display" option="board.clock.pclka.display.value"/>
<node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
<node id="board.clock.pclkc.display" option="board.clock.pclkc.display.value"/>
<node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
<node id="board.clock.fclk.display" option="board.clock.fclk.display.value"/>
<node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
<node id="board.clock.uclk.display" option="board.clock.uclk.display.value"/>
</raClockConfiguration>
<raModuleConfiguration/>
<raPinConfiguration>
<pincfg active="true" name="" symbol="">
<configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk" isUsedByDriver="true"/>
<configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio" isUsedByDriver="true"/>
<configSetting altId="p603.output.high" configurationId="p603"/>
<configSetting altId="sci0.rxd.p100" configurationId="sci0.rxd" isUsedByDriver="true"/>
<configSetting altId="sci0.txd.p101" configurationId="sci0.txd" isUsedByDriver="true"/>
<configSetting altId="sci4.rxd.p206" configurationId="sci4.rxd" isUsedByDriver="true"/>
<configSetting altId="sci4.txd.p207" configurationId="sci4.txd" isUsedByDriver="true"/>
<configSetting altId="sci9.rxd.p601" configurationId="sci9.rxd" isUsedByDriver="true"/>
<configSetting altId="sci9.sck.p600" configurationId="sci9.sck" isUsedByDriver="true"/>
<configSetting altId="sci9.txd.p602" configurationId="sci9.txd" isUsedByDriver="true"/>
</pincfg>
</raPinConfiguration>
</raConfiguration>
bsp/renesas/ra4m2-eco/.settings/standalone.prefs 0 → 100644
浏览文件 @ ab9a80c4
#Wed Dec 07 23:22:04 CST 2022
com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths=ra/arm
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#\#\#4.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#\#\#4.1.0/all=3347489174,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#4.1.0/all=500387124,ra/fsp/src/r_ioport/r_ioport.c|2537229576,ra/fsp/inc/api/r_ioport_api.h|2490905981,ra/fsp/inc/instances/r_ioport.h
com.renesas.cdt.ddsc.project.standalone.projectgenerationoptions/isCpp=true
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.4.1.0/all=3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3778515955,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|1924015782,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|4147548732,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|2675617387,ra/arm/CMSIS_5/CMSIS/Core/Include/core_starmc1.h|1480183821,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|1290634672,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|1438162915,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|1608305587,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm85.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|4084823319,ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#fsp\#\#\#\#4.1.0/all=545907899,ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h|2766481316,ra/fsp/src/bsp/mcu/ra4m2/bsp_elc.h|1942810345,ra/fsp/src/bsp/mcu/ra4m2/bsp_mcu_info.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#4.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.9.0+renesas.0.fsp.4.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_spi\#\#\#\#4.1.0/libraries=
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.spi_on_sci_spi.342272802=false
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.788093718=false
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_dtc\#\#\#\#4.1.0/all=2970687511,ra/fsp/inc/api/r_transfer_api.h|428353588,ra/fsp/inc/instances/r_dtc.h|1071048478,ra/fsp/src/r_dtc/r_dtc.c
com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#4.1.0/all=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#fsp\#\#\#\#4.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#R7FA4M2AD3CFP\#\#4.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#4.1.0/all=3958601320,ra/fsp/inc/instances/r_sci_uart.h|2970687511,ra/fsp/inc/api/r_transfer_api.h|134969800,ra/fsp/inc/api/r_uart_api.h|2640391634,ra/fsp/src/r_sci_uart/r_sci_uart.c
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#4.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_spi\#\#\#\#4.1.0/all=2999473418,ra/fsp/src/r_sci_spi/r_sci_spi.c|2970687511,ra/fsp/inc/api/r_transfer_api.h|2516469150,ra/fsp/inc/api/r_spi_api.h|57267461,ra/fsp/inc/instances/r_sci_spi.h
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#custom\#\#\#\#4.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra4m2\#\#device\#\#R7FA4M2AD3CFP\#\#4.1.0/all=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_dtc\#\#\#\#4.1.0/libraries=
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#4.1.0/all=2136566490,ra/fsp/src/bsp/mcu/all/bsp_guard.h|1564775820,ra/fsp/src/bsp/mcu/all/bsp_security.h|2222043441,ra/fsp/src/bsp/mcu/all/bsp_irq.c|1844233273,ra/fsp/src/bsp/mcu/all/bsp_common.c|1844682318,ra/fsp/src/bsp/mcu/all/bsp_io.h|502753616,ra/fsp/src/bsp/mcu/all/bsp_irq.h|2635614327,ra/fsp/src/bsp/mcu/all/bsp_security.c|2537229576,ra/fsp/inc/api/r_ioport_api.h|1799272679,ra/fsp/inc/fsp_features.h|805765460,ra/fsp/src/bsp/mcu/all/bsp_delay.c|2015535075,ra/fsp/inc/fsp_common_api.h|2461896614,ra/fsp/src/bsp/mcu/all/bsp_io.c|175812246,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|2854226690,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|29339077,ra/fsp/inc/fsp_version.h|547852917,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|604332916,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|2074918554,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|371081032,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|1303542530,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|571584658,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|2922574965,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|2906265047,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|1218854983,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3954882015,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|715820739,ra/fsp/inc/api/bsp_api.h|539993079,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1374997543,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|3748852695,ra/fsp/src/bsp/mcu/all/bsp_delay.h|3299517248,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|2294599662,ra/fsp/src/bsp/mcu/all/bsp_common.h|3035603422,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|2644177141,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|2273123320,ra/fsp/src/bsp/mcu/all/bsp_guard.c|2490905981,ra/fsp/inc/instances/r_ioport.h
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.1802976382=false
com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#4.1.0/libraries=
bsp/renesas/ra4m2-eco/JLinkSettings.JLinkScript 0 → 100644
浏览文件 @ ab9a80c4
/***********************************************************************
* This file was automatically generated by RASC
*
* J-Link script file to change the device being used for a debug
* session. This is required when the RA MCU being debugged is in
* NSECSD device life-cycle state, when the normal flash driver mechanism
* cannot be used as the use of RAM on the target MCU is not permitted.
* This means an alternate, but slower, flash driver mechanism is
* required, which makes no use of target RAM. This alternate mechanism
* is enabled through the use of device names post-pended with "_RAMLess".
*
* To use normal flash driver:
* => Set _USE_RAMLESS_FLASH_DRIVER to 0.
*
* To use slower, alternate flash driver:
* => Set _USE_RAMLESS_FLASH_DRIVER to 1.
*
* Note that the "_RAMLess" device name specified in the call to
* JLINK_SetDevice() must match the actual target device.
***********************************************************************/
__constant U32 _USE_RAMLESS_FLASH_DRIVER = 0;
int ConfigTargetSettings(void) {
if (_USE_RAMLESS_FLASH_DRIVER != 0) {
JLINK_SYS_Report("J-Link script: ConfigTargetSettings()");
JLINK_SYS_Report("Setting Device for flash driver that requires no RAM");
// Ensure below device matches your target MCU (but with _RAMLess added)
JLINK_SetDevice("R7FA4M2AD_RAMLess");
}
return 0;
}
bsp/renesas/ra4m2-eco/Kconfig 0 → 100644
浏览文件 @ ab9a80c4
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
# you can change the RTT_ROOT default "../.." to your rtthread_root,
# example : default "F:/git_repositories/rt-thread"
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
config ENV_DIR
string
option env="ENV_ROOT"
default "/"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "../libraries/Kconfig"
source "$BSP_DIR/board/Kconfig"
bsp/renesas/ra4m2-eco/README.md 0 → 100644
浏览文件 @ ab9a80c4
# 瑞萨 CPK-RA6M4 开发板 BSP 说明
## 简介
本文档为瑞萨 RA-Eco-RA4M2-100PIN 开发板提供的 BSP (板级支持包) 说明。通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
主要内容如下：
- 开发板介绍
- BSP 快速上手指南
## 开发板介绍
基于瑞萨 RA4M2 MCU 开发的 RA-Eco-RA4M2-100PIN 评估板，通过灵活配置软件包和 IDE，可帮助用户对 RA4M2 MCU 群组的特性轻松进行评估，并对嵌入系统应用程序进行开发。
开发板正面外观如下图：
![image-20221208102517429](docs/pictures/eco-ra4m2.jpg)
该开发板常用 **板载资源** 如下：
- MCU：R7FA4M2AD3CFB，100MHz，Arm Cortex®-M33 内核，512kB 代码闪存, 128kB SRAM
- 调试接口：板载 SWD 接口
- 扩展接口：两个 PMOD 连接器，Arduino Uno接口
**更多详细资料及工具**
## 外设支持
本 BSP 目前对外设的支持情况如下：
| **片上外设** | **支持情况** | **备注** |
| :----------------- | :----------------- | :------------- |
| UART | 支持 | UART9 为默认日志输出端口 |
| GPIO | 支持 | |
| SPI | 支持 | |
| 持续更新中... | | |
| **外接外设** | **支持情况** | **备注** |
| 暂无 | 支持 | |
## 使用说明
使用说明分为如下两个章节：
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
### 快速上手
本 BSP 目前仅提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
**硬件连接**
使用 USB 数据线连接开发板(串口)到 PC，使用下载器连接SWD排针和 DEBUG 程序。使用 USB 转串口工具连接 UART9：P109(TXD)、P110(RXD)。
**编译下载**
- 编译：双击 project.uvprojx 文件，打开 MDK5 工程，编译程序。
> 注意：此工程需要使用 J-Flash Lite 工具烧录程序。建议使用 V7.50 及以上版本烧录工程。[J-Link 下载链接](https://www.segger.com/downloads/jlink/)
- 下载：打开 J-Flash lite 工具，选择芯片型号 R7FA4M2AD，点击 OK 进入工具。选择 BSP 目录下 MDK 编译出的 /object/rtthread.hex 文件，点击 Program Device 按钮开始烧录。
**查看运行结果**
下载程序成功之后，系统会自动运行并打印系统信息。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息。输入 help 命令可查看系统中支持的命令。
```bash
\ | /
- RT - Thread Operating System
/ | \ 4.0.4 build Oct 11 2021
2006 - 2021 Copyright by rt-thread team
Hello RT-Thread!
msh >
msh >help
RT-Thread shell commands:
reboot - Reboot System
help - RT - Thread shell help.
ps - List threads in the system.
free - Show the memory usage in the system.
hello - say hello world
clear - clear the terminal screen
version - show RT - Thread version information
list_thread - list thread
list_sem - list semaphore in system
list_event - list event in system
list_mutex - list mutex in system
list_mailbox - list mail box in system
list_msgqueue - list message queue in system
list_timer - list timer in system
list_device - list device in system
list - list all commands in system
msh >
```
**应用入口函数**
应用层的入口函数在 **bsp\ra6m4-cpk\src\hal_emtry.c** 中 的 `void hal_entry(void)` 。用户编写的源文件可直接放在 src 目录下。
```c
void hal_entry(void)
{
rt_kprintf("\nHello RT-Thread!\n");
while (1)
{
rt_pin_write(LED3_PIN, PIN_HIGH);
rt_thread_mdelay(500);
rt_pin_write(LED3_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
}
```
### 进阶使用
**资料及文档**
- [开发板原理图](https://bbs.elecfans.com/jishu_2313024_1_1.html)
- [RA4M2硬件用户手册](https://bbs.elecfans.com/forum.php?mod=attachment&aid=MTIwMDQxN3wxYWU5YWFiMnwxNjcwNDY2MTg2fDU5NTQxMXwyMzEyNjc4)
- [RA4M2数据手册](https://bbs.elecfans.com/forum.php?mod=attachment&aid=MTIwMDQxNnxjOTJiOTgyOHwxNjcwNDY2MTg2fDU5NTQxMXwyMzEyNjc4)
**FSP 配置**
请查看 [RA-Eco-RA4M2-100PIN开发板资料](https://bbs.elecfans.com/jishu_2312678_1_1.html) 及官网和bsp/renesas/docs中的相关文档
**ENV 配置**
- 如何使用 ENV 工具：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
此 BSP 默认只开启了 UART9 的功能，如果需使用更多高级功能例如组件、软件包等，需要利用 ENV 工具进行配置。
步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons --target=mdk5` 命令重新生成工程。
## FAQ
### 使用 MDK 的 DEBUG 时如果遇到提示 “Error: Flash Download failed Cortex-M33” 怎么办？
可按照下图操作，修改 Utilities 中的选项：
![image-20211214102231248](docs/pictures/readme_faq1.png)
## 联系人信息
在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们 [RT-Thread 社区论坛](https://club.rt-thread.org/)
## 贡献代码
如果您对 RA4M2 感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [如何向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。
bsp/renesas/ra4m2-eco/SConscript 0 → 100644
浏览文件 @ ab9a80c4
# for module compiling
import os
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = []
CPPPATH = []
list = os.listdir(cwd)
if rtconfig.PLATFORM in ['iccarm']:
print("\nThe current project does not support IAR build\n")
Return('group')
elif rtconfig.PLATFORM in ['gcc', 'armclang']:
if GetOption('target') != 'mdk5':
CPPPATH = [cwd]
src = Glob('./src/*.c')
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
group = group + SConscript(os.path.join(d, 'SConscript'))
Return('group')
bsp/renesas/ra4m2-eco/SConstruct 0 → 100644
浏览文件 @ ab9a80c4
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM in ['iccarm']:
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
rtconfig.BSP_LIBRARY_TYPE = None
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)
bsp/renesas/ra4m2-eco/board/Kconfig 0 → 100644
浏览文件 @ ab9a80c4
menu "Hardware Drivers Config"
config SOC_R7FA4M2AD
bool
select SOC_SERIES_R7FA4M2
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
menu "Onboard Peripheral Drivers"
endmenu
menu "On-chip Peripheral Drivers"
source "../libraries/HAL_Drivers/Kconfig"
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
select RT_USING_SERIAL_V2
if BSP_USING_UART
menuconfig BSP_USING_UART0
bool "Enable UART0"
default n
if BSP_USING_UART0
config BSP_UART0_RX_USING_DMA
bool "Enable UART0 RX DMA"
depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
default n
config BSP_UART0_TX_USING_DMA
bool "Enable UART0 TX DMA"
depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
default n
config BSP_UART0_RX_BUFSIZE
int "Set UART0 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_UART0_TX_BUFSIZE
int "Set UART0 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
menuconfig BSP_USING_UART1
bool "Enable UART1"
default n
if BSP_USING_UART1
config BSP_UART1_RX_USING_DMA
bool "Enable UART1 RX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_UART1_TX_USING_DMA
bool "Enable UART1 TX DMA"
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
default n
config BSP_UART1_RX_BUFSIZE
int "Set UART1 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_UART1_TX_BUFSIZE
int "Set UART1 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
menuconfig BSP_USING_UART2
bool "Enable UART2"
default n
if BSP_USING_UART2
config BSP_UART2_RX_USING_DMA
bool "Enable UART2 RX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_UART2_TX_USING_DMA
bool "Enable UART2 TX DMA"
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
default n
config BSP_UART2_RX_BUFSIZE
int "Set UART2 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_UART2_TX_BUFSIZE
int "Set UART2 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
menuconfig BSP_USING_UART3
bool "Enable UART3"
default n
if BSP_USING_UART3
config BSP_UART3_RX_USING_DMA
bool "Enable UART3 RX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
config BSP_UART3_TX_USING_DMA
bool "Enable UART3 TX DMA"
depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
default n
config BSP_UART3_RX_BUFSIZE
int "Set UART3 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_UART3_TX_BUFSIZE
int "Set UART3 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
menuconfig BSP_USING_UART4
bool "Enable UART4"
default n
if BSP_USING_UART4
config BSP_UART4_RX_USING_DMA
bool "Enable UART4 RX DMA"
depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
default n
config BSP_UART4_TX_USING_DMA
bool "Enable UART4 TX DMA"
depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
default n
config BSP_UART4_RX_BUFSIZE
int "Set UART4 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_UART4_TX_BUFSIZE
int "Set UART4 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
menuconfig BSP_USING_UART9
bool "Enable UART9"
default n
if BSP_USING_UART9
config BSP_UART9_RX_USING_DMA
bool "Enable UART9 RX DMA"
depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA
default n
config BSP_UART9_TX_USING_DMA
bool "Enable UART9 TX DMA"
depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA
default n
config BSP_UART9_RX_BUFSIZE
int "Set UART9 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_UART9_TX_BUFSIZE
int "Set UART9 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
endif
menuconfig BSP_USING_SPI
bool "Enable SPI"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_SPI_USING_DTC_DMA
bool "Enable SPI DTC transfers data without using the CPU."
default n
config BSP_USING_SPI0
bool "Enable SPI0 BUS"
default n
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_USING_SCI_SPI0
bool "Enable SCI SPI0 BUS"
default n
config BSP_USING_SCI_SPI1
bool "Enable SCI SPI1 BUS"
default n
config BSP_USING_SCI_SPI2
bool "Enable SCI SPI2 BUS"
default n
config BSP_USING_SCI_SPI3
bool "Enable SCI SPI3 BUS"
default n
config BSP_USING_SCI_SPI4
bool "Enable SCI SPI4 BUS"
default n
config BSP_USING_SCI_SPI9
bool "Enable SCI SPI9 BUS"
default n
endif
endmenu
menu "Board extended module Drivers"
endmenu
endmenu
bsp/renesas/ra4m2-eco/board/SConscript 0 → 100644
浏览文件 @ ab9a80c4
import os
from building import *
objs = []
cwd = GetCurrentDir()
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
objs = objs + SConscript(os.path.join(item, 'SConscript'))
Return('objs')
bsp/renesas/ra4m2-eco/board/board.h 0 → 100644
浏览文件 @ ab9a80c4
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-10 Sherman first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#ifdef __cplusplus
extern "C" {
#endif
#define RA_SRAM_SIZE 256 /* The SRAM size of the chip needs to be modified */
#define RA_SRAM_END (0x20000000 + RA_SRAM_SIZE * 1024)
#ifdef __ARMCC_VERSION
extern int Image$$RAM_END$$ZI$$Base;
#define HEAP_BEGIN ((void *)&Image$$RAM_END$$ZI$$Base)
#elif __ICCARM__
#pragma section="CSTACK"
#define HEAP_BEGIN (__segment_end("CSTACK"))
#else
extern int __RAM_segment_used_end__;
#define HEAP_BEGIN (&__RAM_segment_used_end__)
#endif
#define HEAP_END RA_SRAM_END
#ifdef __cplusplus
}
#endif
#endif
bsp/renesas/ra4m2-eco/board/ports/SConscript 0 → 100644
浏览文件 @ ab9a80c4
from building import *
import rtconfig
cwd = GetCurrentDir()
src = []
if GetDepend(['BSP_USING_RW007']):
src += Glob('drv_rw007.c')
CPPPATH = [cwd]
LOCAL_CFLAGS = ''
if rtconfig.PLATFORM in ['gcc', 'armclang']:
LOCAL_CFLAGS += ' -std=c99'
elif rtconfig.PLATFORM in ['armcc']:
LOCAL_CFLAGS += ' --c99'
group = DefineGroup('Drivers', src, depend = [], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS)
Return('group')
bsp/renesas/ra4m2-eco/board/ports/gpio_cfg.h 0 → 100644
浏览文件 @ ab9a80c4
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-01-19 Sherman first version
*/
/* Number of IRQ channels on the device */
#define RA_IRQ_MAX 16
/* PIN to IRQx table */
#define PIN2IRQX_TABLE \
{ \
switch (pin) \
{ \
case BSP_IO_PORT_04_PIN_00: \
case BSP_IO_PORT_02_PIN_06: \
case BSP_IO_PORT_01_PIN_05: \
return 0; \
case BSP_IO_PORT_02_PIN_05: \
case BSP_IO_PORT_01_PIN_01: \
case BSP_IO_PORT_01_PIN_04: \
return 1; \
case BSP_IO_PORT_02_PIN_03: \
case BSP_IO_PORT_01_PIN_00: \
case BSP_IO_PORT_02_PIN_13: \
return 2; \
case BSP_IO_PORT_02_PIN_02: \
case BSP_IO_PORT_01_PIN_10: \
case BSP_IO_PORT_02_PIN_12: \
return 3; \
case BSP_IO_PORT_04_PIN_02: \
case BSP_IO_PORT_01_PIN_11: \
case BSP_IO_PORT_04_PIN_11: \
return 4; \
case BSP_IO_PORT_04_PIN_01: \
case BSP_IO_PORT_03_PIN_02: \
case BSP_IO_PORT_04_PIN_10: \
return 5; \
case BSP_IO_PORT_03_PIN_01: \
case BSP_IO_PORT_00_PIN_00: \
case BSP_IO_PORT_04_PIN_09: \
return 6; \
case BSP_IO_PORT_00_PIN_01: \
case BSP_IO_PORT_04_PIN_08: \
return 7; \
case BSP_IO_PORT_00_PIN_02: \
case BSP_IO_PORT_03_PIN_05: \
case BSP_IO_PORT_04_PIN_15: \
return 8; \
case BSP_IO_PORT_00_PIN_04: \
case BSP_IO_PORT_03_PIN_04: \
case BSP_IO_PORT_04_PIN_14: \
return 9; \
case BSP_IO_PORT_00_PIN_05: \
case BSP_IO_PORT_07_PIN_09: \
return 10; \
case BSP_IO_PORT_05_PIN_01: \
case BSP_IO_PORT_00_PIN_06: \
case BSP_IO_PORT_07_PIN_08: \
return 11; \
case BSP_IO_PORT_05_PIN_02: \
case BSP_IO_PORT_00_PIN_08: \
return 12; \
case BSP_IO_PORT_00_PIN_15: \
case BSP_IO_PORT_00_PIN_09: \
return 13; \
case BSP_IO_PORT_04_PIN_03: \
case BSP_IO_PORT_05_PIN_12: \
case BSP_IO_PORT_05_PIN_05: \
return 14; \
case BSP_IO_PORT_04_PIN_04: \
case BSP_IO_PORT_05_PIN_11: \
case BSP_IO_PORT_05_PIN_06: \
return 15; \
default : \
return -1; \
} \
}
bsp/renesas/ra4m2-eco/buildinfo.gpdsc 0 → 100644
浏览文件 @ ab9a80c4
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
<vendor>Renesas</vendor>
<name>Project Content</name>
<description>Project content managed by the Renesas Smart Configurator</description>
<url/>
<releases>
<release version="1.0.0"/>
</releases>
<generators>
<generator id="Renesas RA Smart Configurator">
<project_files>
<file category="include" name="src/"/>
<file category="source" name="src/hal_entry.cpp"/>
</project_files>
</generator>
</generators>
<components generator="Renesas RA Smart Configurator">
<component Cclass="Flex Software" Cgroup="Components" Csub="ra">
<files>
<file category="include" name="ra/arm/CMSIS_5/CMSIS/Core/Include/"/>
<file category="include" name="ra/fsp/inc/"/>
<file category="include" name="ra/fsp/inc/api/"/>
<file category="include" name="ra/fsp/inc/instances/"/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm85.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_starmc1.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/pac_armv81.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h" path=""/>
<file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h" path=""/>
<file category="other" name="ra/arm/CMSIS_5/LICENSE.txt"/>
<file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_spi_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_transfer_api.h" path=""/>
<file category="header" name="ra/fsp/inc/api/r_uart_api.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_common_api.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
<file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_dtc.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_sci_spi.h" path=""/>
<file category="header" name="ra/fsp/inc/instances/r_sci_uart.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"/>
<file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_common.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_common.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_delay.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_delay.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_guard.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_guard.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_io.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_io.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_irq.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_irq.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_module_stop.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.h" path=""/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.c"/>
<file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_security.c"/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_security.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_tfu.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra4m2/bsp_elc.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h" path=""/>
<file category="header" name="ra/fsp/src/bsp/mcu/ra4m2/bsp_mcu_info.h" path=""/>
<file category="source" name="ra/fsp/src/r_dtc/r_dtc.c"/>
<file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
<file category="source" name="ra/fsp/src/r_sci_spi/r_sci_spi.c"/>
<file category="source" name="ra/fsp/src/r_sci_uart/r_sci_uart.c"/>
<file category="other" name="ra/SConscript"/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Build Configuration">
<files>
<file category="include" name="ra_cfg/fsp_cfg/"/>
<file category="include" name="ra_cfg/fsp_cfg/bsp/"/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/board_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_dtc_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_sci_spi_cfg.h" path=""/>
<file category="header" name="ra_cfg/fsp_cfg/r_sci_uart_cfg.h" path=""/>
<file category="other" name="ra_cfg/SConscript"/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Generated Data">
<files>
<file category="include" name="ra_gen/"/>
<file category="header" name="ra_gen/bsp_clock_cfg.h" path=""/>
<file category="source" name="ra_gen/common_data.c"/>
<file category="header" name="ra_gen/common_data.h" path=""/>
<file category="source" name="ra_gen/hal_data.c"/>
<file category="header" name="ra_gen/hal_data.h" path=""/>
<file category="source" name="ra_gen/main.c"/>
<file category="source" name="ra_gen/pin_data.c"/>
<file category="other" name="ra_gen/SConscript"/>
<file category="source" name="ra_gen/vector_data.c"/>
<file category="header" name="ra_gen/vector_data.h" path=""/>
</files>
</component>
<component Cclass="Flex Software" Cgroup="Linker Script">
<files>
<file category="linkerScript" name="script/fsp.scat"/>
<file category="other" name="script/ac6/fsp_keep.via"/>
</files>
</component>
</components>
</package>
bsp/renesas/ra4m2-eco/configuration.xml 0 → 100644
浏览文件 @ ab9a80c4
此差异已折叠。
bsp/renesas/ra4m2-eco/memory_regions.scat 0 → 100644
浏览文件 @ ab9a80c4
/* generated memory regions file - do not edit */
#define RAM_START 0x20000000
#define RAM_LENGTH 0x20000
#define FLASH_START 0x00000000
#define FLASH_LENGTH 0x80000
#define DATA_FLASH_START 0x08000000
#define DATA_FLASH_LENGTH 0x2000
#define OPTION_SETTING_START 0x0100A100
#define OPTION_SETTING_LENGTH 0x100
#define OPTION_SETTING_S_START 0x0100A200
#define OPTION_SETTING_S_LENGTH 0x100
#define ID_CODE_START 0x00000000
#define ID_CODE_LENGTH 0x0
#define SDRAM_START 0x00000000
#define SDRAM_LENGTH 0x0
#define QSPI_FLASH_START 0x60000000
#define QSPI_FLASH_LENGTH 0x4000000
#define OSPI_DEVICE_0_START 0x00000000
#define OSPI_DEVICE_0_LENGTH 0x0
#define OSPI_DEVICE_1_START 0x00000000
#define OSPI_DEVICE_1_LENGTH 0x0
bsp/renesas/ra4m2-eco/project.uvoptx 0 → 100644
浏览文件 @ ab9a80c4
此差异已折叠。
bsp/renesas/ra4m2-eco/project.uvprojx 0 → 100644
浏览文件 @ ab9a80c4
此差异已折叠。
bsp/renesas/ra4m2-eco/ra/SConscript 0 → 100644
浏览文件 @ ab9a80c4
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = []
group = []
CPPPATH = []
if rtconfig.PLATFORM in ['iccarm']:
print("\nThe current project does not support IAR build\n")
Return('group')
elif rtconfig.PLATFORM in ['gcc', 'armclang']:
if GetOption('target') != 'mdk5':
src += Glob(cwd + '/fsp/src/bsp/mcu/all/*.c')
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c']
src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c']
src += Glob(cwd + '/fsp/src/r_*/*.c')
CPPPATH = [ cwd + '/arm/CMSIS_5/CMSIS/Core/Include',
cwd + '/fsp/inc',
cwd + '/fsp/inc/api',
cwd + '/fsp/inc/instances',]
group = DefineGroup('ra', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/renesas/ra4m2-eco/ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h 0 → 100644
浏览文件 @ ab9a80c4
/******************************************************************************
* @file cachel1_armv7.h
* @brief CMSIS Level 1 Cache API for Armv7-M and later
* @version V1.0.1
* @date 19. April 2021
******************************************************************************/
/*
* Copyright (c) 2020-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_CACHEL1_ARMV7_H
#define ARM_CACHEL1_ARMV7_H
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_CacheFunctions Cache Functions
\brief Functions that configure Instruction and Data cache.
@{
*/
/* Cache Size ID Register Macros */
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
#ifndef __SCB_DCACHE_LINE_SIZE
#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
#endif
#ifndef __SCB_ICACHE_LINE_SIZE
#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
#endif
/**
\brief Enable I-Cache
\details Turns on I-Cache
*/
__STATIC_FORCEINLINE void SCB_EnableICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
__DSB();
__ISB();
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
__DSB();
__ISB();
SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable I-Cache
\details Turns off I-Cache
*/
__STATIC_FORCEINLINE void SCB_DisableICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate I-Cache
\details Invalidates I-Cache
*/
__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
__DSB();
__ISB();
SCB->ICIALLU = 0UL;
__DSB();
__ISB();
#endif
}
/**
\brief I-Cache Invalidate by address
\details Invalidates I-Cache for the given address.
I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
I-Cache memory blocks which are part of given address + given size are invalidated.
\param[in] addr address
\param[in] isize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
{
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
if ( isize > 0 ) {
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_ICACHE_LINE_SIZE;
op_size -= __SCB_ICACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief Enable D-Cache
\details Turns on D-Cache
*/
__STATIC_FORCEINLINE void SCB_EnableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
__DSB();
__ISB();
#endif
}
/**
\brief Disable D-Cache
\details Turns off D-Cache
*/
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean & invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Invalidate D-Cache
\details Invalidates D-Cache
*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Clean D-Cache
\details Cleans D-Cache
*/
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief Clean & Invalidate D-Cache
\details Cleans and Invalidates D-Cache
*/
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
uint32_t ccsidr;
uint32_t sets;
uint32_t ways;
SCB->CSSELR = 0U; /* select Level 1 data cache */
__DSB();
ccsidr = SCB->CCSIDR;
/* clean & invalidate D-Cache */
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
do {
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
do {
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
#if defined ( __CC_ARM )
__schedule_barrier();
#endif
} while (ways-- != 0U);
} while(sets-- != 0U);
__DSB();
__ISB();
#endif
}
/**
\brief D-Cache Invalidate by address
\details Invalidates D-Cache for the given address.
D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are invalidated.
\param[in] addr address
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief D-Cache Clean by address
\details Cleans D-Cache for the given address
D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are cleaned.
\param[in] addr address
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/**
\brief D-Cache Clean and Invalidate by address
\details Cleans and invalidates D_Cache for the given address
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
\param[in] addr address (aligned to 32-byte boundary)
\param[in] dsize size of memory block (in number of bytes)
*/
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
{
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
if ( dsize > 0 ) {
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
__DSB();
do {
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
op_addr += __SCB_DCACHE_LINE_SIZE;
op_size -= __SCB_DCACHE_LINE_SIZE;
} while ( op_size > 0 );
__DSB();
__ISB();
}
#endif
}
/*@} end of CMSIS_Core_CacheFunctions */
#endif /* ARM_CACHEL1_ARMV7_H */
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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */
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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.5
* @date 02. February 2022
******************************************************************************/
/*
* Copyright (c) 2009-2022 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif
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/******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H
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/***********************************************************************************************************************
* Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved.
*
* This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products
* of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are
* sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use
* of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property
* right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas
* reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION
* IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT
* PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR
* DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM
* EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION
* (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING,
* WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS,
* OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY
* OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS.
**********************************************************************************************************************/
#ifndef BSP_API_H
#define BSP_API_H
/***********************************************************************************************************************
* Includes <System Includes> , "Project Includes"
**********************************************************************************************************************/
/* FSP Common Includes. */
#include "fsp_common_api.h"
/* Gets MCU configuration information. */
#include "bsp_cfg.h"
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h.
* We are not modifying these files so we will ignore these warnings temporarily. */
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wsign-conversion"
#endif
/* Vector information for this project. This is generated by the tooling. */
#include "../../src/bsp/mcu/all/bsp_arm_exceptions.h"
#include "vector_data.h"
/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */
#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h"
#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h"
#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */
#pragma GCC diagnostic pop
#endif
/* BSP Common Includes. */
#include "../../src/bsp/mcu/all/bsp_common.h"
/* BSP MCU Specific Includes. */
#include "../../src/bsp/mcu/all/bsp_register_protection.h"
#include "../../src/bsp/mcu/all/bsp_irq.h"
#include "../../src/bsp/mcu/all/bsp_io.h"
#include "../../src/bsp/mcu/all/bsp_group_irq.h"
#include "../../src/bsp/mcu/all/bsp_clocks.h"
#include "../../src/bsp/mcu/all/bsp_module_stop.h"
#include "../../src/bsp/mcu/all/bsp_security.h"
/* Factory MCU information. */
#include "../../inc/fsp_features.h"
/* BSP Common Includes (Other than bsp_common.h) */
#include "../../src/bsp/mcu/all/bsp_delay.h"
#include "../../src/bsp/mcu/all/bsp_mcu_api.h"
/* BSP TFU Includes. */
#if BSP_FEATURE_TFU_SUPPORTED
#include "../../src/bsp/mcu/all/bsp_tfu.h"
#endif
/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
FSP_HEADER
/***********************************************************************************************************************
* Typedef definitions
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global variables
**********************************************************************************************************************/
/***********************************************************************************************************************
* Exported global functions (to be accessed by other files)
**********************************************************************************************************************/
/*******************************************************************************************************************//**
* @addtogroup BSP_MCU
* @{
**********************************************************************************************************************/
fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version);
/** @} (end addtogroup BSP_MCU) */
/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
FSP_FOOTER
#endif
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bsp/renesas/ra4m2-eco/ra_gen/hal_data.c 0 → 100644
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bsp/renesas/ra4m2-eco/ra_gen/main.c 0 → 100644
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bsp/renesas/ra4m2-eco/ra_gen/pin_data.c 0 → 100644
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bsp/renesas/ra4m2-eco/ra_gen/vector_data.c 0 → 100644
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