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97b6f10a
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体验新版 GitCode,发现更多精彩内容 >>
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97b6f10a
编写于
5月 14, 2021
作者:
W
Wang-Huachen
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
format files in zynqmp-r5-axu4ev bsp
上级
d2057214
变更
48
展开全部
隐藏空白更改
内联
并排
Showing
48 changed file
with
6149 addition
and
6149 deletion
+6149
-6149
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps.c
...-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps.c
+117
-117
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps.h
...-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps.h
+42
-42
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_bdring.c
...4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_bdring.c
+226
-226
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_bdring.h
...4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_bdring.h
+19
-19
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_control.c
...ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_control.c
+347
-347
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_g.c
...5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_g.c
+5
-5
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_hw.c
...-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_hw.c
+21
-21
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_hw.h
...-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_hw.h
+41
-41
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_intr.c
...xu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_intr.c
+65
-65
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_sinit.c
...u4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_sinit.c
+7
-7
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.c
...p-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.c
+245
-245
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.h
...p-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.h
+41
-41
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_g.c
...r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_g.c
+4
-4
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.c
...5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.c
+7
-7
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.h
...5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.h
+12
-12
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_intr.c
...axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_intr.c
+298
-298
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_selftest.c
...ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_selftest.c
+23
-23
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_sinit.c
...xu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_sinit.c
+12
-12
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.c
...ynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.c
+153
-153
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.h
...ynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.h
+80
-80
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_card.c
...-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_card.c
+638
-638
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_g.c
...qmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_g.c
+20
-20
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_host.c
...-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_host.c
+864
-864
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_hw.h
...mp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_hw.h
+665
-665
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_options.c
...-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_options.c
+272
-272
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_sinit.c
...r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_sinit.c
+10
-10
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sleep.h
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sleep.h
+5
-5
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xadapter.h
...axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xadapter.h
+16
-16
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xemacpsif.h
...xu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xemacpsif.h
+26
-26
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xpqueue.h
...-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xpqueue.h
+6
-6
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xtopology.h
...xu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xtopology.h
+6
-6
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xadapter.c
...mp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xadapter.c
+148
-148
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemac_ieee_reg.h
...axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemac_ieee_reg.h
+1
-1
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif.c
...p-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif.c
+298
-298
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif_dma.c
...-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif_dma.c
+401
-401
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif_hw.c
...5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif_hw.c
+113
-113
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif_physpeed.c
...ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif_physpeed.c
+639
-639
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xpqueue.c
...qmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xpqueue.c
+25
-25
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xtopology_g.c
...r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xtopology_g.c
+6
-6
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_io.h
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_io.h
+30
-30
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_types.h
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_types.h
+7
-7
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters.h
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters.h
+9
-9
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters_ps.h
...zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters_ps.h
+138
-138
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xplatform_info.h
...zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xplatform_info.h
+7
-7
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xstatus.h
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xstatus.h
+24
-24
bsp/zynqmp-r5-axu4ev/drivers/drv_eth.c
bsp/zynqmp-r5-axu4ev/drivers/drv_eth.c
+3
-3
bsp/zynqmp-r5-axu4ev/drivers/drv_timer.c
bsp/zynqmp-r5-axu4ev/drivers/drv_timer.c
+2
-2
bsp/zynqmp-r5-axu4ev/drivers/zynqmp-r5.h
bsp/zynqmp-r5-axu4ev/drivers/zynqmp-r5.h
+5
-5
未找到文件。
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps.c
浏览文件 @
97b6f10a
...
...
@@ -81,27 +81,27 @@ LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
UINTPTR
EffectiveAddress
)
{
/* Verify arguments */
Xil_AssertNonvoid
(
InstancePtr
!=
NULL
);
Xil_AssertNonvoid
(
CfgPtr
!=
NULL
);
Xil_AssertNonvoid
(
InstancePtr
!=
NULL
);
Xil_AssertNonvoid
(
CfgPtr
!=
NULL
);
/* Set device base address and ID */
InstancePtr
->
Config
.
DeviceId
=
CfgPtr
->
DeviceId
;
InstancePtr
->
Config
.
BaseAddress
=
EffectiveAddress
;
InstancePtr
->
Config
.
IsCacheCoherent
=
CfgPtr
->
IsCacheCoherent
;
InstancePtr
->
Config
.
DeviceId
=
CfgPtr
->
DeviceId
;
InstancePtr
->
Config
.
BaseAddress
=
EffectiveAddress
;
InstancePtr
->
Config
.
IsCacheCoherent
=
CfgPtr
->
IsCacheCoherent
;
#if defined (XCLOCKING)
InstancePtr
->
Config
.
RefClk
=
CfgPtr
->
RefClk
;
InstancePtr
->
Config
.
RefClk
=
CfgPtr
->
RefClk
;
#endif
/* Set callbacks to an initial stub routine */
InstancePtr
->
SendHandler
=
((
XEmacPs_Handler
)((
void
*
)
XEmacPs_StubHandler
));
InstancePtr
->
RecvHandler
=
((
XEmacPs_Handler
)(
void
*
)
XEmacPs_StubHandler
);
InstancePtr
->
ErrorHandler
=
((
XEmacPs_ErrHandler
)(
void
*
)
XEmacPs_StubHandler
);
InstancePtr
->
SendHandler
=
((
XEmacPs_Handler
)((
void
*
)
XEmacPs_StubHandler
));
InstancePtr
->
RecvHandler
=
((
XEmacPs_Handler
)(
void
*
)
XEmacPs_StubHandler
);
InstancePtr
->
ErrorHandler
=
((
XEmacPs_ErrHandler
)(
void
*
)
XEmacPs_StubHandler
);
/* Reset the hardware and set default options */
InstancePtr
->
IsReady
=
XIL_COMPONENT_IS_READY
;
XEmacPs_Reset
(
InstancePtr
);
InstancePtr
->
IsReady
=
XIL_COMPONENT_IS_READY
;
XEmacPs_Reset
(
InstancePtr
);
return
(
LONG
)(
XST_SUCCESS
);
return
(
LONG
)(
XST_SUCCESS
);
}
...
...
@@ -134,15 +134,15 @@ LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
******************************************************************************/
void
XEmacPs_Start
(
XEmacPs
*
InstancePtr
)
{
u32
Reg
;
u32
Reg
;
/* Assert bad arguments and conditions */
Xil_AssertVoid
(
InstancePtr
!=
NULL
);
Xil_AssertVoid
(
InstancePtr
->
IsReady
==
(
u32
)
XIL_COMPONENT_IS_READY
);
Xil_AssertVoid
(
InstancePtr
!=
NULL
);
Xil_AssertVoid
(
InstancePtr
->
IsReady
==
(
u32
)
XIL_COMPONENT_IS_READY
);
#if defined (XCLOCKING)
if
(
InstancePtr
->
IsStarted
!=
(
u32
)
XIL_COMPONENT_IS_STARTED
)
{
Xil_ClockEnable
(
InstancePtr
->
Config
.
RefClk
);
if
(
InstancePtr
->
IsStarted
!=
(
u32
)
XIL_COMPONENT_IS_STARTED
)
{
Xil_ClockEnable
(
InstancePtr
->
Config
.
RefClk
);
}
#endif
...
...
@@ -150,39 +150,39 @@ void XEmacPs_Start(XEmacPs *InstancePtr)
/* When starting the DMA channels, both transmit and receive sides
* need an initialized BD list.
*/
if
(
InstancePtr
->
Version
==
2
)
{
Xil_AssertVoid
(
InstancePtr
->
RxBdRing
.
BaseBdAddr
!=
0
);
Xil_AssertVoid
(
InstancePtr
->
TxBdRing
.
BaseBdAddr
!=
0
);
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
if
(
InstancePtr
->
Version
==
2
)
{
Xil_AssertVoid
(
InstancePtr
->
RxBdRing
.
BaseBdAddr
!=
0
);
Xil_AssertVoid
(
InstancePtr
->
TxBdRing
.
BaseBdAddr
!=
0
);
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_RXQBASE_OFFSET
,
InstancePtr
->
RxBdRing
.
BaseBdAddr
);
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_TXQBASE_OFFSET
,
InstancePtr
->
TxBdRing
.
BaseBdAddr
);
}
/* clear any existed int status */
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_ISR_OFFSET
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_ISR_OFFSET
,
XEMACPS_IXR_ALL_MASK
);
/* Enable transmitter if not already enabled */
if
((
InstancePtr
->
Options
&
(
u32
)
XEMACPS_TRANSMITTER_ENABLE_OPTION
)
!=
0x00000000U
)
{
Reg
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCTRL_OFFSET
);
if
((
!
(
Reg
&
XEMACPS_NWCTRL_TXEN_MASK
))
==
TRUE
)
{
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
if
((
InstancePtr
->
Options
&
(
u32
)
XEMACPS_TRANSMITTER_ENABLE_OPTION
)
!=
0x00000000U
)
{
Reg
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCTRL_OFFSET
);
if
((
!
(
Reg
&
XEMACPS_NWCTRL_TXEN_MASK
))
==
TRUE
)
{
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCTRL_OFFSET
,
Reg
|
(
u32
)
XEMACPS_NWCTRL_TXEN_MASK
);
}
}
/* Enable receiver if not already enabled */
if
((
InstancePtr
->
Options
&
XEMACPS_RECEIVER_ENABLE_OPTION
)
!=
0x00000000U
)
{
Reg
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCTRL_OFFSET
);
if
((
!
(
Reg
&
XEMACPS_NWCTRL_RXEN_MASK
))
==
TRUE
)
{
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
if
((
InstancePtr
->
Options
&
XEMACPS_RECEIVER_ENABLE_OPTION
)
!=
0x00000000U
)
{
Reg
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCTRL_OFFSET
);
if
((
!
(
Reg
&
XEMACPS_NWCTRL_RXEN_MASK
))
==
TRUE
)
{
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCTRL_OFFSET
,
Reg
|
(
u32
)
XEMACPS_NWCTRL_RXEN_MASK
);
}
...
...
@@ -190,17 +190,17 @@ void XEmacPs_Start(XEmacPs *InstancePtr)
/* Enable TX and RX interrupts */
XEmacPs_IntEnable
(
InstancePtr
,
(
XEMACPS_IXR_TX_ERR_MASK
|
XEMACPS_IXR_RX_ERR_MASK
|
(
u32
)
XEMACPS_IXR_FRAMERX_MASK
|
XEMACPS_IXR_RX_ERR_MASK
|
(
u32
)
XEMACPS_IXR_FRAMERX_MASK
|
(
u32
)
XEMACPS_IXR_TXCOMPL_MASK
));
/* Enable TX Q1 Interrupts */
if
(
InstancePtr
->
Version
>
2
)
XEmacPs_IntQ1Enable
(
InstancePtr
,
XEMACPS_INTQ1_IXR_ALL_MASK
);
if
(
InstancePtr
->
Version
>
2
)
XEmacPs_IntQ1Enable
(
InstancePtr
,
XEMACPS_INTQ1_IXR_ALL_MASK
);
/* Mark as started */
InstancePtr
->
IsStarted
=
XIL_COMPONENT_IS_STARTED
;
InstancePtr
->
IsStarted
=
XIL_COMPONENT_IS_STARTED
;
return
;
return
;
}
...
...
@@ -231,27 +231,27 @@ void XEmacPs_Start(XEmacPs *InstancePtr)
******************************************************************************/
void
XEmacPs_Stop
(
XEmacPs
*
InstancePtr
)
{
u32
Reg
;
u32
Reg
;
Xil_AssertVoid
(
InstancePtr
!=
NULL
);
Xil_AssertVoid
(
InstancePtr
->
IsReady
==
(
u32
)
XIL_COMPONENT_IS_READY
);
Xil_AssertVoid
(
InstancePtr
!=
NULL
);
Xil_AssertVoid
(
InstancePtr
->
IsReady
==
(
u32
)
XIL_COMPONENT_IS_READY
);
/* Disable all interrupts */
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_IDR_OFFSET
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_IDR_OFFSET
,
XEMACPS_IXR_ALL_MASK
);
/* Disable the receiver & transmitter */
Reg
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCTRL_OFFSET
);
Reg
&=
(
u32
)(
~
XEMACPS_NWCTRL_RXEN_MASK
);
Reg
&=
(
u32
)(
~
XEMACPS_NWCTRL_TXEN_MASK
);
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
Reg
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCTRL_OFFSET
);
Reg
&=
(
u32
)(
~
XEMACPS_NWCTRL_RXEN_MASK
);
Reg
&=
(
u32
)(
~
XEMACPS_NWCTRL_TXEN_MASK
);
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCTRL_OFFSET
,
Reg
);
/* Mark as stopped */
InstancePtr
->
IsStarted
=
0U
;
InstancePtr
->
IsStarted
=
0U
;
#if defined (XCLOCKING)
Xil_ClockDisable
(
InstancePtr
->
Config
.
RefClk
);
Xil_ClockDisable
(
InstancePtr
->
Config
.
RefClk
);
#endif
}
...
...
@@ -290,53 +290,53 @@ void XEmacPs_Stop(XEmacPs *InstancePtr)
******************************************************************************/
void
XEmacPs_Reset
(
XEmacPs
*
InstancePtr
)
{
u32
Reg
;
u8
i
;
s8
EmacPs_zero_MAC
[
6
]
=
{
0x0
,
0x0
,
0x0
,
0x0
,
0x0
,
0x0
};
u32
Reg
;
u8
i
;
s8
EmacPs_zero_MAC
[
6
]
=
{
0x0
,
0x0
,
0x0
,
0x0
,
0x0
,
0x0
};
Xil_AssertVoid
(
InstancePtr
!=
NULL
);
Xil_AssertVoid
(
InstancePtr
->
IsReady
==
(
u32
)
XIL_COMPONENT_IS_READY
);
Xil_AssertVoid
(
InstancePtr
!=
NULL
);
Xil_AssertVoid
(
InstancePtr
->
IsReady
==
(
u32
)
XIL_COMPONENT_IS_READY
);
/* Stop the device and reset hardware */
XEmacPs_Stop
(
InstancePtr
);
InstancePtr
->
Options
=
XEMACPS_DEFAULT_OPTIONS
;
XEmacPs_Stop
(
InstancePtr
);
InstancePtr
->
Options
=
XEMACPS_DEFAULT_OPTIONS
;
InstancePtr
->
Version
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
0xFC
);
InstancePtr
->
Version
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
0xFC
);
InstancePtr
->
Version
=
(
InstancePtr
->
Version
>>
16
)
&
0xFFF
;
InstancePtr
->
Version
=
(
InstancePtr
->
Version
>>
16
)
&
0xFFF
;
InstancePtr
->
MaxMtuSize
=
XEMACPS_MTU
;
InstancePtr
->
MaxFrameSize
=
XEMACPS_MTU
+
XEMACPS_HDR_SIZE
+
XEMACPS_TRL_SIZE
;
InstancePtr
->
MaxVlanFrameSize
=
InstancePtr
->
MaxFrameSize
+
XEMACPS_HDR_VLAN_SIZE
;
InstancePtr
->
RxBufMask
=
XEMACPS_RXBUF_LEN_MASK
;
InstancePtr
->
MaxMtuSize
=
XEMACPS_MTU
;
InstancePtr
->
MaxFrameSize
=
XEMACPS_MTU
+
XEMACPS_HDR_SIZE
+
XEMACPS_TRL_SIZE
;
InstancePtr
->
MaxVlanFrameSize
=
InstancePtr
->
MaxFrameSize
+
XEMACPS_HDR_VLAN_SIZE
;
InstancePtr
->
RxBufMask
=
XEMACPS_RXBUF_LEN_MASK
;
/* Setup hardware with default values */
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCTRL_OFFSET
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCTRL_OFFSET
,
(
XEMACPS_NWCTRL_STATCLR_MASK
|
XEMACPS_NWCTRL_MDEN_MASK
)
&
XEMACPS_NWCTRL_MDEN_MASK
)
&
(
u32
)(
~
XEMACPS_NWCTRL_LOOPEN_MASK
));
Reg
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCFG_OFFSET
);
Reg
&=
XEMACPS_NWCFG_MDCCLKDIV_MASK
;
Reg
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCFG_OFFSET
);
Reg
&=
XEMACPS_NWCFG_MDCCLKDIV_MASK
;
Reg
=
Reg
|
(
u32
)
XEMACPS_NWCFG_100_MASK
|
Reg
=
Reg
|
(
u32
)
XEMACPS_NWCFG_100_MASK
|
(
u32
)
XEMACPS_NWCFG_FDEN_MASK
|
(
u32
)
XEMACPS_NWCFG_UCASTHASHEN_MASK
;
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCFG_OFFSET
,
Reg
);
if
(
InstancePtr
->
Version
>
2
)
{
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCFG_OFFSET
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCFG_OFFSET
,
Reg
);
if
(
InstancePtr
->
Version
>
2
)
{
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCFG_OFFSET
,
(
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCFG_OFFSET
)
|
XEMACPS_NWCFG_DWIDTH_64_MASK
));
XEMACPS_NWCFG_DWIDTH_64_MASK
));
}
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_DMACR_OFFSET
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_DMACR_OFFSET
,
(((((
u32
)
XEMACPS_RX_BUF_SIZE
/
(
u32
)
XEMACPS_RX_BUF_UNIT
)
+
(((((
u32
)
XEMACPS_RX_BUF_SIZE
%
(
u32
)
XEMACPS_RX_BUF_UNIT
))
!=
(
u32
)
0
)
?
1U
:
0U
))
<<
...
...
@@ -346,8 +346,8 @@ void XEmacPs_Reset(XEmacPs *InstancePtr)
(
u32
)
XEMACPS_DMACR_TXSIZE_MASK
);
if
(
InstancePtr
->
Version
>
2
)
{
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_DMACR_OFFSET
,
if
(
InstancePtr
->
Version
>
2
)
{
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_DMACR_OFFSET
,
(
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_DMACR_OFFSET
)
|
#if defined(__aarch64__) || defined(__arch64__)
(
u32
)
XEMACPS_DMACR_ADDR_WIDTH_64
|
...
...
@@ -355,44 +355,44 @@ void XEmacPs_Reset(XEmacPs *InstancePtr)
(
u32
)
XEMACPS_DMACR_INCR16_AHB_BURST
));
}
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_TXSR_OFFSET
,
XEMACPS_SR_ALL_MASK
);
XEmacPs_SetQueuePtr
(
InstancePtr
,
0
,
0x00U
,
(
u16
)
XEMACPS_SEND
);
if
(
InstancePtr
->
Version
>
2
)
XEmacPs_SetQueuePtr
(
InstancePtr
,
0
,
0x01U
,
(
u16
)
XEMACPS_SEND
);
XEmacPs_SetQueuePtr
(
InstancePtr
,
0
,
0x00U
,
(
u16
)
XEMACPS_RECV
);
XEmacPs_SetQueuePtr
(
InstancePtr
,
0
,
0x00U
,
(
u16
)
XEMACPS_SEND
);
if
(
InstancePtr
->
Version
>
2
)
XEmacPs_SetQueuePtr
(
InstancePtr
,
0
,
0x01U
,
(
u16
)
XEMACPS_SEND
);
XEmacPs_SetQueuePtr
(
InstancePtr
,
0
,
0x00U
,
(
u16
)
XEMACPS_RECV
);
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_RXSR_OFFSET
,
XEMACPS_SR_ALL_MASK
);
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_IDR_OFFSET
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_IDR_OFFSET
,
XEMACPS_IXR_ALL_MASK
);
Reg
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_ISR_OFFSET
);
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_ISR_OFFSET
,
Reg
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_ISR_OFFSET
);
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_ISR_OFFSET
,
Reg
);
XEmacPs_ClearHash
(
InstancePtr
);
XEmacPs_ClearHash
(
InstancePtr
);
for
(
i
=
1U
;
i
<
5U
;
i
++
)
{
for
(
i
=
1U
;
i
<
5U
;
i
++
)
{
(
void
)
XEmacPs_SetMacAddress
(
InstancePtr
,
EmacPs_zero_MAC
,
i
);
(
void
)
XEmacPs_SetTypeIdCheck
(
InstancePtr
,
0x00000000U
,
i
);
}
/* clear all counters */
for
(
i
=
0U
;
i
<
(
u8
)((
XEMACPS_LAST_OFFSET
-
XEMACPS_OCTTXL_OFFSET
)
/
4U
);
for
(
i
=
0U
;
i
<
(
u8
)((
XEMACPS_LAST_OFFSET
-
XEMACPS_OCTTXL_OFFSET
)
/
4U
);
i
++
)
{
(
void
)
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_OCTTXL_OFFSET
+
(
u32
)(((
u32
)
i
)
*
((
u32
)
4
)));
}
/* Disable the receiver */
Reg
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCTRL_OFFSET
);
Reg
&=
(
u32
)(
~
XEMACPS_NWCTRL_RXEN_MASK
);
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
Reg
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCTRL_OFFSET
);
Reg
&=
(
u32
)(
~
XEMACPS_NWCTRL_RXEN_MASK
);
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCTRL_OFFSET
,
Reg
);
/* Sync default options with hardware but leave receiver and
...
...
@@ -418,17 +418,17 @@ void XEmacPs_Reset(XEmacPs *InstancePtr)
******************************************************************************/
void
XEmacPs_StubHandler
(
void
)
{
Xil_AssertVoidAlways
();
Xil_AssertVoidAlways
();
}
/*****************************************************************************/
/**
* This function sets the start address of the transmit/receive buffer queue.
*
* @param
InstancePtr is a pointer to the instance to be worked on.
* @param
QPtr is the address of the Queue to be written
* @param
QueueNum is the Buffer Queue Index
* @param
Direction indicates Transmit/Receive
* @param
InstancePtr is a pointer to the instance to be worked on.
* @param
QPtr is the address of the Queue to be written
* @param
QueueNum is the Buffer Queue Index
* @param
Direction indicates Transmit/Receive
*
* @note
* The buffer queue addresses has to be set before starting the transfer, so
...
...
@@ -439,40 +439,40 @@ void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
u16
Direction
)
{
/* Assert bad arguments and conditions */
Xil_AssertVoid
(
InstancePtr
!=
NULL
);
Xil_AssertVoid
(
InstancePtr
->
IsReady
==
(
u32
)
XIL_COMPONENT_IS_READY
);
Xil_AssertVoid
(
InstancePtr
!=
NULL
);
Xil_AssertVoid
(
InstancePtr
->
IsReady
==
(
u32
)
XIL_COMPONENT_IS_READY
);
/* If already started, then there is nothing to do */
if
(
InstancePtr
->
IsStarted
==
(
u32
)
XIL_COMPONENT_IS_STARTED
)
{
return
;
}
if
(
QueueNum
==
0x00U
)
{
if
(
Direction
==
XEMACPS_SEND
)
{
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_TXQBASE_OFFSET
,
if
(
QueueNum
==
0x00U
)
{
if
(
Direction
==
XEMACPS_SEND
)
{
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_TXQBASE_OFFSET
,
(
QPtr
&
ULONG64_LO_MASK
));
}
else
{
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_RXQBASE_OFFSET
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_RXQBASE_OFFSET
,
(
QPtr
&
ULONG64_LO_MASK
));
}
}
else
{
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_TXQ1BASE_OFFSET
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_TXQ1BASE_OFFSET
,
(
QPtr
&
ULONG64_LO_MASK
));
}
#ifdef __aarch64__
if
(
Direction
==
XEMACPS_SEND
)
{
if
(
Direction
==
XEMACPS_SEND
)
{
/* Set the MSB of TX Queue start address */
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_MSBBUF_TXQBASE_OFFSET
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_MSBBUF_TXQBASE_OFFSET
,
(
u32
)((
QPtr
&
ULONG64_HI_MASK
)
>>
32U
));
}
else
{
/* Set the MSB of RX Queue start address */
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_MSBBUF_RXQBASE_OFFSET
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_MSBBUF_RXQBASE_OFFSET
,
(
u32
)((
QPtr
&
ULONG64_HI_MASK
)
>>
32U
));
}
#endif
...
...
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps.h
浏览文件 @
97b6f10a
...
...
@@ -265,7 +265,7 @@
* removed. It is expected that all BDs are allocated in
* from uncached area.
* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
*
to 0x1fff. This fixes the CR#744902.
*
to 0x1fff. This fixes the CR#744902.
* Made changes in example file xemacps_example.h to fix compilation
* issues with iarcc compiler.
* 2.0 adk 10/12/13 Updated as per the New Tcl API's
...
...
@@ -412,8 +412,8 @@ extern "C" {
/**< Enable the TX checksum offload
* This option defaults to enabled (set) */
#define XEMACPS_JUMBO_ENABLE_OPTION
0x00004000U
#define XEMACPS_SGMII_ENABLE_OPTION
0x00008000U
#define XEMACPS_JUMBO_ENABLE_OPTION
0x00004000U
#define XEMACPS_SGMII_ENABLE_OPTION
0x00008000U
#define XEMACPS_DEFAULT_OPTIONS \
((u32)XEMACPS_FLOW_CONTROL_OPTION | \
...
...
@@ -463,10 +463,10 @@ extern "C" {
/* DMACR Bust length hash defines */
#define XEMACPS_SINGLE_BURST
0x00000001
#define XEMACPS_4BYTE_BURST
0x00000004
#define XEMACPS_8BYTE_BURST
0x00000008
#define XEMACPS_16BYTE_BURST
0x00000010
#define XEMACPS_SINGLE_BURST
0x00000001
#define XEMACPS_4BYTE_BURST
0x00000004
#define XEMACPS_8BYTE_BURST
0x00000008
#define XEMACPS_16BYTE_BURST
0x00000010
/**************************** Type Definitions ******************************/
...
...
@@ -507,12 +507,12 @@ typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
* This typedef contains configuration information for a device.
*/
typedef
struct
{
u16
DeviceId
;
/**< Unique ID of device */
UINTPTR
BaseAddress
;
/**< Physical base address of IPIF registers */
u8
IsCacheCoherent
;
/**< Applicable only to A53 in EL1 mode;
u16
DeviceId
;
/**< Unique ID of device */
UINTPTR
BaseAddress
;
/**< Physical base address of IPIF registers */
u8
IsCacheCoherent
;
/**< Applicable only to A53 in EL1 mode;
* describes whether Cache Coherent or not */
#if defined (XCLOCKING)
u32
RefClk
;
/**< Input clock */
u32
RefClk
;
/**< Input clock */
#endif
}
XEmacPs_Config
;
...
...
@@ -523,26 +523,26 @@ typedef struct {
* to a structure of this type is then passed to the driver API functions.
*/
typedef
struct
XEmacPs_Instance
{
XEmacPs_Config
Config
;
/* Hardware configuration */
u32
IsStarted
;
/* Device is currently started */
u32
IsReady
;
/* Device is initialized and ready */
u32
Options
;
/* Current options word */
XEmacPs_BdRing
TxBdRing
;
/* Transmit BD ring */
XEmacPs_BdRing
RxBdRing
;
/* Receive BD ring */
XEmacPs_Handler
SendHandler
;
XEmacPs_Handler
RecvHandler
;
void
*
SendRef
;
void
*
RecvRef
;
XEmacPs_ErrHandler
ErrorHandler
;
void
*
ErrorRef
;
u32
Version
;
u32
RxBufMask
;
u32
MaxMtuSize
;
u32
MaxFrameSize
;
u32
MaxVlanFrameSize
;
XEmacPs_Config
Config
;
/* Hardware configuration */
u32
IsStarted
;
/* Device is currently started */
u32
IsReady
;
/* Device is initialized and ready */
u32
Options
;
/* Current options word */
XEmacPs_BdRing
TxBdRing
;
/* Transmit BD ring */
XEmacPs_BdRing
RxBdRing
;
/* Receive BD ring */
XEmacPs_Handler
SendHandler
;
XEmacPs_Handler
RecvHandler
;
void
*
SendRef
;
void
*
RecvRef
;
XEmacPs_ErrHandler
ErrorHandler
;
void
*
ErrorRef
;
u32
Version
;
u32
RxBufMask
;
u32
MaxMtuSize
;
u32
MaxFrameSize
;
u32
MaxVlanFrameSize
;
}
XEmacPs
;
...
...
@@ -598,8 +598,8 @@ typedef struct XEmacPs_Instance {
*
*****************************************************************************/
#define XEmacPs_IntEnable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IER_OFFSET, \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IER_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
...
...
@@ -619,8 +619,8 @@ typedef struct XEmacPs_Instance {
*
*****************************************************************************/
#define XEmacPs_IntDisable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IDR_OFFSET, \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IDR_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
...
...
@@ -640,8 +640,8 @@ typedef struct XEmacPs_Instance {
*
*****************************************************************************/
#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IER_OFFSET, \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IER_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
...
...
@@ -661,8 +661,8 @@ typedef struct XEmacPs_Instance {
*
*****************************************************************************/
#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IDR_OFFSET, \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IDR_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
...
...
@@ -750,7 +750,7 @@ typedef struct XEmacPs_Instance {
* @note
*
* Signature: void XEmacPs_SetRXWatermark(XEmacPs *InstancePtr, u16 High,
*
u16 Low)
*
u16 Low)
*
*****************************************************************************/
#define XEmacPs_SetRXWatermark(InstancePtr, High, Low) \
...
...
@@ -797,7 +797,7 @@ XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
* DMA only and FIFO is not supported. This DMA does not support coalescing.
*/
LONG
XEmacPs_SetHandler
(
XEmacPs
*
InstancePtr
,
u32
HandlerType
,
void
*
FuncPointer
,
void
*
CallBackRef
);
void
*
FuncPointer
,
void
*
CallBackRef
);
void
XEmacPs_IntrHandler
(
void
*
XEmacPsPtr
);
/*
...
...
@@ -816,7 +816,7 @@ void XEmacPs_ClearHash(XEmacPs *InstancePtr);
void
XEmacPs_GetHash
(
XEmacPs
*
InstancePtr
,
void
*
AddressPtr
);
void
XEmacPs_SetMdioDivisor
(
XEmacPs
*
InstancePtr
,
XEmacPs_MdcDiv
Divisor
);
XEmacPs_MdcDiv
Divisor
);
void
XEmacPs_SetOperatingSpeed
(
XEmacPs
*
InstancePtr
,
u16
Speed
);
u16
XEmacPs_GetOperatingSpeed
(
XEmacPs
*
InstancePtr
);
LONG
XEmacPs_PhyRead
(
XEmacPs
*
InstancePtr
,
u32
PhyAddress
,
...
...
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_bdring.c
浏览文件 @
97b6f10a
此差异已折叠。
点击以展开。
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_bdring.h
浏览文件 @
97b6f10a
...
...
@@ -40,28 +40,28 @@ extern "C" {
/** This is an internal structure used to maintain the DMA list */
typedef
struct
{
UINTPTR
PhysBaseAddr
;
/**< Physical address of 1st BD in list */
UINTPTR
BaseBdAddr
;
/**< Virtual address of 1st BD in list */
UINTPTR
HighBdAddr
;
/**< Virtual address of last BD in the list */
u32
Length
;
/**< Total size of ring in bytes */
u32
RunState
;
/**< Flag to indicate DMA is started */
u32
Separation
;
/**< Number of bytes between the starting address
UINTPTR
PhysBaseAddr
;
/**< Physical address of 1st BD in list */
UINTPTR
BaseBdAddr
;
/**< Virtual address of 1st BD in list */
UINTPTR
HighBdAddr
;
/**< Virtual address of last BD in the list */
u32
Length
;
/**< Total size of ring in bytes */
u32
RunState
;
/**< Flag to indicate DMA is started */
u32
Separation
;
/**< Number of bytes between the starting address
of adjacent BDs */
XEmacPs_Bd
*
FreeHead
;
XEmacPs_Bd
*
FreeHead
;
/**< First BD in the free group */
XEmacPs_Bd
*
PreHead
;
/**< First BD in the pre-work group */
XEmacPs_Bd
*
HwHead
;
/**< First BD in the work group */
XEmacPs_Bd
*
HwTail
;
/**< Last BD in the work group */
XEmacPs_Bd
*
PostHead
;
XEmacPs_Bd
*
PreHead
;
/**< First BD in the pre-work group */
XEmacPs_Bd
*
HwHead
;
/**< First BD in the work group */
XEmacPs_Bd
*
HwTail
;
/**< Last BD in the work group */
XEmacPs_Bd
*
PostHead
;
/**< First BD in the post-work group */
XEmacPs_Bd
*
BdaRestart
;
XEmacPs_Bd
*
BdaRestart
;
/**< BDA to load when channel is started */
volatile
u32
HwCnt
;
/**< Number of BDs in work group */
u32
PreCnt
;
/**< Number of BDs in pre-work group */
u32
FreeCnt
;
/**< Number of allocatable BDs in the free group */
u32
PostCnt
;
/**< Number of BDs in post-work group */
u32
AllCnt
;
/**< Total Number of BDs for channel */
volatile
u32
HwCnt
;
/**< Number of BDs in work group */
u32
PreCnt
;
/**< Number of BDs in pre-work group */
u32
FreeCnt
;
/**< Number of allocatable BDs in the free group */
u32
PostCnt
;
/**< Number of BDs in post-work group */
u32
AllCnt
;
/**< Total Number of BDs for channel */
}
XEmacPs_BdRing
;
...
...
@@ -195,9 +195,9 @@ LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
LONG
XEmacPs_BdRingUnAlloc
(
XEmacPs_BdRing
*
RingPtr
,
u32
NumBd
,
XEmacPs_Bd
*
BdSetPtr
);
LONG
XEmacPs_BdRingToHw
(
XEmacPs_BdRing
*
RingPtr
,
u32
NumBd
,
XEmacPs_Bd
*
BdSetPtr
);
XEmacPs_Bd
*
BdSetPtr
);
LONG
XEmacPs_BdRingFree
(
XEmacPs_BdRing
*
RingPtr
,
u32
NumBd
,
XEmacPs_Bd
*
BdSetPtr
);
XEmacPs_Bd
*
BdSetPtr
);
u32
XEmacPs_BdRingFromHwTx
(
XEmacPs_BdRing
*
RingPtr
,
u32
BdLimit
,
XEmacPs_Bd
**
BdSetPtr
);
u32
XEmacPs_BdRingFromHwRx
(
XEmacPs_BdRing
*
RingPtr
,
u32
BdLimit
,
...
...
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_control.c
浏览文件 @
97b6f10a
此差异已折叠。
点击以展开。
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_g.c
浏览文件 @
97b6f10a
...
...
@@ -6,9 +6,9 @@
* DO NOT EDIT.
*
* Copyright (C) 2010-2021 Xilinx, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
* SPDX-License-Identifier: MIT
*
*
* Description: Driver configuration
*
*******************************************************************/
...
...
@@ -23,9 +23,9 @@
XEmacPs_Config
XEmacPs_ConfigTable
[
XPAR_XEMACPS_NUM_INSTANCES
]
=
{
{
XPAR_PSU_ETHERNET_3_DEVICE_ID
,
XPAR_PSU_ETHERNET_3_BASEADDR
,
XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT
XPAR_PSU_ETHERNET_3_DEVICE_ID
,
XPAR_PSU_ETHERNET_3_BASEADDR
,
XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT
}
};
...
...
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_hw.c
浏览文件 @
97b6f10a
...
...
@@ -44,11 +44,11 @@
* This function perform the reset sequence to the given emacps interface by
* configuring the appropriate control bits in the emacps specific registers.
* the emacps reset sequence involves the following steps
*
Disable all the interuupts
*
Clear the status registers
*
Disable Rx and Tx engines
*
Update the Tx and Rx descriptor queue registers with reset values
*
Update the other relevant control registers with reset value
*
Disable all the interuupts
*
Clear the status registers
*
Disable Rx and Tx engines
*
Update the Tx and Rx descriptor queue registers with reset values
*
Update the other relevant control registers with reset value
*
* @param BaseAddr of the interface
*
...
...
@@ -60,38 +60,38 @@
******************************************************************************/
void
XEmacPs_ResetHw
(
u32
BaseAddr
)
{
u32
RegVal
;
u32
RegVal
;
/* Disable the interrupts */
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_IDR_OFFSET
,
0x0U
);
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_IDR_OFFSET
,
0x0U
);
/* Stop transmission,disable loopback and Stop tx and Rx engines */
RegVal
=
XEmacPs_ReadReg
(
BaseAddr
,
XEMACPS_NWCTRL_OFFSET
);
RegVal
&=
~
((
u32
)
XEMACPS_NWCTRL_TXEN_MASK
|
RegVal
=
XEmacPs_ReadReg
(
BaseAddr
,
XEMACPS_NWCTRL_OFFSET
);
RegVal
&=
~
((
u32
)
XEMACPS_NWCTRL_TXEN_MASK
|
(
u32
)
XEMACPS_NWCTRL_RXEN_MASK
|
(
u32
)
XEMACPS_NWCTRL_HALTTX_MASK
|
(
u32
)
XEMACPS_NWCTRL_LOOPEN_MASK
);
/* Clear the statistic registers, flush the packets in DPRAM*/
RegVal
|=
(
XEMACPS_NWCTRL_STATCLR_MASK
|
XEMACPS_NWCTRL_FLUSH_DPRAM_MASK
);
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_NWCTRL_OFFSET
,
RegVal
);
RegVal
|=
(
XEMACPS_NWCTRL_STATCLR_MASK
|
XEMACPS_NWCTRL_FLUSH_DPRAM_MASK
);
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_NWCTRL_OFFSET
,
RegVal
);
/* Clear the interrupt status */
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_ISR_OFFSET
,
XEMACPS_IXR_ALL_MASK
);
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_ISR_OFFSET
,
XEMACPS_IXR_ALL_MASK
);
/* Clear the tx status */
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_TXSR_OFFSET
,(
XEMACPS_TXSR_ERROR_MASK
|
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_TXSR_OFFSET
,(
XEMACPS_TXSR_ERROR_MASK
|
(
u32
)
XEMACPS_TXSR_TXCOMPL_MASK
|
(
u32
)
XEMACPS_TXSR_TXGO_MASK
));
/* Clear the rx status */
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_RXSR_OFFSET
,
XEMACPS_RXSR_FRAMERX_MASK
);
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_RXSR_OFFSET
,
XEMACPS_RXSR_FRAMERX_MASK
);
/* Clear the tx base address */
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_TXQBASE_OFFSET
,
0x0U
);
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_TXQBASE_OFFSET
,
0x0U
);
/* Clear the rx base address */
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_RXQBASE_OFFSET
,
0x0U
);
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_RXQBASE_OFFSET
,
0x0U
);
/* Update the network config register with reset value */
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_NWCFG_OFFSET
,
XEMACPS_NWCFG_RESET_MASK
);
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_NWCFG_OFFSET
,
XEMACPS_NWCFG_RESET_MASK
);
/* Update the hash address registers with reset value */
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_HASHL_OFFSET
,
0x0U
);
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_HASHH_OFFSET
,
0x0U
);
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_HASHL_OFFSET
,
0x0U
);
XEmacPs_WriteReg
(
BaseAddr
,
XEMACPS_HASHH_OFFSET
,
0x0U
);
}
/** @} */
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_hw.h
浏览文件 @
97b6f10a
...
...
@@ -89,7 +89,7 @@ extern "C" {
* @{
*/
typedef
enum
{
MDC_DIV_8
=
0U
,
MDC_DIV_16
,
MDC_DIV_32
,
MDC_DIV_48
,
MDC_DIV_64
,
MDC_DIV_96
,
MDC_DIV_128
,
MDC_DIV_224
MDC_DIV_64
,
MDC_DIV_96
,
MDC_DIV_128
,
MDC_DIV_224
}
XEmacPs_MdcDiv
;
/*@}*/
...
...
@@ -276,29 +276,29 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
nanosecond counter */
#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U
/**< Interrupt Q1 Status
reg */
reg */
#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U
/**< TX Q1 Base address
reg */
reg */
#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U
/**< RX Q1 Base address
reg */
reg */
#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U
/**< MSB Buffer TX Q Base
reg */
reg */
#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U
/**< MSB Buffer RX Q Base
reg */
reg */
#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U
/**< Interrupt Q1 Enable
reg */
reg */
#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U
/**< Interrupt Q1 Disable
reg */
reg */
#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U
/**< Interrupt Q1 Mask
reg */
reg */
/* Define some bit positions for registers. */
/** @name network control register bit definitions
* @{
*/
#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK
0x00040000U
/**< Flush a packet from
Rx SRAM */
#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK
0x00040000U
/**< Flush a packet from
Rx SRAM */
#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U
/**< Transmit zero quantum
pause frame */
#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U
/**< Transmit pause frame */
...
...
@@ -382,23 +382,23 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
/** @name DMA control register bit definitions
* @{
*/
#define XEMACPS_DMACR_ADDR_WIDTH_64
0x40000000U
/**< 64 bit address bus */
#define XEMACPS_DMACR_TXEXTEND_MASK
0x20000000U
/**< Tx Extended desc mode */
#define XEMACPS_DMACR_RXEXTEND_MASK
0x10000000U
/**< Rx Extended desc mode */
#define XEMACPS_DMACR_RXBUF_MASK
0x00FF0000U
/**< Mask bit for RX buffer
size */
#define XEMACPS_DMACR_RXBUF_SHIFT
16U
/**< Shift bit for RX buffer
size */
#define XEMACPS_DMACR_TCPCKSUM_MASK
0x00000800U
/**< enable/disable TX
#define XEMACPS_DMACR_ADDR_WIDTH_64
0x40000000U
/**< 64 bit address bus */
#define XEMACPS_DMACR_TXEXTEND_MASK
0x20000000U
/**< Tx Extended desc mode */
#define XEMACPS_DMACR_RXEXTEND_MASK
0x10000000U
/**< Rx Extended desc mode */
#define XEMACPS_DMACR_RXBUF_MASK
0x00FF0000U
/**< Mask bit for RX buffer
size */
#define XEMACPS_DMACR_RXBUF_SHIFT
16U
/**< Shift bit for RX buffer
size */
#define XEMACPS_DMACR_TCPCKSUM_MASK
0x00000800U
/**< enable/disable TX
checksum offload */
#define XEMACPS_DMACR_TXSIZE_MASK
0x00000400U
/**< TX buffer memory size */
#define XEMACPS_DMACR_RXSIZE_MASK
0x00000300U
/**< RX buffer memory size */
#define XEMACPS_DMACR_ENDIAN_MASK
0x00000080U
/**< endian configuration */
#define XEMACPS_DMACR_BLENGTH_MASK
0x0000001FU
/**< buffer burst length */
#define XEMACPS_DMACR_SINGLE_AHB_BURST
0x00000001U
/**< single AHB bursts */
#define XEMACPS_DMACR_INCR4_AHB_BURST
0x00000004U
/**< 4 bytes AHB bursts */
#define XEMACPS_DMACR_INCR8_AHB_BURST
0x00000008U
/**< 8 bytes AHB bursts */
#define XEMACPS_DMACR_INCR16_AHB_BURST
0x00000010U
/**< 16 bytes AHB bursts */
#define XEMACPS_DMACR_TXSIZE_MASK
0x00000400U
/**< TX buffer memory size */
#define XEMACPS_DMACR_RXSIZE_MASK
0x00000300U
/**< RX buffer memory size */
#define XEMACPS_DMACR_ENDIAN_MASK
0x00000080U
/**< endian configuration */
#define XEMACPS_DMACR_BLENGTH_MASK
0x0000001FU
/**< buffer burst length */
#define XEMACPS_DMACR_SINGLE_AHB_BURST
0x00000001U
/**< single AHB bursts */
#define XEMACPS_DMACR_INCR4_AHB_BURST
0x00000004U
/**< 4 bytes AHB bursts */
#define XEMACPS_DMACR_INCR8_AHB_BURST
0x00000008U
/**< 8 bytes AHB bursts */
#define XEMACPS_DMACR_INCR16_AHB_BURST
0x00000010U
/**< 16 bytes AHB bursts */
/*@}*/
/** @name transmit status register bit definitions
...
...
@@ -435,7 +435,7 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
(u32)XEMACPS_RXSR_RXOVR_MASK | \
(u32)XEMACPS_RXSR_BUFFNA_MASK)
#define XEMACPS_SR_ALL_MASK
0xFFFFFFFFU
/**< Mask for full register */
#define XEMACPS_SR_ALL_MASK
0xFFFFFFFFU
/**< Mask for full register */
/*@}*/
...
...
@@ -443,8 +443,8 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
* @name Interrupt Q1 status register bit definitions
* @{
*/
#define XEMACPS_INTQ1SR_TXCOMPL_MASK
0x00000080U
/**< Transmit completed OK */
#define XEMACPS_INTQ1SR_TXERR_MASK
0x00000040U
/**< Transmit AMBA Error */
#define XEMACPS_INTQ1SR_TXCOMPL_MASK
0x00000080U
/**< Transmit completed OK */
#define XEMACPS_INTQ1SR_TXERR_MASK
0x00000040U
/**< Transmit AMBA Error */
#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
(u32)XEMACPS_INTQ1SR_TXERR_MASK)
...
...
@@ -457,15 +457,15 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
* XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
* @{
*/
#define XEMACPS_IXR_PTPPSTX_MASK
0x02000000U
/**< PTP Pdelay_resp TXed */
#define XEMACPS_IXR_PTPPDRTX_MASK
0x01000000U
/**< PTP Pdelay_req TXed */
#define XEMACPS_IXR_PTPPSRX_MASK
0x00800000U
/**< PTP Pdelay_resp RXed */
#define XEMACPS_IXR_PTPPDRRX_MASK
0x00400000U
/**< PTP Pdelay_req RXed */
#define XEMACPS_IXR_PTPPSTX_MASK
0x02000000U
/**< PTP Pdelay_resp TXed */
#define XEMACPS_IXR_PTPPDRTX_MASK
0x01000000U
/**< PTP Pdelay_req TXed */
#define XEMACPS_IXR_PTPPSRX_MASK
0x00800000U
/**< PTP Pdelay_resp RXed */
#define XEMACPS_IXR_PTPPDRRX_MASK
0x00400000U
/**< PTP Pdelay_req RXed */
#define XEMACPS_IXR_PTPSTX_MASK
0x00200000U
/**< PTP Sync TXed */
#define XEMACPS_IXR_PTPDRTX_MASK
0x00100000U
/**< PTP Delay_req TXed */
#define XEMACPS_IXR_PTPSRX_MASK
0x00080000U
/**< PTP Sync RXed */
#define XEMACPS_IXR_PTPDRRX_MASK
0x00040000U
/**< PTP Delay_req RXed */
#define XEMACPS_IXR_PTPSTX_MASK
0x00200000U
/**< PTP Sync TXed */
#define XEMACPS_IXR_PTPDRTX_MASK
0x00100000U
/**< PTP Delay_req TXed */
#define XEMACPS_IXR_PTPSRX_MASK
0x00080000U
/**< PTP Sync RXed */
#define XEMACPS_IXR_PTPDRRX_MASK
0x00040000U
/**< PTP Delay_req RXed */
#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U
/**< Pause frame transmitted */
#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U
/**< Pause time has reached
...
...
@@ -511,9 +511,9 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
/** @name RX watermark bit definitions
* @{
*/
#define XEMACPS_RXWM_HIGH_MASK
0x0000FFFFU
/**< RXWM high mask */
#define XEMACPS_RXWM_LOW_MASK
0xFFFF0000U
/**< RXWM low mask */
#define XEMACPS_RXWM_LOW_SHFT_MSK
16U
/**< Shift for RXWM low */
#define XEMACPS_RXWM_HIGH_MASK
0x0000FFFFU
/**< RXWM high mask */
#define XEMACPS_RXWM_LOW_MASK
0xFFFF0000U
/**< RXWM low mask */
#define XEMACPS_RXWM_LOW_SHFT_MSK
16U
/**< Shift for RXWM low */
/*@}*/
/* Transmit buffer descriptor status words offset
...
...
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_intr.c
浏览文件 @
97b6f10a
...
...
@@ -77,34 +77,34 @@
*
*****************************************************************************/
LONG
XEmacPs_SetHandler
(
XEmacPs
*
InstancePtr
,
u32
HandlerType
,
void
*
FuncPointer
,
void
*
CallBackRef
)
void
*
FuncPointer
,
void
*
CallBackRef
)
{
LONG
Status
;
Xil_AssertNonvoid
(
InstancePtr
!=
NULL
);
Xil_AssertNonvoid
(
FuncPointer
!=
NULL
);
Xil_AssertNonvoid
(
InstancePtr
->
IsReady
==
(
u32
)
XIL_COMPONENT_IS_READY
);
switch
(
HandlerType
)
{
case
XEMACPS_HANDLER_DMASEND
:
Status
=
(
LONG
)(
XST_SUCCESS
);
InstancePtr
->
SendHandler
=
((
XEmacPs_Handler
)(
void
*
)
FuncPointer
);
InstancePtr
->
SendRef
=
CallBackRef
;
break
;
case
XEMACPS_HANDLER_DMARECV
:
Status
=
(
LONG
)(
XST_SUCCESS
);
InstancePtr
->
RecvHandler
=
((
XEmacPs_Handler
)(
void
*
)
FuncPointer
);
InstancePtr
->
RecvRef
=
CallBackRef
;
break
;
case
XEMACPS_HANDLER_ERROR
:
Status
=
(
LONG
)(
XST_SUCCESS
);
InstancePtr
->
ErrorHandler
=
((
XEmacPs_ErrHandler
)(
void
*
)
FuncPointer
);
InstancePtr
->
ErrorRef
=
CallBackRef
;
break
;
default:
Status
=
(
LONG
)(
XST_INVALID_PARAM
);
break
;
LONG
Status
;
Xil_AssertNonvoid
(
InstancePtr
!=
NULL
);
Xil_AssertNonvoid
(
FuncPointer
!=
NULL
);
Xil_AssertNonvoid
(
InstancePtr
->
IsReady
==
(
u32
)
XIL_COMPONENT_IS_READY
);
switch
(
HandlerType
)
{
case
XEMACPS_HANDLER_DMASEND
:
Status
=
(
LONG
)(
XST_SUCCESS
);
InstancePtr
->
SendHandler
=
((
XEmacPs_Handler
)(
void
*
)
FuncPointer
);
InstancePtr
->
SendRef
=
CallBackRef
;
break
;
case
XEMACPS_HANDLER_DMARECV
:
Status
=
(
LONG
)(
XST_SUCCESS
);
InstancePtr
->
RecvHandler
=
((
XEmacPs_Handler
)(
void
*
)
FuncPointer
);
InstancePtr
->
RecvRef
=
CallBackRef
;
break
;
case
XEMACPS_HANDLER_ERROR
:
Status
=
(
LONG
)(
XST_SUCCESS
);
InstancePtr
->
ErrorHandler
=
((
XEmacPs_ErrHandler
)(
void
*
)
FuncPointer
);
InstancePtr
->
ErrorRef
=
CallBackRef
;
break
;
default:
Status
=
(
LONG
)(
XST_INVALID_PARAM
);
break
;
}
return
Status
;
return
Status
;
}
/*****************************************************************************/
...
...
@@ -121,93 +121,93 @@ LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
******************************************************************************/
void
XEmacPs_IntrHandler
(
void
*
XEmacPsPtr
)
{
u32
RegISR
;
u32
RegSR
;
u32
RegCtrl
;
u32
RegQ1ISR
=
0U
;
XEmacPs
*
InstancePtr
=
(
XEmacPs
*
)
XEmacPsPtr
;
u32
RegISR
;
u32
RegSR
;
u32
RegCtrl
;
u32
RegQ1ISR
=
0U
;
XEmacPs
*
InstancePtr
=
(
XEmacPs
*
)
XEmacPsPtr
;
Xil_AssertVoid
(
InstancePtr
!=
NULL
);
Xil_AssertVoid
(
InstancePtr
->
IsReady
==
(
u32
)
XIL_COMPONENT_IS_READY
);
Xil_AssertVoid
(
InstancePtr
!=
NULL
);
Xil_AssertVoid
(
InstancePtr
->
IsReady
==
(
u32
)
XIL_COMPONENT_IS_READY
);
/* This ISR will try to handle as many interrupts as it can in a single
* call. However, in most of the places where the user's error handler
* is called, this ISR exits because it is expected that the user will
* reset the device in nearly all instances.
*/
RegISR
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
RegISR
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_ISR_OFFSET
);
/* Read Transmit Q1 ISR */
if
(
InstancePtr
->
Version
>
2
)
RegQ1ISR
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
if
(
InstancePtr
->
Version
>
2
)
RegQ1ISR
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_INTQ1_STS_OFFSET
);
/* Clear the interrupt status register */
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_ISR_OFFSET
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_ISR_OFFSET
,
RegISR
);
/* Receive complete interrupt */
if
((
RegISR
&
XEMACPS_IXR_FRAMERX_MASK
)
!=
0x00000000U
)
{
if
((
RegISR
&
XEMACPS_IXR_FRAMERX_MASK
)
!=
0x00000000U
)
{
/* Clear RX status register RX complete indication but preserve
* error bits if there is any */
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_RXSR_OFFSET
,
((
u32
)
XEMACPS_RXSR_FRAMERX_MASK
|
(
u32
)
XEMACPS_RXSR_BUFFNA_MASK
));
InstancePtr
->
RecvHandler
(
InstancePtr
->
RecvRef
);
InstancePtr
->
RecvHandler
(
InstancePtr
->
RecvRef
);
}
/* Transmit Q1 complete interrupt */
if
((
InstancePtr
->
Version
>
2
)
&&
if
((
InstancePtr
->
Version
>
2
)
&&
((
RegQ1ISR
&
XEMACPS_INTQ1SR_TXCOMPL_MASK
)
!=
0x00000000U
))
{
/* Clear TX status register TX complete indication but preserve
* error bits if there is any */
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_INTQ1_STS_OFFSET
,
XEMACPS_INTQ1SR_TXCOMPL_MASK
);
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_TXSR_OFFSET
,
((
u32
)
XEMACPS_TXSR_TXCOMPL_MASK
|
(
u32
)
XEMACPS_TXSR_USEDREAD_MASK
));
InstancePtr
->
SendHandler
(
InstancePtr
->
SendRef
);
InstancePtr
->
SendHandler
(
InstancePtr
->
SendRef
);
}
/* Transmit complete interrupt */
if
((
RegISR
&
XEMACPS_IXR_TXCOMPL_MASK
)
!=
0x00000000U
)
{
if
((
RegISR
&
XEMACPS_IXR_TXCOMPL_MASK
)
!=
0x00000000U
)
{
/* Clear TX status register TX complete indication but preserve
* error bits if there is any */
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_TXSR_OFFSET
,
((
u32
)
XEMACPS_TXSR_TXCOMPL_MASK
|
(
u32
)
XEMACPS_TXSR_USEDREAD_MASK
));
InstancePtr
->
SendHandler
(
InstancePtr
->
SendRef
);
InstancePtr
->
SendHandler
(
InstancePtr
->
SendRef
);
}
/* Receive error conditions interrupt */
if
((
RegISR
&
XEMACPS_IXR_RX_ERR_MASK
)
!=
0x00000000U
)
{
if
((
RegISR
&
XEMACPS_IXR_RX_ERR_MASK
)
!=
0x00000000U
)
{
/* Clear RX status register */
RegSR
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
RegSR
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_RXSR_OFFSET
);
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_RXSR_OFFSET
,
RegSR
);
/* Fix for CR # 692702. Write to bit 18 of net_ctrl
* register to flush a packet out of Rx SRAM upon
* an error for receive buffer not available. */
if
((
RegISR
&
XEMACPS_IXR_RXUSED_MASK
)
!=
0x00000000U
)
{
RegCtrl
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCTRL_OFFSET
);
RegCtrl
|=
(
u32
)
XEMACPS_NWCTRL_FLUSH_DPRAM_MASK
;
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCTRL_OFFSET
,
RegCtrl
);
if
((
RegISR
&
XEMACPS_IXR_RXUSED_MASK
)
!=
0x00000000U
)
{
RegCtrl
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCTRL_OFFSET
);
RegCtrl
|=
(
u32
)
XEMACPS_NWCTRL_FLUSH_DPRAM_MASK
;
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_NWCTRL_OFFSET
,
RegCtrl
);
}
if
(
RegSR
!=
0
)
{
InstancePtr
->
ErrorHandler
(
InstancePtr
->
ErrorRef
,
XEMACPS_RECV
,
RegSR
);
if
(
RegSR
!=
0
)
{
InstancePtr
->
ErrorHandler
(
InstancePtr
->
ErrorRef
,
XEMACPS_RECV
,
RegSR
);
}
}
...
...
@@ -220,9 +220,9 @@ void XEmacPs_IntrHandler(void *XEmacPsPtr)
((
RegQ1ISR
&
XEMACPS_INTQ1SR_TXERR_MASK
)
!=
0x00000000U
)
&&
((
RegQ1ISR
&
XEMACPS_INTQ1SR_TXCOMPL_MASK
)
!=
0x00000000U
))
{
/* Clear Interrupt Q1 status register */
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_INTQ1_STS_OFFSET
,
RegQ1ISR
);
InstancePtr
->
ErrorHandler
(
InstancePtr
->
ErrorRef
,
XEMACPS_SEND
,
InstancePtr
->
ErrorHandler
(
InstancePtr
->
ErrorRef
,
XEMACPS_SEND
,
RegQ1ISR
);
}
...
...
@@ -230,11 +230,11 @@ void XEmacPs_IntrHandler(void *XEmacPsPtr)
if
(((
RegISR
&
XEMACPS_IXR_TX_ERR_MASK
)
!=
0x00000000U
)
&&
(
!
(
RegISR
&
XEMACPS_IXR_TXCOMPL_MASK
)
!=
0x00000000U
))
{
/* Clear TX status register */
RegSR
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
RegSR
=
XEmacPs_ReadReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_TXSR_OFFSET
);
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEmacPs_WriteReg
(
InstancePtr
->
Config
.
BaseAddress
,
XEMACPS_TXSR_OFFSET
,
RegSR
);
InstancePtr
->
ErrorHandler
(
InstancePtr
->
ErrorRef
,
XEMACPS_SEND
,
InstancePtr
->
ErrorHandler
(
InstancePtr
->
ErrorRef
,
XEMACPS_SEND
,
RegSR
);
}
...
...
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/xemacps_sinit.c
浏览文件 @
97b6f10a
...
...
@@ -56,16 +56,16 @@ extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
******************************************************************************/
XEmacPs_Config
*
XEmacPs_LookupConfig
(
u16
DeviceId
)
{
XEmacPs_Config
*
CfgPtr
=
NULL
;
u32
i
;
XEmacPs_Config
*
CfgPtr
=
NULL
;
u32
i
;
for
(
i
=
0U
;
i
<
(
u32
)
XPAR_XEMACPS_NUM_INSTANCES
;
i
++
)
{
if
(
XEmacPs_ConfigTable
[
i
].
DeviceId
==
DeviceId
)
{
CfgPtr
=
&
XEmacPs_ConfigTable
[
i
];
break
;
for
(
i
=
0U
;
i
<
(
u32
)
XPAR_XEMACPS_NUM_INSTANCES
;
i
++
)
{
if
(
XEmacPs_ConfigTable
[
i
].
DeviceId
==
DeviceId
)
{
CfgPtr
=
&
XEmacPs_ConfigTable
[
i
];
break
;
}
}
return
(
XEmacPs_Config
*
)(
CfgPtr
);
return
(
XEmacPs_Config
*
)(
CfgPtr
);
}
/** @} */
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.c
浏览文件 @
97b6f10a
此差异已折叠。
点击以展开。
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops.h
浏览文件 @
97b6f10a
...
...
@@ -67,10 +67,10 @@
* for output pins on all banks during initialization.
* 1.02a hk 08/22/13 Added low level reset API
* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
* 2.2
sk 10/13/14 Used Pin number in Bank instead of pin number
* 2.2
sk 10/13/14 Used Pin number in Bank instead of pin number
* passed to APIs. CR# 822636
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1
kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
* 3.1
kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* ms 04/05/17 Added tabspace for return statements in functions of
...
...
@@ -89,9 +89,9 @@
* 3.5 sne 03/14/19 Added Versal support.
* 3.6 mus 04/05/19 Replaced XPLAT_versal macro with XPLAT_VERSAL, to be in
* sync with standalone BSP
* 3.6
sne 06/12/19 Fixed IAR compiler warning.
* 3.6
sne 06/12/19 Fixed IAR compiler warning.
* 3.6 sne 08/14/19 Added interrupt handler support on versal.
* 3.7
sne 12/04/19 Reverted versal examples support.
* 3.7
sne 12/04/19 Reverted versal examples support.
*
* </pre>
*
...
...
@@ -116,43 +116,43 @@ extern "C" {
* The following constants define the interrupt types that can be set for each
* GPIO pin.
*/
#define XGPIOPS_IRQ_TYPE_EDGE_RISING
0x00U
/**< Interrupt on Rising edge */
#define XGPIOPS_IRQ_TYPE_EDGE_FALLING
0x01U
/**< Interrupt Falling edge */
#define XGPIOPS_IRQ_TYPE_EDGE_BOTH
0x02U
/**< Interrupt on both edges */
#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH
0x03U
/**< Interrupt on high level */
#define XGPIOPS_IRQ_TYPE_LEVEL_LOW
0x04U
/**< Interrupt on low level */
#define XGPIOPS_IRQ_TYPE_EDGE_RISING
0x00U
/**< Interrupt on Rising edge */
#define XGPIOPS_IRQ_TYPE_EDGE_FALLING
0x01U
/**< Interrupt Falling edge */
#define XGPIOPS_IRQ_TYPE_EDGE_BOTH
0x02U
/**< Interrupt on both edges */
#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH
0x03U
/**< Interrupt on high level */
#define XGPIOPS_IRQ_TYPE_LEVEL_LOW
0x04U
/**< Interrupt on low level */
/*@}*/
#define XGPIOPS_BANK_MAX_PINS (u32)32
/**< Max pins in a GPIO bank */
#define XGPIOPS_BANK0
0x00U
/**< GPIO Bank 0 */
#define XGPIOPS_BANK1
0x01U
/**< GPIO Bank 1 */
#define XGPIOPS_BANK2
0x02U
/**< GPIO Bank 2 */
#define XGPIOPS_BANK3
0x03U
/**< GPIO Bank 3 */
#define XGPIOPS_BANK0
0x00U
/**< GPIO Bank 0 */
#define XGPIOPS_BANK1
0x01U
/**< GPIO Bank 1 */
#define XGPIOPS_BANK2
0x02U
/**< GPIO Bank 2 */
#define XGPIOPS_BANK3
0x03U
/**< GPIO Bank 3 */
#ifdef XPAR_PSU_GPIO_0_BASEADDR
#define XGPIOPS_BANK4
0x04U
/**< GPIO Bank 4 */
#define XGPIOPS_BANK5
0x05U
/**< GPIO Bank 5 */
#define XGPIOPS_BANK4
0x04U
/**< GPIO Bank 4 */
#define XGPIOPS_BANK5
0x05U
/**< GPIO Bank 5 */
#endif
#define XGPIOPS_MAX_BANKS_ZYNQMP
0x06U
/**< Max banks in a
*
Zynq Ultrascale+ MP GPIO device
#define XGPIOPS_MAX_BANKS_ZYNQMP
0x06U
/**< Max banks in a
*
Zynq Ultrascale+ MP GPIO device
*/
#define XGPIOPS_MAX_BANKS
0x04U
/**< Max banks in a Zynq GPIO device */
#define XGPIOPS_MAX_BANKS
0x04U
/**< Max banks in a Zynq GPIO device */
#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174
/**< Max pins in the
*
Zynq Ultrascale+ MP GPIO device
*
Zynq Ultrascale+ MP GPIO device
* 0 - 25, Bank 0
* 26 - 51, Bank 1
*
52 - 77, Bank 2
*
78 - 109, Bank 3
*
110 - 141, Bank 4
*
142 - 173, Bank 5
*
52 - 77, Bank 2
*
78 - 109, Bank 3
*
110 - 141, Bank 4
*
142 - 173, Bank 5
*/
#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118
/**< Max pins in the Zynq GPIO device
* 0 - 31, Bank 0
* 32 - 53, Bank 1
*
54 - 85, Bank 2
*
86 - 117, Bank 3
*
54 - 85, Bank 2
*
86 - 117, Bank 3
*/
/**************************** Type Definitions *******************************/
...
...
@@ -165,13 +165,13 @@ extern "C" {
* driven mode. The handler executes in an interrupt context such that minimal
* processing should be performed.
*
* @param
CallBackRef is a callback reference passed in by the upper layer
*
when setting the callback functions for a GPIO bank. It is
*
passed back to the upper layer when the callback is invoked. Its
*
type is not important to the driver component, so it is a void
*
pointer.
* @param
Bank is the bank for which the interrupt status has changed.
* @param
Status is the Interrupt status of the GPIO bank.
* @param
CallBackRef is a callback reference passed in by the upper layer
*
when setting the callback functions for a GPIO bank. It is
*
passed back to the upper layer when the callback is invoked. Its
*
type is not important to the driver component, so it is a void
*
pointer.
* @param
Bank is the bank for which the interrupt status has changed.
* @param
Status is the Interrupt status of the GPIO bank.
*
*****************************************************************************/
typedef
void
(
*
XGpioPs_Handler
)
(
void
*
CallBackRef
,
u32
Bank
,
u32
Status
);
...
...
@@ -180,8 +180,8 @@ typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
* This typedef contains configuration information for a device.
*/
typedef
struct
{
u16
DeviceId
;
/**< Unique ID of device */
u32
BaseAddr
;
/**< Register base address */
u16
DeviceId
;
/**< Unique ID of device */
u32
BaseAddr
;
/**< Register base address */
}
XGpioPs_Config
;
/**
...
...
@@ -190,13 +190,13 @@ typedef struct {
* to a variable of this type is then passed to the driver API functions.
*/
typedef
struct
{
XGpioPs_Config
GpioConfig
;
/**< Device configuration */
u32
IsReady
;
/**< Device is initialized and ready */
XGpioPs_Handler
Handler
;
/**< Status handlers for all banks */
void
*
CallBackRef
;
/**< Callback ref for bank handlers */
u32
Platform
;
/**< Platform data */
u32
MaxPinNum
;
/**< Max pins in the GPIO device */
u8
MaxBanks
;
/**< Max banks in a GPIO device */
XGpioPs_Config
GpioConfig
;
/**< Device configuration */
u32
IsReady
;
/**< Device is initialized and ready */
XGpioPs_Handler
Handler
;
/**< Status handlers for all banks */
void
*
CallBackRef
;
/**< Callback ref for bank handlers */
u32
Platform
;
/**< Platform data */
u32
MaxPinNum
;
/**< Max pins in the GPIO device */
u8
MaxBanks
;
/**< Max banks in a GPIO device */
u32
PmcGpio
;
/**< Flag for accessing PS GPIO for versal*/
}
XGpioPs
;
...
...
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_g.c
浏览文件 @
97b6f10a
...
...
@@ -6,9 +6,9 @@
* DO NOT EDIT.
*
* Copyright (C) 2010-2020 Xilinx, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
* SPDX-License-Identifier: MIT
*
*
* Description: Driver configuration
*
*******************************************************************/
...
...
@@ -23,8 +23,8 @@
XGpioPs_Config
XGpioPs_ConfigTable
[
XPAR_XGPIOPS_NUM_INSTANCES
]
=
{
{
XPAR_PSU_GPIO_0_DEVICE_ID
,
XPAR_PSU_GPIO_0_BASEADDR
XPAR_PSU_GPIO_0_DEVICE_ID
,
XPAR_PSU_GPIO_0_BASEADDR
}
};
...
...
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.c
浏览文件 @
97b6f10a
...
...
@@ -19,7 +19,7 @@
* ----- ---- -------- -----------------------------------------------
* 1.02a hk 08/22/13 First Release
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1
kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
* 3.1
kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
* in safety mode and modified the code such as
* Use of mixed mode arithmetic,Declared the pointer param
...
...
@@ -52,19 +52,19 @@
* This function resets the GPIO module by writing reset values to
* all registers
*
* @param
Base address of GPIO module
* @param
Base address of GPIO module
*
* @return
None
* @return
None
*
* @note
None.
* @note
None.
*
******************************************************************************/
void
XGpioPs_ResetHw
(
u32
BaseAddress
)
{
u32
BankCount
;
u32
Platform
,
MaxBanks
;
u32
BankCount
;
u32
Platform
,
MaxBanks
;
Platform
=
XGetPlatform_Info
();
Platform
=
XGetPlatform_Info
();
if
(
Platform
==
(
u32
)
XPLAT_ZYNQ_ULTRA_MP
)
{
MaxBanks
=
(
u32
)
6
;
}
...
...
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_hw.h
浏览文件 @
97b6f10a
...
...
@@ -23,7 +23,7 @@
* 1.02a hk 08/22/13 Added low level reset API function prototype and
* related constant definitions
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1
kvn 04/13/15 Corrected reset values of banks.
* 3.1
kvn 04/13/15 Corrected reset values of banks.
* 3.5 sne 03/14/19 Added versal support.
* </pre>
*
...
...
@@ -106,33 +106,33 @@ extern "C" {
*
* This macro reads the given register.
*
* @param
BaseAddr is the base address of the device.
* @param
RegOffset is the register offset to be read.
* @param
BaseAddr is the base address of the device.
* @param
RegOffset is the register offset to be read.
*
* @return
The 32-bit value of the register
* @return
The 32-bit value of the register
*
* @note
None.
* @note
None.
*
*****************************************************************************/
#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
Xil_In32((BaseAddr) + (u32)(RegOffset))
Xil_In32((BaseAddr) + (u32)(RegOffset))
/****************************************************************************/
/**
*
* This macro writes to the given register.
*
* @param
BaseAddr is the base address of the device.
* @param
RegOffset is the offset of the register to be written.
* @param
Data is the 32-bit value to write to the register.
* @param
BaseAddr is the base address of the device.
* @param
RegOffset is the offset of the register to be written.
* @param
Data is the 32-bit value to write to the register.
*
* @return
None.
* @return
None.
*
* @note
None.
* @note
None.
*
*****************************************************************************/
#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
/************************** Function Prototypes ******************************/
...
...
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_intr.c
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_selftest.c
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/xgpiops_sinit.c
浏览文件 @
97b6f10a
...
...
@@ -13,7 +13,7 @@
* This file contains the implementation of the XGpioPs driver's static
* initialization functionality.
*
* @note
None.
* @note
None.
*
* <pre>
*
...
...
@@ -50,26 +50,26 @@ extern XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES];
* ID. The table XGpioPs_ConfigTable[] contains the configuration information
* for each device in the system.
*
* @param
DeviceId is the unique device ID of the device being looked up.
* @param
DeviceId is the unique device ID of the device being looked up.
*
* @return
A pointer to the configuration table entry corresponding to the
*
given device ID, or NULL if no match is found.
* @return
A pointer to the configuration table entry corresponding to the
*
given device ID, or NULL if no match is found.
*
* @note
None.
* @note
None.
*
******************************************************************************/
XGpioPs_Config
*
XGpioPs_LookupConfig
(
u16
DeviceId
)
{
XGpioPs_Config
*
CfgPtr
=
NULL
;
u32
Index
;
XGpioPs_Config
*
CfgPtr
=
NULL
;
u32
Index
;
for
(
Index
=
0U
;
Index
<
(
u32
)
XPAR_XGPIOPS_NUM_INSTANCES
;
Index
++
)
{
if
(
XGpioPs_ConfigTable
[
Index
].
DeviceId
==
DeviceId
)
{
CfgPtr
=
&
XGpioPs_ConfigTable
[
Index
];
break
;
for
(
Index
=
0U
;
Index
<
(
u32
)
XPAR_XGPIOPS_NUM_INSTANCES
;
Index
++
)
{
if
(
XGpioPs_ConfigTable
[
Index
].
DeviceId
==
DeviceId
)
{
CfgPtr
=
&
XGpioPs_ConfigTable
[
Index
];
break
;
}
}
return
(
XGpioPs_Config
*
)
CfgPtr
;
return
(
XGpioPs_Config
*
)
CfgPtr
;
}
/** @} */
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.c
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps.h
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_card.c
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_g.c
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_host.c
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_hw.h
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_options.c
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/xsdps_sinit.c
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sleep.h
浏览文件 @
97b6f10a
...
...
@@ -13,15 +13,15 @@ extern "C" {
static
inline
void
usleep
(
unsigned
long
useconds
)
{
rt_uint32_t
milliseconds
=
useconds
/
1000
;
useconds
=
useconds
%
1000
;
if
(
milliseconds
)
rt_thread_mdelay
(
milliseconds
);
if
(
useconds
)
rt_hw_us_delay
(
useconds
);
rt_uint32_t
milliseconds
=
useconds
/
1000
;
useconds
=
useconds
%
1000
;
if
(
milliseconds
)
rt_thread_mdelay
(
milliseconds
);
if
(
useconds
)
rt_hw_us_delay
(
useconds
);
}
static
inline
void
sleep
(
unsigned
int
seconds
)
{
rt_thread_delay
(
seconds
*
RT_TICK_PER_SECOND
);
rt_thread_delay
(
seconds
*
RT_TICK_PER_SECOND
);
}
#ifdef __cplusplus
...
...
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xadapter.h
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xemacpsif.h
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xpqueue.h
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/netif/xtopology.h
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xadapter.c
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemac_ieee_reg.h
浏览文件 @
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...
...
@@ -44,7 +44,7 @@
#define ADVERTISE_100_AND_10 (ADVERTISE_10FULL | ADVERTISE_100FULL | \
ADVERTISE_10HALF | ADVERTISE_100HALF)
ADVERTISE_10HALF | ADVERTISE_100HALF)
#define ADVERTISE_100 (ADVERTISE_100FULL | ADVERTISE_100HALF)
#define ADVERTISE_10 (ADVERTISE_10FULL | ADVERTISE_10HALF)
...
...
bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif.c
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif_dma.c
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif_hw.c
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xemacpsif_physpeed.c
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xpqueue.c
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/xtopology_g.c
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_io.h
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xil_types.h
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters.h
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xparameters_ps.h
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bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xplatform_info.h
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bsp/zynqmp-r5-axu4ev/drivers/drv_eth.c
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