[bsp][lpc55s06] add LPC55S06 support

bsp/lpc55sxx/Libraries/Kconfig

@@ -8,3 +8,7 @@ config SOC_LPC55S69_SERIES
     select ARCH_ARM_CORTEX_M33
     select ARCH_ARM_CORTEX_FPU
 
+config SOC_LPC55S06_SERIES
+    bool
+    select ARCH_ARM_CORTEX_M33
+    select ARCH_ARM_CORTEX_FPU

bsp/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/LPC55S06_flash.scf

+#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
+/*
+** ###################################################################
+**     Processors:          LPC55S06JBD64
+**                          LPC55S06JHI48
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    LPC55S0x/LPC550x User manual Rev.0.3  14 August 2020
+**     Version:             rev. 1.0, 2020-04-09
+**     Build:               b220622
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2022 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/* USB BDT size */
+#define usb_bdt_size                   0x0
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+#define  m_interrupts_start            0x00000000
+#define  m_interrupts_size             0x00000200
+
+#define m_text_start                   0x00000200
+#define m_text_size                    0x0003CE00
+
+#define  m_data_start                  0x20000000
+#define  m_data_size                   0x00010000
+
+#define  m_sramx_start                 0x04000000
+#define  m_sramx_size                  0x00004000
+
+#define  m_sram3_start                 0x20010000
+#define  m_sram3_size                  0x00004000
+
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region
+
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (.isr_vector,+FIRST)
+  }
+
+  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+  }
+  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+
+}

bsp/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/LPC55S06_ram.scf

+#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
+/*
+** ###################################################################
+**     Processors:          LPC55S06JBD64
+**                          LPC55S06JHI48
+**
+**     Compiler:            Keil ARM C/C++ Compiler
+**     Reference manual:    LPC55S0x/LPC550x User manual Rev.0.3  14 August 2020
+**     Version:             rev. 1.0, 2020-04-09
+**     Build:               b220622
+**
+**     Abstract:
+**         Linker file for the Keil ARM C/C++ Compiler
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2022 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/* USB BDT size */
+#define usb_bdt_size                   0x0
+/* Sizes */
+#if (defined(__stack_size__))
+  #define Stack_Size                   __stack_size__
+#else
+  #define Stack_Size                   0x0400
+#endif
+
+#if (defined(__heap_size__))
+  #define Heap_Size                    __heap_size__
+#else
+  #define Heap_Size                    0x0400
+#endif
+
+#define  m_interrupts_start            0x20000000
+#define  m_interrupts_size             0x00000200
+
+#define m_text_start                   0x20000200
+#define m_text_size                    0x0000FE00
+
+#define  m_data_start                  0x04000000
+#define  m_data_size                   0x00004000
+
+#define  m_sram3_start                 0x20010000
+#define  m_sram3_size                  0x00004000
+
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region
+
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (.isr_vector,+FIRST)
+  }
+
+  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+    * (InRoot$$Sections)
+    .ANY (+RO)
+  }
+
+  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+    .ANY (+RW +ZI)
+  }
+  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
+  }
+  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+  }
+
+}

bsp/lpc55sxx/Libraries/LPC55S06/LPC55S06/arm/LPC55S0xx.dbgconf

+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <o0> SWO pin
+// <i> The SWO (Serial Wire Output) pin optionally provides data from the ITM
+// <i> for an external debug tool to evaluate.
+//      <0=> PIO0_10
+//      <1=> PIO0_8
+SWO_Pin = 0;
+// 
+
+// <h>Debug Configuration
+//   <o.0>    StopAfterBootloader       <i> Stop after Bootloader
+// </h>
+Dbg_CR = 0x00000001;
+//
+
+
+// <<< end of configuration section >>>
\ No newline at end of file

bsp/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_anactrl.c

+/*
+ * Copyright 2018-2021, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "fsl_anactrl.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.anactrl"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get instance number for ANACTRL module.
+ *
+ * @param base ANACTRL peripheral base address
+ */
+static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to ANACTRL bases for each instance. */
+static ANACTRL_Type *const s_anactrlBases[] = ANACTRL_BASE_PTRS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to ANACTRL clocks for each instance. */
+static const clock_ip_name_t s_anactrlClocks[] = ANALOGCTRL_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * brief Get the ANACTRL instance from peripheral base address.
+ *
+ * param base ANACTRL peripheral base address.
+ * return ANACTRL instance.
+ */
+static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_anactrlBases); instance++)
+    {
+        if (s_anactrlBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_anactrlBases));
+
+    return instance;
+}
+
+/*!
+ * brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function.
+ *
+ * param base ANACTRL peripheral base address.
+ */
+void ANACTRL_Init(ANACTRL_Type *base)
+{
+    assert(NULL != base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the clock for ANACTRL instance. */
+    CLOCK_EnableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function.
+ *
+ * param base ANACTRL peripheral base address.
+ */
+void ANACTRL_Deinit(ANACTRL_Type *base)
+{
+    assert(NULL != base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the clock for ANACTRL instance. */
+    CLOCK_DisableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock output
+ * and enable/disable 96MHZ clock output.
+ *
+ * param base ANACTRL peripheral base address.
+ * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure.
+ */
+void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config)
+{
+    assert(NULL != config);
+
+    uint32_t tmp32 = base->FRO192M_CTRL;
+
+    tmp32 &= ~(ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK);
+
+    if (config->enable12MHzClk)
+    {
+        tmp32 |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK;
+    }
+    if (config->enable96MHzClk)
+    {
+        tmp32 |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK;
+    }
+
+    base->FRO192M_CTRL |= tmp32;
+}
+
+/*!
+ * brief Gets the default configuration of FRO192M.
+ * The default values are:
+ * code
+    config->enable12MHzClk = true;
+    config->enable96MHzClk = false;
+    endcode
+ * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure.
+ */
+void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config)
+{
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->enable12MHzClk = true;
+    config->enable96MHzClk = false;
+}
+
+/*!
+ * brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU
+ * system, and so on.
+ *
+ * param base ANACTRL peripheral base address.
+ * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure.
+ */
+void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config)
+{
+    assert(NULL != config);
+
+    uint32_t tmp32 = base->XO32M_CTRL;
+
+    tmp32 &= ~(ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK | ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK);
+
+    /* Set XO32M CTRL. */
+#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \
+      FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD)
+    tmp32 &= ~ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK;
+    if (config->enablePllUsbOutput)
+    {
+        tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK;
+    }
+#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */
+
+    if (config->enableACBufferBypass)
+    {
+        tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK;
+    }
+
+    if (config->enableSysCLkOutput)
+    {
+        tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;
+    }
+    base->XO32M_CTRL = tmp32;
+
+#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \
+     FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD)
+    if (config->enableADCOutput)
+    {
+        base->DUMMY_CTRL |= ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK;
+    }
+    else
+    {
+        base->DUMMY_CTRL &= ~ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK;
+    }
+#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */
+}
+
+/*!
+ * brief Gets the default configuration of XO32M.
+ * The default values are:
+ * code
+    config->enableSysCLkOutput = false;
+    config->enableACBufferBypass = false;
+    endcode
+ * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure.
+ */
+void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config)
+{
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \
+      FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD)
+    config->enablePllUsbOutput = false;
+#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */
+    config->enableSysCLkOutput   = false;
+    config->enableACBufferBypass = false;
+#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \
+     FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD)
+    config->enableADCOutput = true;
+#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */
+}
+
+#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL)
+/*!
+ * brief Measures the frequency of the target clock source.
+ *
+ * This function measures target frequency according to a accurate reference frequency.The formula is:
+ * Ftarget = (CAPVAL * Freference) / ((1<<SCALE)-1)
+ *
+ * note Both tartget and reference clocks are selectable by programming the target clock select FREQMEAS_TARGET register
+ * in INPUTMUX and reference clock select FREQMEAS_REF register in INPUTMUX.
+ *
+ * param base ANACTRL peripheral base address.
+ * param scale Define the power of 2 count that ref counter counts to during measurement, ranges from 2 to 31.
+ * param refClkFreq frequency of the reference clock.
+ *
+ * return frequency of the target clock.
+ */
+uint32_t ANACTRL_MeasureFrequency(ANACTRL_Type *base, uint8_t scale, uint32_t refClkFreq)
+{
+    assert(scale >= 2U);
+
+    uint32_t targetClkFreq = 0U;
+    uint32_t capval        = 0U;
+
+    /* Init a measurement cycle. */
+    base->FREQ_ME_CTRL = ANACTRL_FREQ_ME_CTRL_PROG_MASK + ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(scale);
+    while (ANACTRL_FREQ_ME_CTRL_PROG_MASK == (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_PROG_MASK))
+    {
+    }
+
+    /* Calculate the target clock frequency. */
+    capval        = (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK);
+    targetClkFreq = (capval * refClkFreq) / ((1UL << scale) - 1UL);
+
+    return targetClkFreq;
+}
+#endif /* FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL */

bsp/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_anactrl.h

+/*
+ * Copyright 2018-2021, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FSL_ANACTRL_H__
+#define __FSL_ANACTRL_H__
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup anactrl
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief ANACTRL driver version. */
+#define FSL_ANACTRL_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version 2.3.0. */`
+
+/*!
+ * @brief ANACTRL interrupt flags
+ */
+enum _anactrl_interrupt_flags
+{
+#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN)
+    kANACTRL_BodVDDMainFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status
+                                                                               before Interrupt Enable. */
+    kANACTRL_BodVDDMainInterruptFlag =
+        ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_MASK,                     /*!< BOD VDDMAIN Interrupt status
+                                                                                 after Interrupt Enable. */
+    kANACTRL_BodVDDMainPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_MASK, /*!< Current value of BOD VDDMAIN
+                                                                                   power status output. */
+#else
+    kANACTRL_BodVbatFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK, /*!< BOD VBAT Interrupt status before
+                                                                                Interrupt Enable. */
+    kANACTRL_BodVbatInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK, /*!< BOD VBAT Interrupt status
+                                                                                            after Interrupt Enable. */
+    kANACTRL_BodVbatPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK, /*!< Current value of BOD VBAT power
+                                                                                    status output. */
+#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */
+    kANACTRL_BodCoreFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK, /*!< BOD CORE Interrupt status before
+                                                                                Interrupt Enable. */
+    kANACTRL_BodCoreInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK, /*!< BOD CORE Interrupt status
+                                                                                            after Interrupt Enable. */
+    kANACTRL_BodCorePowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK,      /*!< Current value of BOD CORE power
+                                                                                         status output. */
+    kANACTRL_DcdcFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK,              /*!< DCDC Interrupt status before
+                                                                                         Interrupt Enable. */
+    kANACTRL_DcdcInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK, /*!< DCDC Interrupt status after
+                                                                                        Interrupt Enable. */
+    kANACTRL_DcdcPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK,            /*!< Current value of DCDC power
+                                                                                       status output. */
+};
+
+/*!
+ * @brief ANACTRL interrupt control
+ */
+enum _anactrl_interrupt
+{
+#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN)
+    kANACTRL_BodVDDMainInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_MASK, /*!< BOD VDDMAIN
+                                                                                            interrupt control. */
+#else
+    kANACTRL_BodVbatInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK, /*!< BOD VBAT interrupt
+                                                                                            control. */
+#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */
+    kANACTRL_BodCoreInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK, /*!< BOD CORE interrupt
+                                                                                            control. */
+    kANACTRL_DcdcInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK,       /*!< DCDC interrupt control. */
+};
+
+/*!
+ * @brief ANACTRL status flags
+ */
+enum _anactrl_flags
+{
+    kANACTRL_FlashPowerDownFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK,     /*!< Flash power-down status. */
+    kANACTRL_FlashInitErrorFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK, /*!< Flash initialization
+                                                                                          error status. */
+};
+
+/*!
+ * @brief ANACTRL FRO192M and XO32M status flags
+ */
+enum _anactrl_osc_flags
+{
+    kANACTRL_OutputClkValidFlag      = ANACTRL_FRO192M_STATUS_CLK_VALID_MASK,  /*!< Output clock valid signal. */
+    kANACTRL_CCOThresholdVoltageFlag = ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK,  /*!< CCO threshold voltage detector
+                                                                                     output (signal vcco_ok). */
+    kANACTRL_XO32MOutputReadyFlag = ANACTRL_XO32M_STATUS_XO_READY_MASK << 16U, /*!< Indicates XO out
+                                                                                    frequency statibilty. */
+};
+
+/*!
+ * @brief Configuration for FRO192M
+ *
+ * This structure holds the configuration settings for the on-chip high-speed Free Running Oscillator. To initialize
+ * this structure to reasonable defaults, call the ANACTRL_GetDefaultFro192MConfig() function and pass a
+ * pointer to your config structure instance.
+ */
+typedef struct _anactrl_fro192M_config
+{
+    bool enable12MHzClk; /*!< Enable 12MHz clock. */
+    bool enable96MHzClk; /*!< Enable 96MHz clock. */
+} anactrl_fro192M_config_t;
+
+/*!
+ * @brief Configuration for XO32M
+ *
+ * This structure holds the configuration settings for the 32 MHz crystal oscillator. To initialize this
+ * structure to reasonable defaults, call the ANACTRL_GetDefaultXo32MConfig() function and pass a
+ * pointer to your config structure instance.
+ */
+typedef struct _anactrl_xo32M_config
+{
+    bool enableACBufferBypass; /*!< Enable XO AC buffer bypass in pll and top level. */
+#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \
+      FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD)
+    bool enablePllUsbOutput; /*!< Enable XO 32 MHz output to USB HS PLL. */
+#endif                       /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */
+    bool enableSysCLkOutput; /*!< Enable XO 32 MHz output to CPU system, SCT, and CLKOUT */
+#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \
+     FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD)
+    bool enableADCOutput; /*!< Enable High speed crystal oscillator output to ADC. */
+#endif                    /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */
+} anactrl_xo32M_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function.
+ *
+ * @param base ANACTRL peripheral base address.
+ */
+void ANACTRL_Init(ANACTRL_Type *base);
+
+/*!
+ * @brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function.
+ *
+ * @param base ANACTRL peripheral base address.
+ */
+void ANACTRL_Deinit(ANACTRL_Type *base);
+/* @} */
+
+/*!
+ * @name Set oscillators
+ * @{
+ */
+
+/*!
+ * @brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock
+ * output and enable/disable 96MHZ clock output.
+ *
+ * @param base ANACTRL peripheral base address.
+ * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure.
+ */
+void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config);
+
+/*!
+ * @brief Gets the default configuration of FRO192M.
+ * The default values are:
+ * @code
+    config->enable12MHzClk = true;
+    config->enable96MHzClk = false;
+    @endcode
+ * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure.
+ */
+void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config);
+
+/*!
+ * @brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU
+ * system, and so on.
+ *
+ * @param base ANACTRL peripheral base address.
+ * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure.
+ */
+void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config);
+
+/*!
+ * @brief Gets the default configuration of XO32M.
+ * The default values are:
+ * @code
+    config->enableSysCLkOutput = false;
+    config->enableACBufferBypass = false;
+    @endcode
+ * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure.
+ */
+void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config);
+
+/* @} */
+
+#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL)
+/*!
+ * @name Measure Frequency
+ * @{
+ */
+
+/*!
+ * @brief Measures the frequency of the target clock source.
+ *
+ * This function measures target frequency according to a accurate reference frequency.The formula is:
+ * Ftarget = (CAPVAL * Freference) / ((1<<SCALE)-1)
+ *
+ * @note Both tartget and reference clocks are selectable by programming the target clock select FREQMEAS_TARGET
+ * register in INPUTMUX and reference clock select FREQMEAS_REF register in INPUTMUX.
+ *
+ * @param base ANACTRL peripheral base address.
+ * @param scale Define the power of 2 count that ref counter counts to during measurement, ranges from 2 to 31.
+ * @param refClkFreq frequency of the reference clock.
+ *
+ * @return frequency of the target clock.
+ */
+uint32_t ANACTRL_MeasureFrequency(ANACTRL_Type *base, uint8_t scale, uint32_t refClkFreq);
+/* @} */
+#endif /* FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL */
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the ANACTRL interrupts.
+ *
+ * @param base ANACTRL peripheral base address.
+ * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration.
+ */
+static inline void ANACTRL_EnableInterrupts(ANACTRL_Type *base, uint32_t mask)
+{
+    base->BOD_DCDC_INT_CTRL |= (0x15U & mask);
+}
+
+/*!
+ * @brief Disables the ANACTRL interrupts.
+ *
+ * @param base ANACTRL peripheral base address.
+ * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration.
+ */
+static inline void ANACTRL_DisableInterrupts(ANACTRL_Type *base, uint32_t mask)
+{
+    base->BOD_DCDC_INT_CTRL &= ~(0x15U & mask);
+}
+
+/*!
+ * @brief Clears the ANACTRL interrupts.
+ *
+ * @param base ANACTRL peripheral base address.
+ * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration.
+ */
+static inline void ANACTRL_ClearInterrupts(ANACTRL_Type *base, uint32_t mask)
+{
+    base->BOD_DCDC_INT_CTRL |= (uint32_t)(mask << 1UL);
+}
+/* @} */
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets ANACTRL status flags.
+ *
+ * This function gets Analog control status flags. The flags are returned as the logical
+ * OR value of the enumerators @ref _anactrl_flags. To check for a specific status,
+ * compare the return value with enumerators in the @ref _anactrl_flags.
+ * For example, to check whether the flash is in power down mode:
+ * @code
+ *     if (kANACTRL_FlashPowerDownFlag & ANACTRL_ANACTRL_GetStatusFlags(ANACTRL))
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base ANACTRL peripheral base address.
+ * @return ANACTRL status flags which are given in the enumerators in the @ref _anactrl_flags.
+ */
+static inline uint32_t ANACTRL_GetStatusFlags(ANACTRL_Type *base)
+{
+    return base->ANALOG_CTRL_STATUS;
+}
+
+/*!
+ * @brief Gets ANACTRL oscillators status flags.
+ *
+ * This function gets Anactrl oscillators status flags. The flags are returned as the logical
+ * OR value of the enumerators @ref _anactrl_osc_flags. To check for a specific status,
+ * compare the return value with enumerators in the @ref _anactrl_osc_flags.
+ * For example, to check whether the FRO192M clock output is valid:
+ * @code
+ *     if (kANACTRL_OutputClkValidFlag & ANACTRL_ANACTRL_GetOscStatusFlags(ANACTRL))
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base ANACTRL peripheral base address.
+ * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags.
+ */
+static inline uint32_t ANACTRL_GetOscStatusFlags(ANACTRL_Type *base)
+{
+    return (base->FRO192M_STATUS & 0xFFU) | ((base->XO32M_STATUS & 0xFFU) << 16U);
+}
+
+/*!
+ * @brief Gets ANACTRL interrupt status flags.
+ *
+ * This function gets Anactrl interrupt status flags. The flags are returned as the logical
+ * OR value of the enumerators @ref _anactrl_interrupt_flags. To check for a specific status,
+ * compare the return value with enumerators in the @ref _anactrl_interrupt_flags.
+ * For example, to check whether the VBAT voltage level is above the threshold:
+ * @code
+ *     if (kANACTRL_BodVbatPowerFlag & ANACTRL_ANACTRL_GetInterruptStatusFlags(ANACTRL))
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base ANACTRL peripheral base address.
+ * @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags.
+ */
+static inline uint32_t ANACTRL_GetInterruptStatusFlags(ANACTRL_Type *base)
+{
+    return base->BOD_DCDC_INT_STATUS & 0x1FFU;
+}
+/* @} */
+
+#if (defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) && (FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG == 1U))
+/*!
+ * @brief Aux_Bias Control Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Enables/disabless 1V reference voltage buffer.
+ *
+ * @param base ANACTRL peripheral base address.
+ * @param enable Used to enable or disable 1V reference voltage buffer.
+ */
+static inline void ANACTRL_EnableVref1V(ANACTRL_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->AUX_BIAS |= ANACTRL_AUX_BIAS_VREF1VENABLE_MASK;
+    }
+    else
+    {
+        base->AUX_BIAS &= ~ANACTRL_AUX_BIAS_VREF1VENABLE_MASK;
+    }
+}
+
+/* @} */
+#endif /* defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* @}*/
+
+#endif /* __FSL_ANACTRL_H__ */

bsp/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_casper.h

+/*
+ * Copyright 2018-2021 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_CASPER_H_
+#define _FSL_CASPER_H_
+
+#include "fsl_common.h"
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*!
+ * @addtogroup casper_driver
+ * @{
+ */
+/*! @name Driver version */
+/*@{*/
+/*! @brief CASPER driver version. Version 2.2.3.
+ *
+ * Current version: 2.2.3
+ *
+ * Change log:
+ * - Version 2.0.0
+ *   - Initial version
+ * - Version 2.0.1
+ *   - Bug fix KPSDK-24531 double_scalar_multiplication() result may be all zeroes for some specific input
+ * - Version 2.0.2
+ *   - Bug fix KPSDK-25015 CASPER_MEMCPY hard-fault on LPC55xx when both source and destination buffers are outside of
+ * CASPER_RAM
+ * - Version 2.0.3
+ *   - Bug fix KPSDK-28107 RSUB, FILL and ZERO operations not implemented in enum _casper_operation.
+ * - Version 2.0.4
+ *   - For GCC compiler, enforce O1 optimize level, specifically to remove strict-aliasing option.
+ *     This driver is very specific and requires -fno-strict-aliasing.
+ * - Version 2.0.5
+ *   - Fix sign-compare warning.
+ * - Version 2.0.6
+ *   - Fix IAR Pa082 warning.
+ * - Version 2.0.7
+ *   - Fix MISRA-C 2012 issue.
+ * - Version 2.0.8
+ *   - Add feature macro for CASPER_RAM_OFFSET.
+ * - Version 2.0.9
+ *   - Remove unused function Jac_oncurve().
+ *   - Fix ECC384 build.
+ * - Version 2.0.10
+ *   - Fix MISRA-C 2012 issue.
+ * - Version 2.1.0
+ *   - Add ECC NIST P-521 elliptic curve.
+ * - Version 2.2.0
+ *   - Rework driver to support multiple curves at once.
+ * - Version 2.2.1
+ *   - Fix MISRA-C 2012 issue.
+ * - Version 2.2.2
+ *   - Enable hardware interleaving to RAMX0 and RAMX1 for CASPER by feature macro FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE
+ * - Version 2.2.3
+ *   - Added macro into CASPER_Init and CASPER_Deinit to support devices without clock and reset control.
+ */
+#define FSL_CASPER_DRIVER_VERSION (MAKE_VERSION(2, 2, 3))
+/*@}*/
+
+/*! @brief CASPER operation
+ *
+ */
+typedef enum _casper_operation
+{
+    kCASPER_OpMul6464NoSum = 0x01, /*! Walking 1 or more of J loop, doing r=a*b using 64x64=128*/
+    kCASPER_OpMul6464Sum =
+        0x02, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but assume inner j loop*/
+    kCASPER_OpMul6464FullSum =
+        0x03, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but sum all of w. */
+    kCASPER_OpMul6464Reduce =
+        0x04,               /*! Walking 1 or more of J loop, doing c,r[-1]=r+a*b using 64x64=128, but skip 1st write*/
+    kCASPER_OpAdd64 = 0x08, /*! Walking add with off_AB, and in/out off_RES doing c,r=r+a+c using 64+64=65*/
+    kCASPER_OpSub64 = 0x09, /*! Walking subtract with off_AB, and in/out off_RES doing r=r-a using 64-64=64, with last
+                               borrow implicit if any*/
+    kCASPER_OpDouble64 = 0x0A, /*! Walking add to self with off_RES doing c,r=r+r+c using 64+64=65*/
+    kCASPER_OpXor64    = 0x0B, /*! Walking XOR with off_AB, and in/out off_RES doing r=r^a using 64^64=64*/
+    kCASPER_OpRSub64   = 0x0C, /*! Walking subtract with off_AB, and in/out off_RES using r=a-r */
+    kCASPER_OpShiftLeft32 =
+        0x10, /*! Walking shift left doing r1,r=(b*D)|r1, where D is 2^amt and is loaded by app (off_CD not used)*/
+    kCASPER_OpShiftRight32 = 0x11, /*! Walking shift right doing r,r1=(b*D)|r1, where D is 2^(32-amt) and is loaded by
+                                      app (off_CD not used) and off_RES starts at MSW*/
+    kCASPER_OpCopy        = 0x14,  /*! Copy from ABoff to resoff, 64b at a time*/
+    kCASPER_OpRemask      = 0x15,  /*! Copy and mask from ABoff to resoff, 64b at a time*/
+    kCASPER_OpFill        = 0x16,  /*! Fill RESOFF using 64 bits at a time with value in A and B */
+    kCASPER_OpZero        = 0x17,  /*! Fill RESOFF using 64 bits at a time of 0s */
+    kCASPER_OpCompare     = 0x18,  /*! Compare two arrays, running all the way to the end*/
+    kCASPER_OpCompareFast = 0x19,  /*! Compare two arrays, stopping on 1st !=*/
+} casper_operation_t;
+
+/*! @brief Algorithm used for CASPER operation */
+typedef enum _casper_algo_t
+{
+    kCASPER_ECC_P256 = 0x01, /*!< ECC_P256*/
+    kCASPER_ECC_P384 = 0x02, /*!< ECC_P384 */
+    kCASPER_ECC_P521 = 0x03, /*!< ECC_P521 */
+} casper_algo_t;
+
+#define CASPER_CP          1
+#define CASPER_CP_CTRL0    (0x0 >> 2)
+#define CASPER_CP_CTRL1    (0x4 >> 2)
+#define CASPER_CP_LOADER   (0x8 >> 2)
+#define CASPER_CP_STATUS   (0xC >> 2)
+#define CASPER_CP_INTENSET (0x10 >> 2)
+#define CASPER_CP_INTENCLR (0x14 >> 2)
+#define CASPER_CP_INTSTAT  (0x18 >> 2)
+#define CASPER_CP_AREG     (0x20 >> 2)
+#define CASPER_CP_BREG     (0x24 >> 2)
+#define CASPER_CP_CREG     (0x28 >> 2)
+#define CASPER_CP_DREG     (0x2C >> 2)
+#define CASPER_CP_RES0     (0x30 >> 2)
+#define CASPER_CP_RES1     (0x34 >> 2)
+#define CASPER_CP_RES2     (0x38 >> 2)
+#define CASPER_CP_RES3     (0x3C >> 2)
+#define CASPER_CP_MASK     (0x60 >> 2)
+#define CASPER_CP_REMASK   (0x64 >> 2)
+#define CASPER_CP_LOCK     (0x80 >> 2)
+#define CASPER_CP_ID       (0xFFC >> 2)
+/* mcr (cp,  opc1, value, CRn, CRm, opc2) */
+#define CASPER_Wr32b(value, off) __arm_mcr(CASPER_CP, 0, value, ((off >> 4)), (off), 0)
+/* mcrr(coproc, opc1, value, CRm) */
+#define CASPER_Wr64b(value, off) __arm_mcrr(CASPER_CP, 0, value, off)
+/* mrc(coproc, opc1, CRn, CRm, opc2) */
+#define CASPER_Rd32b(off) __arm_mrc(CASPER_CP, 0, ((off >> 4)), (off), 0)
+
+/*  The model for this algo is that it can be implemented for a fixed size RSA key */
+/*  for max speed. If this is made into a variable (to allow varying size), then */
+/*  it will be slower by a bit. */
+/*  The file is compiled with N_bitlen passed in as number of bits of the RSA key */
+/*  #define N_bitlen 2048 */
+#define N_wordlen_max (4096U / 32U)
+
+enum
+{
+    kCASPER_RamOffset_Result   = 0x0u,
+    kCASPER_RamOffset_Base     = (N_wordlen_max + 8u),
+    kCASPER_RamOffset_TempBase = (2u * N_wordlen_max + 16u),
+    kCASPER_RamOffset_Modulus  = (kCASPER_RamOffset_TempBase + N_wordlen_max + 4u),
+    kCASPER_RamOffset_M64      = 1022U,
+};
+
+/*! @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @addtogroup casper_driver
+ * @{
+ */
+
+/*!
+ * @brief Enables clock and disables reset for CASPER peripheral.
+ *
+ * Enable clock and disable reset for CASPER.
+ *
+ * @param base CASPER base address
+ */
+void CASPER_Init(CASPER_Type *base);
+
+/*!
+ * @brief Disables clock for CASPER peripheral.
+ *
+ * Disable clock and enable reset.
+ *
+ * @param base CASPER base address
+ */
+void CASPER_Deinit(CASPER_Type *base);
+
+/*!
+ *@}
+ */ /* end of casper_driver */
+
+/*******************************************************************************
+ * PKHA API
+ ******************************************************************************/
+
+/*!
+ * @addtogroup casper_driver_pkha
+ * @{
+ */
+
+/*!
+ * @brief Performs modular exponentiation - (A^E) mod N.
+ *
+ * This function performs modular exponentiation.
+ *
+ * @param base CASPER base address
+ * @param signature first addend (in little endian format)
+ * @param pubN modulus (in little endian format)
+ * @param wordLen Size of pubN in bytes
+ * @param pubE exponent
+ * @param[out] plaintext Output array to store result of operation (in little endian format)
+ */
+void CASPER_ModExp(CASPER_Type *base,
+                   const uint8_t *signature,
+                   const uint8_t *pubN,
+                   size_t wordLen,
+                   uint32_t pubE,
+                   uint8_t *plaintext);
+
+/*!
+ * @brief Initialize prime modulus mod in Casper memory .
+ *
+ * Set the prime modulus mod in Casper memory and set N_wordlen
+ * according to selected algorithm.
+ *
+ * @param curve elliptic curve algoritm
+ */
+void CASPER_ecc_init(casper_algo_t curve);
+
+/*!
+ * @brief Performs ECC secp256r1 point single scalar multiplication
+ *
+ * This function performs ECC secp256r1 point single scalar multiplication
+ * [resX; resY] = scalar * [X; Y]
+ * Coordinates are affine in normal form, little endian.
+ * Scalars are little endian.
+ * All arrays are little endian byte arrays, uint32_t type is used
+ * only to enforce the 32-bit alignment (0-mod-4 address).
+ *
+ * @param base CASPER base address
+ * @param[out] resX Output X affine coordinate in normal form, little endian.
+ * @param[out] resY Output Y affine coordinate in normal form, little endian.
+ * @param X Input X affine coordinate in normal form, little endian.
+ * @param Y Input Y affine coordinate in normal form, little endian.
+ * @param scalar Input scalar integer, in normal form, little endian.
+ */
+void CASPER_ECC_SECP256R1_Mul(
+    CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]);
+
+/*!
+ * @brief Performs ECC secp256r1 point double scalar multiplication
+ *
+ * This function performs ECC secp256r1 point double scalar multiplication
+ * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2]
+ * Coordinates are affine in normal form, little endian.
+ * Scalars are little endian.
+ * All arrays are little endian byte arrays, uint32_t type is used
+ * only to enforce the 32-bit alignment (0-mod-4 address).
+ *
+ * @param base CASPER base address
+ * @param[out] resX Output X affine coordinate.
+ * @param[out] resY Output Y affine coordinate.
+ * @param X1 Input X1 affine coordinate.
+ * @param Y1 Input Y1 affine coordinate.
+ * @param scalar1 Input scalar1 integer.
+ * @param X2 Input X2 affine coordinate.
+ * @param Y2 Input Y2 affine coordinate.
+ * @param scalar2 Input scalar2 integer.
+ */
+void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base,
+                                 uint32_t resX[8],
+                                 uint32_t resY[8],
+                                 uint32_t X1[8],
+                                 uint32_t Y1[8],
+                                 uint32_t scalar1[8],
+                                 uint32_t X2[8],
+                                 uint32_t Y2[8],
+                                 uint32_t scalar2[8]);
+
+/*!
+ * @brief Performs ECC secp384r1 point single scalar multiplication
+ *
+ * This function performs ECC secp384r1 point single scalar multiplication
+ * [resX; resY] = scalar * [X; Y]
+ * Coordinates are affine in normal form, little endian.
+ * Scalars are little endian.
+ * All arrays are little endian byte arrays, uint32_t type is used
+ * only to enforce the 32-bit alignment (0-mod-4 address).
+ *
+ * @param base CASPER base address
+ * @param[out] resX Output X affine coordinate in normal form, little endian.
+ * @param[out] resY Output Y affine coordinate in normal form, little endian.
+ * @param X Input X affine coordinate in normal form, little endian.
+ * @param Y Input Y affine coordinate in normal form, little endian.
+ * @param scalar Input scalar integer, in normal form, little endian.
+ */
+void CASPER_ECC_SECP384R1_Mul(
+    CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]);
+
+/*!
+ * @brief Performs ECC secp384r1 point double scalar multiplication
+ *
+ * This function performs ECC secp384r1 point double scalar multiplication
+ * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2]
+ * Coordinates are affine in normal form, little endian.
+ * Scalars are little endian.
+ * All arrays are little endian byte arrays, uint32_t type is used
+ * only to enforce the 32-bit alignment (0-mod-4 address).
+ *
+ * @param base CASPER base address
+ * @param[out] resX Output X affine coordinate.
+ * @param[out] resY Output Y affine coordinate.
+ * @param X1 Input X1 affine coordinate.
+ * @param Y1 Input Y1 affine coordinate.
+ * @param scalar1 Input scalar1 integer.
+ * @param X2 Input X2 affine coordinate.
+ * @param Y2 Input Y2 affine coordinate.
+ * @param scalar2 Input scalar2 integer.
+ */
+void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base,
+                                 uint32_t resX[12],
+                                 uint32_t resY[12],
+                                 uint32_t X1[12],
+                                 uint32_t Y1[12],
+                                 uint32_t scalar1[12],
+                                 uint32_t X2[12],
+                                 uint32_t Y2[12],
+                                 uint32_t scalar2[12]);
+
+/*!
+ * @brief Performs ECC secp521r1 point single scalar multiplication
+ *
+ * This function performs ECC secp521r1 point single scalar multiplication
+ * [resX; resY] = scalar * [X; Y]
+ * Coordinates are affine in normal form, little endian.
+ * Scalars are little endian.
+ * All arrays are little endian byte arrays, uint32_t type is used
+ * only to enforce the 32-bit alignment (0-mod-4 address).
+ *
+ * @param base CASPER base address
+ * @param[out] resX Output X affine coordinate in normal form, little endian.
+ * @param[out] resY Output Y affine coordinate in normal form, little endian.
+ * @param X Input X affine coordinate in normal form, little endian.
+ * @param Y Input Y affine coordinate in normal form, little endian.
+ * @param scalar Input scalar integer, in normal form, little endian.
+ */
+void CASPER_ECC_SECP521R1_Mul(
+    CASPER_Type *base, uint32_t resX[18], uint32_t resY[18], uint32_t X[18], uint32_t Y[18], uint32_t scalar[18]);
+
+/*!
+ * @brief Performs ECC secp521r1 point double scalar multiplication
+ *
+ * This function performs ECC secp521r1 point double scalar multiplication
+ * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2]
+ * Coordinates are affine in normal form, little endian.
+ * Scalars are little endian.
+ * All arrays are little endian byte arrays, uint32_t type is used
+ * only to enforce the 32-bit alignment (0-mod-4 address).
+ *
+ * @param base CASPER base address
+ * @param[out] resX Output X affine coordinate.
+ * @param[out] resY Output Y affine coordinate.
+ * @param X1 Input X1 affine coordinate.
+ * @param Y1 Input Y1 affine coordinate.
+ * @param scalar1 Input scalar1 integer.
+ * @param X2 Input X2 affine coordinate.
+ * @param Y2 Input Y2 affine coordinate.
+ * @param scalar2 Input scalar2 integer.
+ */
+void CASPER_ECC_SECP521R1_MulAdd(CASPER_Type *base,
+                                 uint32_t resX[18],
+                                 uint32_t resY[18],
+                                 uint32_t X1[18],
+                                 uint32_t Y1[18],
+                                 uint32_t scalar1[18],
+                                 uint32_t X2[18],
+                                 uint32_t Y2[18],
+                                 uint32_t scalar2[18]);
+
+void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2);
+void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1);
+
+/*!
+ *@}
+ */ /* end of casper_driver_pkha */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_CASPER_H_ */

bsp/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_cdog.c

+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_cdog.h"
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.cdog"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief Sets the default configuration of CDOG
+ *
+ * This function initialize CDOG config structure to default values.
+ *
+ * param conf CDOG configuration structure
+ */
+void CDOG_GetDefaultConfig(cdog_config_t *conf)
+{
+    /* Default configuration after reset */
+    conf->lock       = (uint8_t)kCDOG_LockCtrl_Unlock;    /* Lock control */
+    conf->timeout    = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Timeout control */
+    conf->miscompare = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Miscompare control */
+    conf->sequence   = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Sequence control */
+    conf->state      = (uint8_t)kCDOG_FaultCtrl_NoAction; /* State control */
+    conf->address    = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Address control */
+    conf->irq_pause  = (uint8_t)kCDOG_IrqPauseCtrl_Run;   /* IRQ pause control */
+    conf->debug_halt = (uint8_t)kCDOG_DebugHaltCtrl_Run;  /* Debug halt control */
+    return;
+}
+
+/*!
+ * brief Sets secure counter and instruction timer values
+ *
+ * This function sets value in RELOAD and START registers for instruction timer.
+ *
+ * param base CDOG peripheral base address
+ * param reload reload value
+ * param start start value
+ */
+void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start)
+{
+    base->RELOAD = reload;
+    base->START  = start;
+}
+
+/*!
+ * brief Stops secure counter and instruction timer
+ *
+ * This function stops instruction timer and secure counter.
+ * This also change state of CDOG to IDLE.
+ *
+ * param base CDOG peripheral base address
+ * param stop expected value which will be compared with value of secure counter
+ */
+void CDOG_Stop(CDOG_Type *base, uint32_t stop)
+{
+    base->STOP = stop;
+}
+
+/*!
+ * brief Sets secure counter and instruction timer values
+ *
+ * This function sets value in STOP, RELOAD and START registers
+ * for instruction timer and secure counter.
+ *
+ * param base CDOG peripheral base address
+ * param stop expected value which will be compared with value of secure counter
+ * param reload reload value for instruction timer
+ * param start start value for secure timer
+ */
+void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start)
+{
+    base->STOP   = stop;
+    base->RELOAD = reload;
+    base->START  = start;
+}
+
+/*!
+ * brief Add value to secure counter
+ *
+ * This function add specified value to secure counter.
+ *
+ * param base CDOG peripheral base address.
+ * param add Value to be added.
+ */
+void CDOG_Add(CDOG_Type *base, uint32_t add)
+{
+    base->ADD = (secure_counter_t)add;
+}
+
+/*!
+ * brief Add 1 to secure counter
+ *
+ * This function add 1 to secure counter.
+ *
+ * param base CDOG peripheral base address.
+ * param add Value to be added.
+ */
+void CDOG_Add1(CDOG_Type *base)
+{
+    base->ADD1 = (secure_counter_t)0x1U;
+}
+
+/*!
+ * brief Add 16 to secure counter
+ *
+ * This function add 16 to secure counter.
+ *
+ * param base CDOG peripheral base address.
+ * param add Value to be added.
+ */
+void CDOG_Add16(CDOG_Type *base)
+{
+    base->ADD16 = (secure_counter_t)0x1U;
+}
+
+/*!
+ * brief Add 256 to secure counter
+ *
+ * This function add 256 to secure counter.
+ *
+ * param base CDOG peripheral base address.
+ * param add Value to be added.
+ */
+void CDOG_Add256(CDOG_Type *base)
+{
+    base->ADD256 = (secure_counter_t)0x1U;
+}
+
+/*!
+ * brief Substract value to secure counter
+ *
+ * This function substract specified value to secure counter.
+ *
+ * param base CDOG peripheral base address.
+ * param sub Value to be substracted.
+ */
+void CDOG_Sub(CDOG_Type *base, uint32_t sub)
+{
+    base->SUB = (secure_counter_t)sub;
+}
+
+/*!
+ * brief Substract 1 from secure counter
+ *
+ * This function substract specified 1 from secure counter.
+ *
+ * param base CDOG peripheral base address.
+ */
+void CDOG_Sub1(CDOG_Type *base)
+{
+    base->SUB1 = (secure_counter_t)0x1U;
+}
+
+/*!
+ * brief Substract 16 from secure counter
+ *
+ * This function substract specified 16 from secure counter.
+ *
+ * param base CDOG peripheral base address.
+ */
+void CDOG_Sub16(CDOG_Type *base)
+{
+    base->SUB16 = (secure_counter_t)0x1U;
+}
+
+/*!
+ * brief Substract 256 from secure counter
+ *
+ * This function substract specified 256 from secure counter.
+ *
+ * param base CDOG peripheral base address.
+ */
+void CDOG_Sub256(CDOG_Type *base)
+{
+    base->SUB256 = (secure_counter_t)0x1U;
+}
+
+/*!
+ * brief Checks secure counter.
+ *
+ * This function compares stop value with secure counter value
+ * by writting to RELOAD refister.
+ *
+ * param base CDOG peripheral base address
+ * param check expected (stop) value.
+ */
+void CDOG_Check(CDOG_Type *base, uint32_t check)
+{
+    base->RESTART = check;
+}
+
+/*!
+ * brief Set the CDOG persistent word.
+ *
+ * param base CDOG peripheral base address.
+ * param value The value to be written.
+ */
+void CDOG_WritePersistent(CDOG_Type *base, uint32_t value)
+{
+    base->PERSISTENT = value;
+}
+
+/*!
+ * brief Get the CDOG persistent word.
+ *
+ * param base CDOG peripheral base address.
+ * return The persistent word.
+ */
+uint32_t CDOG_ReadPersistent(CDOG_Type *base)
+{
+    return base->PERSISTENT;
+}
+
+/*!
+ * brief Initialize CDOG
+ *
+ * This function initializes CDOG block and setting.
+ *
+ * param base CDOG peripheral base address
+ * param conf CDOG configuration structure
+ * return Status of the init operation
+ */
+status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)
+{
+    /* Ungate clock to CDOG engine and reset it */
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+#ifdef CDOG_CLOCKS
+    CLOCK_EnableClock(kCLOCK_Cdog);
+#endif /* CDOG_CLOCKS */
+#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET)
+    RESET_PeripheralReset(kCDOG_RST_SHIFT_RSTn);
+#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */
+
+    if (base->CONTROL == 0x0U)
+    {
+        /* CDOG is not in IDLE mode, which may be cause after SW reset. */
+        /* Writing to CONTROL register will trigger fault. */
+        return kStatus_Fail;
+    }
+
+    /* Clear pending errors, otherwise the device will reset */
+    /* itself immediately after enable Code Watchdog */
+    if ((uint32_t)kCDOG_LockCtrl_Lock ==
+        ((base->CONTROL & CDOG_CONTROL_LOCK_CTRL_MASK) >> CDOG_CONTROL_LOCK_CTRL_SHIFT))
+
+    {
+        CDOG->FLAGS = CDOG_FLAGS_TO_FLAG(1U) | CDOG_FLAGS_MISCOM_FLAG(1U) | CDOG_FLAGS_SEQ_FLAG(1U) |
+                      CDOG_FLAGS_CNT_FLAG(1U) | CDOG_FLAGS_STATE_FLAG(1U) | CDOG_FLAGS_ADDR_FLAG(1U) |
+                      CDOG_FLAGS_POR_FLAG(1U);
+    }
+    else
+    {
+        CDOG->FLAGS = CDOG_FLAGS_TO_FLAG(0U) | CDOG_FLAGS_MISCOM_FLAG(0U) | CDOG_FLAGS_SEQ_FLAG(0U) |
+                      CDOG_FLAGS_CNT_FLAG(0U) | CDOG_FLAGS_STATE_FLAG(0U) | CDOG_FLAGS_ADDR_FLAG(0U) |
+                      CDOG_FLAGS_POR_FLAG(0U);
+    }
+
+    base->CONTROL =
+        CDOG_CONTROL_TIMEOUT_CTRL(conf->timeout) |       /* Action if the timeout event is triggered  */
+        CDOG_CONTROL_MISCOMPARE_CTRL(conf->miscompare) | /* Action if the miscompare error event is triggered  */
+        CDOG_CONTROL_SEQUENCE_CTRL(conf->sequence) |     /* Action if the sequence error event is triggered  */
+        CDOG_CONTROL_STATE_CTRL(conf->state) |           /* Action if the state error event is triggered  */
+        CDOG_CONTROL_ADDRESS_CTRL(conf->address) |       /* Action if the address error event is triggered */
+        CDOG_CONTROL_IRQ_PAUSE(conf->irq_pause) |        /* Pause running during interrupts setup */
+        CDOG_CONTROL_DEBUG_HALT_CTRL(
+            conf->debug_halt) |             /* Halt CDOG timer during debug so we have chance to debug code */
+        CDOG_CONTROL_LOCK_CTRL(conf->lock); /* Lock control register */
+
+    NVIC_EnableIRQ(CDOG_IRQn);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Deinitialize CDOG
+ *
+ * This function stops CDOG secure counter.
+ *
+ * param base CDOG peripheral base address
+ */
+void CDOG_Deinit(CDOG_Type *base)
+{
+    NVIC_DisableIRQ(CDOG_IRQn);
+
+#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET)
+    RESET_SetPeripheralReset(kCDOG_RST_SHIFT_RSTn);
+#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+#ifdef CDOG_CLOCKS
+    CLOCK_DisableClock(kCLOCK_Cdog);
+#endif /* CDOG_CLOCKS */
+#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}

bsp/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_cdog.h

+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_CDOG_H_
+#define _FSL_CDOG_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup CDOG
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Defines CDOG driver version 2.1.1.
+ *
+ * Change log:
+ * - Version 2.1.1
+ *   - Remove bit CONTROL[CONTROL_CTRL]
+ * - Version 2.1.0
+ *   - Rename CWT to CDOG
+ * - Version 2.0.2
+ *   - Fix MISRA-2012 issues
+ * - Version 2.0.1
+ *   - Fix doxygen issues
+ * - Version 2.0.0
+ *   - initial version
+ */
+#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*@}*/
+
+typedef struct
+{
+    uint8_t lock : 2;
+    uint8_t timeout : 3;
+    uint8_t miscompare : 3;
+    uint8_t sequence : 3;
+    uint8_t state : 3;
+    uint8_t address : 3;
+    uint8_t reserved : 8;
+    uint8_t irq_pause : 2;
+    uint8_t debug_halt : 2;
+} cdog_config_t;
+
+enum __cdog_debug_Action_ctrl_enum
+{
+    kCDOG_DebugHaltCtrl_Run   = 0x1,
+    kCDOG_DebugHaltCtrl_Pause = 0x2,
+};
+
+enum __cdog_irq_pause_ctrl_enum
+{
+    kCDOG_IrqPauseCtrl_Run   = 0x1,
+    kCDOG_IrqPauseCtrl_Pause = 0x2,
+};
+
+enum __cdog_fault_ctrl_enum
+{
+    kCDOG_FaultCtrl_EnableReset     = 0x1U,
+    kCDOG_FaultCtrl_EnableInterrupt = 0x2U,
+    kCDOG_FaultCtrl_NoAction        = 0x4U,
+};
+
+enum __code_lock_ctrl_enum
+{
+    kCDOG_LockCtrl_Lock   = 0x1,
+    kCDOG_LockCtrl_Unlock = 0x2,
+};
+
+typedef uint32_t secure_counter_t;
+
+#define SC_ADD(add)                          \
+    do                                       \
+    {                                        \
+        CDOG->ADD = (secure_counter_t)(add); \
+    } while (0)
+
+#define SC_ADD1                              \
+    do                                       \
+    {                                        \
+        CDOG->ADD1 = (secure_counter_t)0x1U; \
+    } while (0)
+
+#define SC_ADD16                              \
+    do                                        \
+    {                                         \
+        CDOG->ADD16 = (secure_counter_t)0x1U; \
+    } while (0)
+
+#define SC_ADD256                              \
+    do                                         \
+    {                                          \
+        CDOG->ADD256 = (secure_counter_t)0x1U; \
+    } while (0)
+
+#define SC_SUB(sub)                          \
+    do                                       \
+    {                                        \
+        CDOG->SUB = (secure_counter_t)(sub); \
+    } while (0)
+
+#define SC_SUB1                              \
+    do                                       \
+    {                                        \
+        CDOG->SUB1 = (secure_counter_t)0x1U; \
+    } while (0)
+
+#define SC_SUB16                              \
+    do                                        \
+    {                                         \
+        CDOG->SUB16 = (secure_counter_t)0x1U; \
+    } while (0)
+
+#define SC_SUB256                              \
+    do                                         \
+    {                                          \
+        CDOG->SUB256 = (secure_counter_t)0x1U; \
+    } while (0)
+
+#define SC_CHECK(val)                          \
+    do                                         \
+    {                                          \
+        CDOG->RESTART = (secure_counter_t)val; \
+    } while (0)
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+extern void CDOG_DriverIRQHandler(void);
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name CDOG Functional Operation
+ * @{
+ */
+
+/*!
+ * @brief Initialize CDOG
+ *
+ * This function initializes CDOG block and setting.
+ *
+ * @param base CDOG peripheral base address
+ * @param conf CDOG configuration structure
+ * @return Status of the init operation
+ */
+status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf);
+
+/*!
+ * @brief Deinitialize CDOG
+ *
+ * This function deinitializes CDOG secure counter.
+ *
+ * @param base CDOG peripheral base address
+ */
+void CDOG_Deinit(CDOG_Type *base);
+
+/*!
+ * @brief Sets the default configuration of CDOG
+ *
+ * This function initialize CDOG config structure to default values.
+ *
+ * @param conf CDOG configuration structure
+ */
+void CDOG_GetDefaultConfig(cdog_config_t *conf);
+
+/*!
+ * @brief Stops secure counter and instruction timer
+ *
+ * This function stops instruction timer and secure counter.
+ * This also change state od CDOG to IDLE.
+ *
+ * @param base CDOG peripheral base address
+ * @param stop expected value which will be compared with value of secure counter
+ */
+void CDOG_Stop(CDOG_Type *base, uint32_t stop);
+
+/*!
+ * @brief Sets secure counter and instruction timer values
+ *
+ * This function sets value in RELOAD and START registers
+ * for instruction timer and secure counter
+ *
+ * @param base CDOG peripheral base address
+ * @param reload reload value
+ * @param start start value
+ */
+void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start);
+
+/*!
+ * @brief Checks secure counter.
+ *
+ * This function compares stop value in handler with secure counter value
+ * by writting to RELOAD refister.
+ *
+ * @param base CDOG peripheral base address
+ * @param check expected (stop) value
+ */
+void CDOG_Check(CDOG_Type *base, uint32_t check);
+
+/*!
+ * @brief Sets secure counter and instruction timer values
+ *
+ * This function sets value in STOP, RELOAD and START registers
+ * for instruction timer and secure counter.
+ *
+ * @param base CDOG peripheral base address
+ * @param stop expected value which will be compared with value of secure counter
+ * @param reload reload value for instruction timer
+ * @param start start value for secure timer
+ */
+void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start);
+
+/*!
+ * @brief Add value to secure counter
+ *
+ * This function add specified value to secure counter.
+ *
+ * @param base CDOG peripheral base address.
+ * @param add Value to be added.
+ */
+void CDOG_Add(CDOG_Type *base, uint32_t add);
+
+/*!
+ * @brief Add 1 to secure counter
+ *
+ * This function add 1 to secure counter.
+ *
+ * @param base CDOG peripheral base address.
+ */
+void CDOG_Add1(CDOG_Type *base);
+
+/*!
+ * @brief Add 16 to secure counter
+ *
+ * This function add 16 to secure counter.
+ *
+ * @param base CDOG peripheral base address.
+ */
+void CDOG_Add16(CDOG_Type *base);
+
+/*!
+ * @brief Add 256 to secure counter
+ *
+ * This function add 256 to secure counter.
+ *
+ * @param base CDOG peripheral base address.
+ */
+void CDOG_Add256(CDOG_Type *base);
+
+/*!
+ * brief Substract value to secure counter
+ *
+ * This function substract specified value to secure counter.
+ *
+ * param base CDOG peripheral base address.
+ * param sub Value to be substracted.
+ */
+void CDOG_Sub(CDOG_Type *base, uint32_t sub);
+
+/*!
+ * @brief Substract 1 from secure counter
+ *
+ * This function substract specified 1 from secure counter.
+ *
+ * @param base CDOG peripheral base address.
+ */
+void CDOG_Sub1(CDOG_Type *base);
+
+/*!
+ * @brief Substract 16 from secure counter
+ *
+ * This function substract specified 16 from secure counter.
+ *
+ * @param base CDOG peripheral base address.
+ */
+void CDOG_Sub16(CDOG_Type *base);
+
+/*!
+ * @brief Substract 256 from secure counter
+ *
+ * This function substract specified 256 from secure counter.
+ *
+ * @param base CDOG peripheral base address.
+ */
+void CDOG_Sub256(CDOG_Type *base);
+
+/*!
+ * @brief Set the CDOG persistent word.
+ *
+ * @param base CDOG peripheral base address.
+ * @param value The value to be written.
+ */
+void CDOG_WritePersistent(CDOG_Type *base, uint32_t value);
+
+/*!
+ * @brief Get the CDOG persistent word.
+ *
+ * @param base CDOG peripheral base address.
+ * @return The persistent word.
+ */
+uint32_t CDOG_ReadPersistent(CDOG_Type *base);
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/ /* end of group cdog */
+
+#endif /* _FSL_CDOG_H_ */

bsp/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_cmp.c

+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_cmp.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.cmp_1"
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief CMP initialization.
+ *
+ * This function enables the CMP module and do necessary settings.
+ *
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_Init(const cmp_config_t *config)
+{
+    assert(NULL != config);
+
+    uint32_t tmpReg = 0U;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the clock. */
+    CLOCK_EnableClock(kCLOCK_Comp);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_CMP_HAS_NO_RESET) && FSL_TEATURE_CMP_HAS_NO_RESET)
+    /* Reset the CMP module. */
+    RESET_PeripheralReset(kCMP_RST_SHIFT_RSTn);
+#endif /* FSL_FEATURE_CMP_HAS_NO_RESET */
+
+    tmpReg = (PMC->COMP & ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_FILTERCGF_CLKDIV_MASK |
+                            PMC_COMP_FILTERCGF_SAMPLEMODE_MASK));
+
+    if (true == config->enableLowPower)
+    {
+        tmpReg |= PMC_COMP_LOWPOWER_MASK;
+    }
+    else
+    {
+        tmpReg &= ~PMC_COMP_LOWPOWER_MASK;
+    }
+
+    if (true == config->enableHysteresis)
+    {
+        tmpReg |= PMC_COMP_HYST_MASK;
+    }
+    else
+    {
+        tmpReg &= ~PMC_COMP_HYST_MASK;
+    }
+
+    tmpReg |= (PMC_COMP_FILTERCGF_CLKDIV(config->filterClockDivider) |
+               PMC_COMP_FILTERCGF_SAMPLEMODE(config->filterSampleMode));
+
+    PMC->COMP = tmpReg;
+}
+
+/*!
+ * @brief CMP deinitialization.
+ *
+ * This function gates the clock for CMP module.
+ */
+void CMP_Deinit(void)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the clock. */
+    CLOCK_DisableClock(kCLOCK_Comp);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * @brief Initializes the CMP user configuration structure.
+ *
+ * This function initializes the user configuration structure to these default values.
+ * @code
+ *   config->enableHysteresis    = true;
+ *   config->enableLowPower      = true;
+ *   config->filterClockDivider  = kCMP_FilterClockDivide1;
+ *   config->filterSampleMode    = kCMP_FilterSampleMode0;
+ * @endcode
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_GetDefaultConfig(cmp_config_t *config)
+{
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->enableHysteresis   = true;
+    config->enableLowPower     = true;
+    config->filterClockDivider = kCMP_FilterClockDivide1;
+    config->filterSampleMode   = kCMP_FilterSampleMode0;
+}
+
+/*!
+ * @brief Configures the VREFINPUT.
+ *
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_SetVREF(const cmp_vref_config_t *config)
+{
+    assert(NULL != config);
+    assert(config->vrefValue < 32U);
+
+    uint32_t tmpReg = PMC->COMP & ~(PMC_COMP_VREF_MASK | PMC_COMP_VREFINPUT_MASK);
+
+    tmpReg |= PMC_COMP_VREFINPUT(config->vrefSource) | PMC_COMP_VREF(config->vrefValue);
+
+    PMC->COMP = tmpReg;
+}

bsp/lpc55sxx/Libraries/LPC55S06/LPC55S06/drivers/fsl_cmp.h

+/*
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FSL_CMP_H_
+#define __FSL_CMP_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup cmp_1
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions.
+ *****************************************************************************/
+/*! @name Driver version */
+/*@{*/
+/*! @brief Driver version 2.2.1. */
+#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 1U))
+/*@}*/
+
+/*! @brief CMP input mux for positive and negative sides. */
+enum _cmp_input_mux
+{
+    kCMP_InputVREF = 0U, /*!< Cmp input from VREF. */
+    kCMP_Input1    = 1U, /*!< Cmp input source 1. */
+    kCMP_Input2    = 2U, /*!< Cmp input source 2. */
+    kCMP_Input3    = 3U, /*!< Cmp input source 3. */
+    kCMP_Input4    = 4U, /*!< Cmp input source 4. */
+    kCMP_Input5    = 5U, /*!< Cmp input source 5. */
+};
+
+/*! @brief CMP interrupt type. */
+enum _cmp_interrupt_type
+{
+    kCMP_EdgeDisable       = 0U, /*!< Disable edge interupt. */
+    kCMP_EdgeRising        = 2U, /*!< Interrupt on falling edge. */
+    kCMP_EdgeFalling       = 4U, /*!< Interrupt on rising edge. */
+    kCMP_EdgeRisingFalling = 6U, /*!< Interrupt on both rising and falling edges. */
+
+    kCMP_LevelDisable = 1U, /*!< Disable level interupt. */
+    kCMP_LevelHigh    = 3U, /*!< Interrupt on high level. */
+    kCMP_LevelLow     = 5U, /*!< Interrupt on low level. */
+};
+
+/*! @brief CMP Voltage Reference source. */
+typedef enum _cmp_vref_source
+{
+    KCMP_VREFSourceVDDA         = 1U, /*!< Select VDDA as VREF. */
+    KCMP_VREFSourceInternalVREF = 0U, /*!< Select internal VREF as VREF. */
+} cmp_vref_source_t;
+
+typedef struct _cmp_vref_config
+{
+    cmp_vref_source_t vrefSource; /*!< Reference voltage source. */
+    uint8_t vrefValue; /*!< Reference voltage step. Available range is 0-31. Per step equals to VREFINPUT/31. */
+} cmp_vref_config_t;
+
+/*! @brief CMP Filter sample mode. */
+typedef enum _cmp_filtercgf_samplemode
+{
+    kCMP_FilterSampleMode0 = 0U, /*!< Bypass mode. Filtering is disabled. */
+    kCMP_FilterSampleMode1 = 1U, /*!< Filter 1 clock period. */
+    kCMP_FilterSampleMode2 = 2U, /*!< Filter 2 clock period. */
+    kCMP_FilterSampleMode3 = 3U  /*!< Filter 3 clock period. */
+} cmp_filtercgf_samplemode_t;
+
+/*! @brief CMP Filter clock divider. */
+typedef enum _cmp_filtercgf_clkdiv
+{
+    kCMP_FilterClockDivide1  = 0U, /*!< Filter clock period duration equals 1 analog comparator clock period. */
+    kCMP_FilterClockDivide2  = 1U, /*!< Filter clock period duration equals 2 analog comparator clock period. */
+    kCMP_FilterClockDivide4  = 2U, /*!< Filter clock period duration equals 4 analog comparator clock period. */
+    kCMP_FilterClockDivide8  = 3U, /*!< Filter clock period duration equals 8 analog comparator clock period. */
+    kCMP_FilterClockDivide16 = 4U, /*!< Filter clock period duration equals 16 analog comparator clock period. */
+    kCMP_FilterClockDivide32 = 5U, /*!< Filter clock period duration equals 32 analog comparator clock period. */
+    kCMP_FilterClockDivide64 = 6U  /*!< Filter clock period duration equals 64 analog comparator clock period. */
+} cmp_filtercgf_clkdiv_t;
+
+/*! @brief CMP configuration structure. */
+typedef struct _cmp_config
+{
+    bool enableHysteresis;                     /*!< Enable hysteresis. */
+    bool enableLowPower;                       /*!< Enable low power mode. */
+    cmp_filtercgf_clkdiv_t filterClockDivider; /* Filter clock divider. Filter clock equals the Analog Comparator clock
+                                                  divided by 2^FILTERCGF_CLKDIV. */
+    cmp_filtercgf_samplemode_t
+        filterSampleMode; /* Filter sample mode. Control the filtering of the Analog Comparator output. */
+} cmp_config_t;
+
+/*************************************************************************************************
+ * API
+ ************************************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief CMP initialization.
+ *
+ * This function enables the CMP module and do necessary settings.
+ *
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_Init(const cmp_config_t *config);
+
+/*!
+ * @brief CMP deinitialization.
+ *
+ * This function gates the clock for CMP module.
+ */
+void CMP_Deinit(void);
+
+/*!
+ * @brief Initializes the CMP user configuration structure.
+ *
+ * This function initializes the user configuration structure to these default values.
+ * @code
+ *   config->enableHysteresis    = true;
+ *   config->enableLowPower      = true;
+ *   config->filterClockDivider  = kCMP_FilterClockDivide1;
+ *   config->filterSampleMode    = kCMP_FilterSampleMode0;
+ * @endcode
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_GetDefaultConfig(cmp_config_t *config);
+
+/* @} */
+
+/*!
+ * @name Compare Interface
+ * @{
+ */
+
+/*
+ * @brief Set the input channels for the comparator.
+ *
+ * @param positiveChannel Positive side input channel number. See "_cmp_input_mux".
+ * @param negativeChannel Negative side input channel number. See "_cmp_input_mux".
+ */
+static inline void CMP_SetInputChannels(uint8_t positiveChannel, uint8_t negativeChannel)
+{
+    PMC->COMP &= ~(PMC_COMP_PMUX_MASK | PMC_COMP_NMUX_MASK);
+    PMC->COMP |= (PMC_COMP_PMUX(positiveChannel) | PMC_COMP_NMUX(negativeChannel));
+}
+
+/*!
+ * @brief Configures the VREFINPUT.
+ *
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_SetVREF(const cmp_vref_config_t *config);
+
+/*!
+ * @brief Get CMP compare output.
+ *
+ * @return The output result. true: voltage on positive side is greater than negative side.
+ *                            false: voltage on positive side is lower than negative side.
+ */
+static inline bool CMP_GetOutput(void)
+{
+    return SYSCON_COMP_INT_STATUS_VAL_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_VAL_MASK);
+}
+
+/* @} */
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief CMP enable interrupt.
+ *
+ * @param type CMP interrupt type. See "_cmp_interrupt_type".
+ */
+static inline void CMP_EnableInterrupt(uint32_t type)
+{
+    SYSCON->COMP_INT_CTRL |= (SYSCON_COMP_INT_CTRL_INT_CTRL(type) | SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK);
+}
+
+/*!
+ * @brief CMP disable interrupt.
+ *
+ */
+static inline void CMP_DisableInterrupt(void)
+{
+    SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK;
+}
+
+/*!
+ * @brief CMP clear interrupt.
+ *
+ */
+static inline void CMP_ClearInterrupt(void)
+{
+    SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK;
+}
+
+/*!
+ * @brief Select which Analog comparator output (filtered or un-filtered) is used for interrupt detection.
+ *
+ * @param enable false: Select Analog Comparator raw output (unfiltered) as input for interrupt detection.
+ *               true: Select Analog Comparator filtered output as input for interrupt detection.
+ *
+ * @note: When CMP is configured as the wakeup source in power down mode, this function must use the raw output as the
+ *        interupt source, that is, call this function and set parameter enable to false.
+ */
+static inline void CMP_EnableFilteredInterruptSource(bool enable)
+{
+    if (enable)
+    {
+        SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK;
+    }
+    else
+    {
+        SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK;
+    }
+}
+/* @} */
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Get CMP interrupt status before interupt enable.
+ *
+ * @return Interrupt status. true: interrupt pending,
+ *                           false: no interrupt pending.
+ */
+static inline bool CMP_GetPreviousInterruptStatus(void)
+{
+    return SYSCON_COMP_INT_STATUS_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_STATUS_MASK);
+}
+
+/*!
+ * @brief Get CMP interrupt status after interupt enable.
+ *
+ * @return Interrupt status. true: interrupt pending,
+ *                           false: no interrupt pending.
+ */
+static inline bool CMP_GetInterruptStatus(void)
+{
+    return SYSCON_COMP_INT_STATUS_INT_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK);
+}
+/* @} */
+
+/*!
+ * @name Filter Interface
+ * @{
+ */
+
+/*!
+ * @brief CMP Filter Sample Config.
+ *
+ * This function allows the users to configure the sampling mode and clock divider of the CMP Filter.
+ *
+ * @param filterSampleMode   CMP Select filter sample mode
+ * @param filterClockDivider CMP Set fileter clock divider
+ */
+static inline void CMP_FilterSampleConfig(cmp_filtercgf_samplemode_t filterSampleMode,
+                                          cmp_filtercgf_clkdiv_t filterClockDivider)
+{
+    uint32_t comp = PMC->COMP;
+
+    comp &= ~(PMC_COMP_FILTERCGF_CLKDIV_MASK | PMC_COMP_FILTERCGF_SAMPLEMODE_MASK);
+    comp |= (((uint32_t)filterClockDivider << PMC_COMP_FILTERCGF_CLKDIV_SHIFT) |
+             ((uint32_t)filterSampleMode << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT));
+
+    PMC->COMP = comp;
+}
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+#endif /* __FSL_CMP_H_ */

bsp/lpc55sxx/Libraries/LPC55S06/LPC55S06/fsl_device_registers.h

+/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_LPC55S06JBD64) || defined(CPU_LPC55S06JHI48))
+
+#define LPC55S06_SERIES
+
+/* CMSIS-style register definitions */
+#include "LPC55S06.h"
+/* CPU specific feature definitions */
+#include "LPC55S06_features.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/