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体验新版 GitCode,发现更多精彩内容 >>
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75e4c9dd
编写于
4月 09, 2021
作者:
Nameless-Y
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差异文件
[bsp]update GPL license to Apache-2.0, and format files
上级
31cb379d
变更
320
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隐藏空白更改
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Showing
320 changed file
with
15940 addition
and
18871 deletion
+15940
-18871
bsp/CME_M7/applications/application.c
bsp/CME_M7/applications/application.c
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bsp/CME_M7/drivers/board.c
bsp/CME_M7/drivers/board.c
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bsp/CME_M7/drivers/board.h
bsp/CME_M7/drivers/board.h
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bsp/allwinner_tina/libcpu/context_gcc.S
bsp/allwinner_tina/libcpu/context_gcc.S
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bsp/amebaz/libraries/smartconfig/inc/smartconfig.h
bsp/amebaz/libraries/smartconfig/inc/smartconfig.h
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bsp/asm9260t/applications/application.c
bsp/asm9260t/applications/application.c
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bsp/asm9260t/drivers/board.c
bsp/asm9260t/drivers/board.c
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bsp/asm9260t/drivers/board.h
bsp/asm9260t/drivers/board.h
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bsp/asm9260t/drivers/led.c
bsp/asm9260t/drivers/led.c
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bsp/asm9260t/drivers/led.h
bsp/asm9260t/drivers/led.h
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bsp/asm9260t/drivers/usart.c
bsp/asm9260t/drivers/usart.c
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bsp/asm9260t/platform/gpio.c
bsp/asm9260t/platform/gpio.c
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bsp/asm9260t/platform/gpio.h
bsp/asm9260t/platform/gpio.h
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bsp/asm9260t/platform/interrupt.c
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bsp/asm9260t/platform/interrupt.h
bsp/asm9260t/platform/interrupt.h
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bsp/asm9260t/platform/reset.c
bsp/asm9260t/platform/reset.c
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bsp/asm9260t/platform/rt_low_level_init.c
bsp/asm9260t/platform/rt_low_level_init.c
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bsp/asm9260t/platform/rt_low_level_init.h
bsp/asm9260t/platform/rt_low_level_init.h
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bsp/asm9260t/platform/system_clock.c
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bsp/asm9260t/platform/uart.c
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bsp/at91sam9260/applications/application.c
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bsp/hifive1/drivers/board.h
bsp/hifive1/drivers/board.h
+2
-16
bsp/hifive1/drivers/drv_usart.c
bsp/hifive1/drivers/drv_usart.c
+3
-17
bsp/hifive1/drivers/interrupt.c
bsp/hifive1/drivers/interrupt.c
+7
-21
bsp/hifive1/drivers/interrupt.h
bsp/hifive1/drivers/interrupt.h
+3
-17
bsp/imx6sx/cortex-a9/drivers/emac_drv.c
bsp/imx6sx/cortex-a9/drivers/emac_drv.c
+74
-73
bsp/imx6sx/cortex-a9/drivers/emac_drv.h
bsp/imx6sx/cortex-a9/drivers/emac_drv.h
+2
-1
bsp/imx6sx/cortex-a9/drivers/serial.c
bsp/imx6sx/cortex-a9/drivers/serial.c
+2
-1
bsp/imx6sx/cortex-a9/drivers/serial.h
bsp/imx6sx/cortex-a9/drivers/serial.h
+2
-1
bsp/imx6ul/drivers/serial.c
bsp/imx6ul/drivers/serial.c
+2
-1
bsp/imx6ul/drivers/serial.h
bsp/imx6ul/drivers/serial.h
+2
-1
bsp/imxrt/libraries/drivers/drv_lcd.c
bsp/imxrt/libraries/drivers/drv_lcd.c
+3
-7
bsp/imxrt/libraries/drivers/drv_lcd.h
bsp/imxrt/libraries/drivers/drv_lcd.h
+2
-6
bsp/lpc43xx/M0/applications/vbus_drv.c
bsp/lpc43xx/M0/applications/vbus_drv.c
+1
-0
bsp/lpc43xx/M0/applications/vbus_hw.h
bsp/lpc43xx/M0/applications/vbus_hw.h
+1
-0
bsp/lpc43xx/M4/applications/vbus_drv.c
bsp/lpc43xx/M4/applications/vbus_drv.c
+1
-0
bsp/lpc43xx/M4/applications/vbus_hw.h
bsp/lpc43xx/M4/applications/vbus_hw.h
+1
-0
bsp/ls1bdev/drivers/board.c
bsp/ls1bdev/drivers/board.c
+5
-9
bsp/ls1bdev/drivers/board.h
bsp/ls1bdev/drivers/board.h
+4
-8
bsp/ls1bdev/drivers/display_controller.c
bsp/ls1bdev/drivers/display_controller.c
+179
-183
bsp/ls1bdev/drivers/display_controller.h
bsp/ls1bdev/drivers/display_controller.h
+27
-31
bsp/ls1bdev/ls1b_ram.lds
bsp/ls1bdev/ls1b_ram.lds
+23
-27
bsp/ls1cdev/drivers/drv_spi.c
bsp/ls1cdev/drivers/drv_spi.c
+2
-16
bsp/ls1cdev/ls1c_ram.lds
bsp/ls1cdev/ls1c_ram.lds
+23
-27
bsp/m16c62p/applications/application.c
bsp/m16c62p/applications/application.c
+3
-7
bsp/m16c62p/applications/startup.c
bsp/m16c62p/applications/startup.c
+42
-46
bsp/m16c62p/drivers/board.c
bsp/m16c62p/drivers/board.c
+4
-8
bsp/m16c62p/drivers/board.h
bsp/m16c62p/drivers/board.h
+2
-6
bsp/m16c62p/drivers/bsp.c
bsp/m16c62p/drivers/bsp.c
+24
-28
bsp/m16c62p/drivers/bsp.h
bsp/m16c62p/drivers/bsp.h
+2
-6
bsp/m16c62p/drivers/interrupts_gcc.S
bsp/m16c62p/drivers/interrupts_gcc.S
+16
-20
bsp/m16c62p/drivers/interrupts_iar.asm
bsp/m16c62p/drivers/interrupts_iar.asm
+9
-13
bsp/m16c62p/drivers/uart.c
bsp/m16c62p/drivers/uart.c
+137
-141
bsp/m16c62p/drivers/vectors_iar.asm
bsp/m16c62p/drivers/vectors_iar.asm
+3
-7
bsp/m16c62p/readme.txt
bsp/m16c62p/readme.txt
+8
-12
bsp/mb9bf500r/CMSIS/start_gcc.S
bsp/mb9bf500r/CMSIS/start_gcc.S
+28
-32
bsp/mb9bf500r/CMSIS/start_iar.S
bsp/mb9bf500r/CMSIS/start_iar.S
+268
-272
bsp/mb9bf500r/CMSIS/start_rvds.S
bsp/mb9bf500r/CMSIS/start_rvds.S
+2
-6
bsp/microblaze/application.c
bsp/microblaze/application.c
+3
-7
bsp/microblaze/startup.c
bsp/microblaze/startup.c
+34
-38
bsp/mini2440/drivers/board.c
bsp/mini2440/drivers/board.c
+36
-40
bsp/mini2440/drivers/board.h
bsp/mini2440/drivers/board.h
+2
-6
bsp/mini2440/drivers/key.c
bsp/mini2440/drivers/key.c
+251
-255
bsp/mini2440/drivers/lcd_a70.c
bsp/mini2440/drivers/lcd_a70.c
+6
-10
bsp/mini2440/drivers/lcd_n35.c
bsp/mini2440/drivers/lcd_n35.c
+7
-11
bsp/mini2440/drivers/lcd_t35.c
bsp/mini2440/drivers/lcd_t35.c
+7
-11
bsp/mini2440/drivers/lcd_x35.c
bsp/mini2440/drivers/lcd_x35.c
+9
-13
bsp/mini2440/drivers/led.c
bsp/mini2440/drivers/led.c
+7
-11
bsp/mini2440/drivers/led.h
bsp/mini2440/drivers/led.h
+2
-6
bsp/mini2440/drivers/touch.c
bsp/mini2440/drivers/touch.c
+21
-25
bsp/mini4020/applications/application.c
bsp/mini4020/applications/application.c
+69
-73
bsp/mini4020/applications/startup.c
bsp/mini4020/applications/startup.c
+38
-42
bsp/mini4020/drivers/board.h
bsp/mini4020/drivers/board.h
+2
-6
bsp/mini4020/drivers/dm9161.c
bsp/mini4020/drivers/dm9161.c
+482
-486
bsp/mini4020/drivers/dm9161.h
bsp/mini4020/drivers/dm9161.h
+20
-24
bsp/mini4020/drivers/lcd.c
bsp/mini4020/drivers/lcd.c
+4
-8
bsp/mini4020/drivers/lcdc.c
bsp/mini4020/drivers/lcdc.c
+9
-13
bsp/mini4020/drivers/lcdc.h
bsp/mini4020/drivers/lcdc.h
+19
-23
bsp/mini4020/drivers/mii.h
bsp/mini4020/drivers/mii.h
+12
-16
bsp/mini4020/drivers/sdcard.c
bsp/mini4020/drivers/sdcard.c
+3
-7
bsp/mini4020/drivers/sdcard.h
bsp/mini4020/drivers/sdcard.h
+2
-6
bsp/nios_ii/application.c
bsp/nios_ii/application.c
+2
-6
bsp/nios_ii/board.c
bsp/nios_ii/board.c
+2
-6
bsp/nios_ii/board.h
bsp/nios_ii/board.h
+2
-6
bsp/nios_ii/startup.c
bsp/nios_ii/startup.c
+2
-6
bsp/nrf51822/applications/application.c
bsp/nrf51822/applications/application.c
+2
-6
bsp/nrf51822/drivers/board.c
bsp/nrf51822/drivers/board.c
+2
-6
bsp/nrf51822/drivers/board.h
bsp/nrf51822/drivers/board.h
+2
-6
bsp/nrf51822/drivers/uart.c
bsp/nrf51822/drivers/uart.c
+2
-6
bsp/nrf51822/drivers/uart.h
bsp/nrf51822/drivers/uart.h
+2
-6
bsp/nrf5x/libraries/templates/nrf52x/applications/application.c
...f5x/libraries/templates/nrf52x/applications/application.c
+2
-6
bsp/nv32f100x/app/src/ledapp.c
bsp/nv32f100x/app/src/ledapp.c
+7
-11
bsp/nv32f100x/app/src/main.c
bsp/nv32f100x/app/src/main.c
+2
-16
bsp/nv32f100x/board/inc/board.h
bsp/nv32f100x/board/inc/board.h
+2
-6
bsp/nv32f100x/board/inc/drv_uart.h
bsp/nv32f100x/board/inc/drv_uart.h
+2
-6
bsp/nv32f100x/board/src/board.c
bsp/nv32f100x/board/src/board.c
+7
-11
bsp/nv32f100x/board/src/drv_uart.c
bsp/nv32f100x/board/src/drv_uart.c
+2
-6
bsp/pic32ethernet/application.c
bsp/pic32ethernet/application.c
+3
-7
bsp/pic32ethernet/board.c
bsp/pic32ethernet/board.c
+16
-20
bsp/pic32ethernet/console.c
bsp/pic32ethernet/console.c
+4
-8
bsp/pic32ethernet/startup.c
bsp/pic32ethernet/startup.c
+26
-30
bsp/qemu-vexpress-gemini/applications/application.c
bsp/qemu-vexpress-gemini/applications/application.c
+3
-7
bsp/qemu-vexpress-gemini/applications/startup.c
bsp/qemu-vexpress-gemini/applications/startup.c
+2
-6
bsp/qemu-vexpress-gemini/cpu/context_gcc.S
bsp/qemu-vexpress-gemini/cpu/context_gcc.S
+2
-16
bsp/qemu-vexpress-gemini/cpu/cp15_gcc.S
bsp/qemu-vexpress-gemini/cpu/cp15_gcc.S
+2
-17
bsp/qemu-vexpress-gemini/cpu/cpu.c
bsp/qemu-vexpress-gemini/cpu/cpu.c
+9
-13
bsp/qemu-vexpress-gemini/cpu/gic.c
bsp/qemu-vexpress-gemini/cpu/gic.c
+2
-6
bsp/qemu-vexpress-gemini/cpu/gic.h
bsp/qemu-vexpress-gemini/cpu/gic.h
+2
-6
bsp/qemu-vexpress-gemini/cpu/interrupt.c
bsp/qemu-vexpress-gemini/cpu/interrupt.c
+2
-6
bsp/qemu-vexpress-gemini/cpu/interrupt.h
bsp/qemu-vexpress-gemini/cpu/interrupt.h
+22
-26
bsp/qemu-vexpress-gemini/cpu/mmu.c
bsp/qemu-vexpress-gemini/cpu/mmu.c
+2
-6
bsp/qemu-vexpress-gemini/cpu/stack.c
bsp/qemu-vexpress-gemini/cpu/stack.c
+28
-32
bsp/qemu-vexpress-gemini/cpu/start_gcc.S
bsp/qemu-vexpress-gemini/cpu/start_gcc.S
+7
-21
bsp/qemu-vexpress-gemini/cpu/trap.c
bsp/qemu-vexpress-gemini/cpu/trap.c
+3
-7
bsp/qemu-vexpress-gemini/cpu/vector_gcc.S
bsp/qemu-vexpress-gemini/cpu/vector_gcc.S
+3
-17
bsp/qemu-vexpress-gemini/drivers/board.c
bsp/qemu-vexpress-gemini/drivers/board.c
+2
-6
bsp/qemu-vexpress-gemini/drivers/board.h
bsp/qemu-vexpress-gemini/drivers/board.h
+2
-6
bsp/qemu-vexpress-gemini/drivers/serial.c
bsp/qemu-vexpress-gemini/drivers/serial.c
+2
-21
bsp/qemu-vexpress-gemini/drivers/serial.h
bsp/qemu-vexpress-gemini/drivers/serial.h
+2
-21
bsp/qemu-vexpress-gemini/drivers/vbus_drv.c
bsp/qemu-vexpress-gemini/drivers/vbus_drv.c
+2
-21
bsp/qemu-vexpress-gemini/drivers/vbus_hw.h
bsp/qemu-vexpress-gemini/drivers/vbus_hw.h
+2
-20
bsp/raspberry-pi/raspi2/applications/main.c
bsp/raspberry-pi/raspi2/applications/main.c
+2
-16
bsp/raspberry-pi/raspi2/applications/mnt.c
bsp/raspberry-pi/raspi2/applications/mnt.c
+2
-16
bsp/raspberry-pi/raspi2/cpu/context_gcc.S
bsp/raspberry-pi/raspi2/cpu/context_gcc.S
+2
-16
bsp/raspberry-pi/raspi2/cpu/cp15_gcc.S
bsp/raspberry-pi/raspi2/cpu/cp15_gcc.S
+2
-17
bsp/raspberry-pi/raspi2/cpu/cpu.c
bsp/raspberry-pi/raspi2/cpu/cpu.c
+2
-6
bsp/raspberry-pi/raspi2/cpu/interrupt.c
bsp/raspberry-pi/raspi2/cpu/interrupt.c
+2
-6
bsp/raspberry-pi/raspi2/cpu/mmu.c
bsp/raspberry-pi/raspi2/cpu/mmu.c
+2
-6
bsp/raspberry-pi/raspi2/cpu/stack.c
bsp/raspberry-pi/raspi2/cpu/stack.c
+2
-6
bsp/raspberry-pi/raspi2/cpu/start_gcc.S
bsp/raspberry-pi/raspi2/cpu/start_gcc.S
+19
-33
bsp/raspberry-pi/raspi2/cpu/trap.c
bsp/raspberry-pi/raspi2/cpu/trap.c
+2
-6
bsp/raspberry-pi/raspi2/cpu/vector_gcc.S
bsp/raspberry-pi/raspi2/cpu/vector_gcc.S
+2
-16
bsp/raspberry-pi/raspi2/driver/board.c
bsp/raspberry-pi/raspi2/driver/board.c
+2
-16
bsp/raspberry-pi/raspi2/driver/board.h
bsp/raspberry-pi/raspi2/driver/board.h
+2
-16
bsp/raspberry-pi/raspi2/driver/drv_uart.c
bsp/raspberry-pi/raspi2/driver/drv_uart.c
+2
-16
bsp/raspberry-pi/raspi2/driver/drv_uart.h
bsp/raspberry-pi/raspi2/driver/drv_uart.h
+2
-16
bsp/raspberry-pi/raspi2/link.lds
bsp/raspberry-pi/raspi2/link.lds
+2
-15
bsp/raspberry-pi/raspi3-32/link.lds
bsp/raspberry-pi/raspi3-32/link.lds
+2
-15
bsp/raspberry-pi/raspi3-64/link.lds
bsp/raspberry-pi/raspi3-64/link.lds
+4
-17
bsp/raspberry-pi/raspi4-32/link.lds
bsp/raspberry-pi/raspi4-32/link.lds
+4
-17
bsp/raspberry-pi/raspi4-64/link.lds
bsp/raspberry-pi/raspi4-64/link.lds
+4
-17
bsp/realview-a8/applications/application.c
bsp/realview-a8/applications/application.c
+3
-7
bsp/realview-a8/applications/startup.c
bsp/realview-a8/applications/startup.c
+2
-6
bsp/realview-a8/drivers/board.c
bsp/realview-a8/drivers/board.c
+2
-6
bsp/realview-a8/drivers/board.h
bsp/realview-a8/drivers/board.h
+2
-6
bsp/realview-a8/drivers/serial.c
bsp/realview-a8/drivers/serial.c
+2
-21
bsp/realview-a8/drivers/serial.h
bsp/realview-a8/drivers/serial.h
+2
-21
bsp/realview-a8/rtt_api.h
bsp/realview-a8/rtt_api.h
+6
-24
bsp/rm48x50/application/startup.c
bsp/rm48x50/application/startup.c
+31
-35
bsp/sam7x/applications/application.c
bsp/sam7x/applications/application.c
+29
-33
bsp/sam7x/applications/startup.c
bsp/sam7x/applications/startup.c
+40
-44
bsp/sep6200/application/application.c
bsp/sep6200/application/application.c
+22
-36
bsp/sep6200/application/startup.c
bsp/sep6200/application/startup.c
+25
-39
bsp/sep6200/board.h
bsp/sep6200/board.h
+2
-16
bsp/sep6200/drivers/board.c
bsp/sep6200/drivers/board.c
+57
-71
bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c
bsp/stm32/stm32f429-st-disco/board/ports/ili9341.c
+2
-16
bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h
bsp/stm32/stm32f429-st-disco/board/ports/ili9341.h
+2
-16
bsp/stm32/stm32l475-atk-pandora/board/board.c
bsp/stm32/stm32l475-atk-pandora/board/board.c
+2
-6
bsp/stm32/stm32l496-ali-developer/board/board.c
bsp/stm32/stm32l496-ali-developer/board/board.c
+2
-6
bsp/stm32/stm32l496-st-nucleo/board/board.c
bsp/stm32/stm32l496-st-nucleo/board/board.c
+2
-6
bsp/upd70f3454/applications/application.c
bsp/upd70f3454/applications/application.c
+2
-6
bsp/upd70f3454/applications/startup.c
bsp/upd70f3454/applications/startup.c
+4
-8
bsp/upd70f3454/drivers/board.c
bsp/upd70f3454/drivers/board.c
+2
-6
bsp/upd70f3454/drivers/board.h
bsp/upd70f3454/drivers/board.h
+3
-7
bsp/upd70f3454/drivers/uart.c
bsp/upd70f3454/drivers/uart.c
+3
-7
bsp/xplorer4330/applications/application.c
bsp/xplorer4330/applications/application.c
+2
-6
bsp/xplorer4330/applications/startup.c
bsp/xplorer4330/applications/startup.c
+2
-6
bsp/xplorer4330/drivers/board.c
bsp/xplorer4330/drivers/board.c
+2
-6
bsp/xplorer4330/drivers/board.h
bsp/xplorer4330/drivers/board.h
+2
-6
bsp/xplorer4330/drivers/drv_uart.c
bsp/xplorer4330/drivers/drv_uart.c
+6
-10
未找到文件。
bsp/CME_M7/applications/application.c
浏览文件 @
75e4c9dd
/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2014, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
@@ -32,10 +28,10 @@ int rt_application_init()
tid
=
rt_thread_create
(
"init"
,
rt_init_thread_entry
,
RT_NULL
,
RT_NULL
,
2048
,
RT_THREAD_PRIORITY_MAX
/
3
,
20
);
RT_THREAD_PRIORITY_MAX
/
3
,
20
);
if
(
tid
!=
RT_NULL
)
rt_thread_startup
(
tid
);
...
...
bsp/CME_M7/drivers/board.c
浏览文件 @
75e4c9dd
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009-2014, RT-Thread Develop Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
bsp/CME_M7/drivers/board.h
浏览文件 @
75e4c9dd
/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2009-2014, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
@@ -18,7 +14,7 @@
#include "cmem7_includes.h"
//#include "cmem7_retarget.h"
#define SRAM_SIZE 64
// KB
#define SRAM_SIZE 64
// KB
#define SRAM_END (0x20000000 + SRAM_SIZE * 1024)
//#define RT_USING_UART0
...
...
bsp/allwinner_tina/libcpu/context_gcc.S
浏览文件 @
75e4c9dd
;/*
; * File : context_iar.S
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2006, RT-Thread Development Team
; * Copyright (c) 2006-2021, RT-Thread Development Team
; *
; * This program is free software; you can redistribute it and/or modify
; * it under the terms of the GNU General Public License as published by
; * the Free Software Foundation; either version 2 of the License, or
; * (at your option) any later version.
; *
; * This program is distributed in the hope that it will be useful,
; * but WITHOUT ANY WARRANTY; without even the implied warranty of
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; * GNU General Public License for more details.
; *
; * You should have received a copy of the GNU General Public License along
; * with this program; if not, write to the Free Software Foundation, Inc.,
; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
...
...
bsp/amebaz/libraries/smartconfig/inc/smartconfig.h
浏览文件 @
75e4c9dd
/*
* File : smartconfig.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
bsp/asm9260t/applications/application.c
浏览文件 @
75e4c9dd
/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2015, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author
Notes
* 2011-01-13 weety
first version
* Date Author
Notes
* 2011-01-13 weety
first version
* 2015-04-27 ArdaFu Port bsp from at91sam9260 to asm9260t
*/
...
...
bsp/asm9260t/drivers/board.c
浏览文件 @
75e4c9dd
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
bsp/asm9260t/drivers/board.h
浏览文件 @
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/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
bsp/asm9260t/drivers/led.c
浏览文件 @
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/*
* File : led.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2015, RT-Thread Develop Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
bsp/asm9260t/drivers/led.h
浏览文件 @
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/*
* File : led.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
bsp/asm9260t/drivers/usart.c
浏览文件 @
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/*
* File : usart.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2015, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
@@ -72,12 +58,12 @@ static rt_err_t asm_usart_configure(struct rt_serial_device *serial,
RT_ASSERT
(
serial
!=
RT_NULL
);
RT_ASSERT
(
cfg
!=
RT_NULL
);
uart
=
(
asm_uart_t
*
)
serial
->
parent
.
user_data
;
Hw_UartDisable
(
uart
->
port
);
Hw_UartReset
(
uart
->
port
);
Hw_UartConfig
(
uart
->
port
,
cfg
->
baud_rate
,
cfg
->
data_bits
,
Hw_UartConfig
(
uart
->
port
,
cfg
->
baud_rate
,
cfg
->
data_bits
,
cfg
->
stop_bits
,
cfg
->
parity
);
Hw_UartEnable
(
uart
->
port
);
...
...
bsp/asm9260t/platform/gpio.c
浏览文件 @
75e4c9dd
/*
* File : interrupt.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2015-04-14 ArdaFu first version
*/
#include "asm9260t.h"
#include "rtthread.h"
...
...
bsp/asm9260t/platform/gpio.h
浏览文件 @
75e4c9dd
/*
* File : interrupt.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
bsp/asm9260t/platform/interrupt.c
浏览文件 @
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/*
* File : interrupt.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2015, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
bsp/asm9260t/platform/interrupt.h
浏览文件 @
75e4c9dd
/*
* File : interrupt.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
@@ -29,69 +15,69 @@
// IRQ Source
#define INT_ARM_COMMRX 0
#define INT_ARM_COMMTX 1
#define INT_RTC 2
#define INT_GPIO0 3
#define INT_GPIO1 4
#define INT_GPIO2 5
#define INT_GPIO3 6
#define INT_GPIO4_IIS1 7
#define INT_USB0 8
#define INT_USB1 9
#define INT_USB0_DMA 10
#define INT_USB1_DMA 11
#define INT_MAC 12
#define INT_MAC_PMT 13
#define INT_NAND 14
#define INT_UART0 15
#define INT_UART1 16
#define INT_UART2 17
#define INT_UART3 18
#define INT_UART4 19
#define INT_UART5 20
#define INT_UART6 21
#define INT_UART7 22
#define INT_UART8 23
#define INT_UART9 24
#define INT_I2S0 25
#define INT_I2C0 26
#define INT_I2C1 27
#define INT_CAMIF 28
#define INT_TIMER0 29
#define INT_TIMER1 30
#define INT_TIMER2 31
#define INT_TIMER3 32
#define INT_ADC0 33
#define INT_DAC0 34
#define INT_USB0_RESUME_HOSTDISCONNECT 35
#define INT_USB0_VBUSVALID 36
#define INT_USB1_RESUME_HOSTDISCONNECT 37
#define INT_USB1_VBUSVALID 38
#define INT_DMA0_CH0 39
#define INT_DMA0_CH1 40
#define INT_DMA0_CH2 41
#define INT_DMA0_CH3 42
#define INT_DMA0_CH4 43
#define INT_DMA0_CH5 44
#define INT_DMA0_CH6 45
#define INT_DMA0_CH7 46
#define INT_DMA1_CH0 47
#define INT_DMA1_CH1 48
#define INT_DMA1_CH2 49
#define INT_DMA1_CH3 50
#define INT_DMA1_CH4 51
#define INT_DMA1_CH5 52
#define INT_DMA1_CH6 53
#define INT_DMA1_CH7 54
#define INT_WATCHDOG 55
#define INT_CAN0 56
#define INT_CAN1 57
#define INT_QEI 58
#define INT_MCPWM 59
#define INT_SPI0 60
#define INT_SPI1 61
#define INT_QUADSPI0 62
#define INT_ARM_COMMRX 0
#define INT_ARM_COMMTX 1
#define INT_RTC 2
#define INT_GPIO0 3
#define INT_GPIO1 4
#define INT_GPIO2 5
#define INT_GPIO3 6
#define INT_GPIO4_IIS1 7
#define INT_USB0 8
#define INT_USB1 9
#define INT_USB0_DMA 10
#define INT_USB1_DMA 11
#define INT_MAC 12
#define INT_MAC_PMT 13
#define INT_NAND 14
#define INT_UART0 15
#define INT_UART1 16
#define INT_UART2 17
#define INT_UART3 18
#define INT_UART4 19
#define INT_UART5 20
#define INT_UART6 21
#define INT_UART7 22
#define INT_UART8 23
#define INT_UART9 24
#define INT_I2S0 25
#define INT_I2C0 26
#define INT_I2C1 27
#define INT_CAMIF 28
#define INT_TIMER0 29
#define INT_TIMER1 30
#define INT_TIMER2 31
#define INT_TIMER3 32
#define INT_ADC0 33
#define INT_DAC0 34
#define INT_USB0_RESUME_HOSTDISCONNECT 35
#define INT_USB0_VBUSVALID 36
#define INT_USB1_RESUME_HOSTDISCONNECT 37
#define INT_USB1_VBUSVALID 38
#define INT_DMA0_CH0 39
#define INT_DMA0_CH1 40
#define INT_DMA0_CH2 41
#define INT_DMA0_CH3 42
#define INT_DMA0_CH4 43
#define INT_DMA0_CH5 44
#define INT_DMA0_CH6 45
#define INT_DMA0_CH7 46
#define INT_DMA1_CH0 47
#define INT_DMA1_CH1 48
#define INT_DMA1_CH2 49
#define INT_DMA1_CH3 50
#define INT_DMA1_CH4 51
#define INT_DMA1_CH5 52
#define INT_DMA1_CH6 53
#define INT_DMA1_CH7 54
#define INT_WATCHDOG 55
#define INT_CAN0 56
#define INT_CAN1 57
#define INT_QEI 58
#define INT_MCPWM 59
#define INT_SPI0 60
#define INT_SPI1 61
#define INT_QUADSPI0 62
#define INT_SSP0 63
#endif
bsp/asm9260t/platform/reset.c
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/*
* File : reset.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2015, RT-Thread Develop Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
bsp/asm9260t/platform/rt_low_level_init.c
浏览文件 @
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/*
* File : rt_low_level_init.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
bsp/asm9260t/platform/rt_low_level_init.h
浏览文件 @
75e4c9dd
/*
* File : rt_low_level_init.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
@@ -23,7 +9,7 @@
*/
#ifndef __RT_LOW_LEVEL_INIT_H__
#define __RT_LOW_LEVEL_INIT_H__
/*-------- Stack size of CPU modes -------------------------------------------*/
#define UND_STK_SIZE 512
#define SVC_STK_SIZE 4096
...
...
bsp/asm9260t/platform/system_clock.c
浏览文件 @
75e4c9dd
/*
* File : clock.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
@@ -28,269 +14,269 @@
static rt_list_t clocks;
struct clk {
char name[32];
rt_uint32_t rate_hz;
struct clk *parent;
rt_list_t node;
char name[32];
rt_uint32_t rate_hz;
struct clk *parent;
rt_list_t node;
};
static struct clk clk32k = {
"clk32k",
AT91_SLOW_CLOCK,
RT_NULL,
{RT_NULL, RT_NULL},
"clk32k",
AT91_SLOW_CLOCK,
RT_NULL,
{RT_NULL, RT_NULL},
};
static struct clk main_clk = {
"main",
0,
RT_NULL,
{RT_NULL, RT_NULL},
"main",
0,
RT_NULL,
{RT_NULL, RT_NULL},
};
static struct clk plla = {
"plla",
0,
RT_NULL,
{RT_NULL, RT_NULL},
"plla",
0,
RT_NULL,
{RT_NULL, RT_NULL},
};
static struct clk mck = {
"mck",
0,
RT_NULL,
{RT_NULL, RT_NULL},
"mck",
0,
RT_NULL,
{RT_NULL, RT_NULL},
};
static struct clk uhpck = {
"uhpck",
0,
RT_NULL,
{RT_NULL, RT_NULL},
"uhpck",
0,
RT_NULL,
{RT_NULL, RT_NULL},
};
static struct clk pllb = {
"pllb",
0,
&main_clk,
{RT_NULL, RT_NULL},
"pllb",
0,
&main_clk,
{RT_NULL, RT_NULL},
};
static struct clk udpck = {
"udpck",
0,
&pllb,
{RT_NULL, RT_NULL},
"udpck",
0,
&pllb,
{RT_NULL, RT_NULL},
};
static struct clk *const standard_pmc_clocks[] = {
// four primary clocks
&clk32k,
&main_clk,
&plla,
// four primary clocks
&clk32k,
&main_clk,
&plla,
// MCK
&mck
// MCK
&mck
};
// clocks cannot be de-registered no refcounting necessary
struct clk *clk_get(const char *id)
{
struct clk *clk;
rt_list_t *list;
for (list = (&clocks)->next; list != &clocks; list = list->next)
{
clk = (struct clk *)rt_list_entry(list, struct clk, node);
if (rt_strcmp(id, clk->name) == 0)
return clk;
}
return RT_NULL;
struct clk *clk;
rt_list_t *list;
for (list = (&clocks)->next; list != &clocks; list = list->next)
{
clk = (struct clk *)rt_list_entry(list, struct clk, node);
if (rt_strcmp(id, clk->name) == 0)
return clk;
}
return RT_NULL;
}
rt_uint32_t clk_get_rate(struct clk *clk)
{
rt_uint32_t
rate;
for (;;) {
rate = clk->rate_hz;
if (rate || !clk->parent)
break;
clk = clk->parent;
}
return rate;
rt_uint32_t
rate;
for (;;) {
rate = clk->rate_hz;
if (rate || !clk->parent)
break;
clk = clk->parent;
}
return rate;
}
static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
{
unsigned mul, div;
unsigned mul, div;
div = reg & 0xff;
mul = (reg >> 16) & 0x7ff;
if (div && mul) {
freq /= div;
freq *= mul + 1;
} else
freq = 0;
div = reg & 0xff;
mul = (reg >> 16) & 0x7ff;
if (div && mul) {
freq /= div;
freq *= mul + 1;
} else
freq = 0;
return freq;
return freq;
}
static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
{
unsigned i, div = 0, mul = 0, diff = 1 << 30;
unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
//PLL output max 240 MHz (or 180 MHz per errata)
if (out_freq > 240000000)
goto fail;
for (i = 1; i < 256; i++) {
int diff1;
unsigned input, mul1;
//
// PLL input between 1MHz and 32MHz per spec, but lower
// frequences seem necessary in some cases so allow 100K.
// Warning: some newer products need 2MHz min.
//
input = main_freq / i;
if (input < 100000)
continue;
if (input > 32000000)
continue;
mul1 = out_freq / input;
if (mul1 > 2048)
continue;
if (mul1 < 2)
goto fail;
diff1 = out_freq - input * mul1;
if (diff1 < 0)
diff1 = -diff1;
if (diff > diff1) {
diff = diff1;
div = i;
mul = mul1;
if (diff == 0)
break;
}
}
if (i == 256 && diff > (out_freq >> 5))
goto fail;
return ret | ((mul - 1) << 16) | div;
unsigned i, div = 0, mul = 0, diff = 1 << 30;
unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
//PLL output max 240 MHz (or 180 MHz per errata)
if (out_freq > 240000000)
goto fail;
for (i = 1; i < 256; i++) {
int diff1;
unsigned input, mul1;
//
// PLL input between 1MHz and 32MHz per spec, but lower
// frequences seem necessary in some cases so allow 100K.
// Warning: some newer products need 2MHz min.
//
input = main_freq / i;
if (input < 100000)
continue;
if (input > 32000000)
continue;
mul1 = out_freq / input;
if (mul1 > 2048)
continue;
if (mul1 < 2)
goto fail;
diff1 = out_freq - input * mul1;
if (diff1 < 0)
diff1 = -diff1;
if (diff > diff1) {
diff = diff1;
div = i;
mul = mul1;
if (diff == 0)
break;
}
}
if (i == 256 && diff > (out_freq >> 5))
goto fail;
return ret | ((mul - 1) << 16) | div;
fail:
return 0;
return 0;
}
static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
{
if (pll == &pllb && (reg & AT91_PMC_USB96M))
return freq / 2;
else
return freq;
if (pll == &pllb && (reg & AT91_PMC_USB96M))
return freq / 2;
else
return freq;
}
// PLLB generated USB full speed clock init
static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock)
{
rt_uint32_t at91_pllb_usb_init;
//
// USB clock init: choose 48 MHz PLLB value,
// disable 48MHz clock during usb peripheral suspend.
//
// REVISIT: assumes MCK doesn't derive from PLLB!
//
uhpck.parent = &pllb;
at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
at91_sys_write(AT91_CKGR_PLLBR, 0);
udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
rt_uint32_t at91_pllb_usb_init;
//
// USB clock init: choose 48 MHz PLLB value,
// disable 48MHz clock during usb peripheral suspend.
//
// REVISIT: assumes MCK doesn't derive from PLLB!
//
uhpck.parent = &pllb;
at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
at91_sys_write(AT91_CKGR_PLLBR, 0);
udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
}
static struct clk *at91_css_to_clk(unsigned long css)
{
switch (css) {
case AT91_PMC_CSS_SLOW:
return &clk32k;
case AT91_PMC_CSS_MAIN:
return &main_clk;
case AT91_PMC_CSS_PLLA:
return &plla;
case AT91_PMC_CSS_PLLB:
return &pllb;
}
return RT_NULL;
switch (css) {
case AT91_PMC_CSS_SLOW:
return &clk32k;
case AT91_PMC_CSS_MAIN:
return &main_clk;
case AT91_PMC_CSS_PLLA:
return &plla;
case AT91_PMC_CSS_PLLB:
return &pllb;
}
return RT_NULL;
}
#define false 0
#define true 1
int at91_clock_init(rt_uint32_t main_clock)
{
unsigned tmp, freq, mckr;
int i;
int pll_overclock = false;
//
// When the bootloader initialized the main oscillator correctly,
// there's no problem using the cycle counter. But if it didn't,
// or when using oscillator bypass mode, we must be told the speed
// of the main clock.
//
if (!main_clock) {
do {
tmp = at91_sys_read(AT91_CKGR_MCFR);
} while (!(tmp & AT91_PMC_MAINRDY));
main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
}
main_clk.rate_hz = main_clock;
// report if PLLA is more than mildly overclocked
plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
if (plla.rate_hz > 209000000)
pll_overclock = true;
if (pll_overclock)
;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
at91_pllb_usbfs_clock_init(main_clock);
//
// MCK and CPU derive from one of those primary clocks.
// For now, assume this parentage won't change.
//
mckr = at91_sys_read(AT91_PMC_MCKR);
mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
freq = mck.parent->rate_hz;
freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); // prescale
mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); // mdiv
// Register the PMC's standard clocks
rt_list_init(&clocks);
for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
rt_list_insert_after(&clocks, &pllb.node);
rt_list_insert_after(&clocks, &uhpck.node);
rt_list_insert_after(&clocks, &udpck.node);
// MCK and CPU clock are "always on"
//clk_enable(&mck);
//rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
//
freq / 1000000, (unsigned) mck.rate_hz / 1000000,
//
(unsigned) main_clock / 1000000,
//
((unsigned) main_clock % 1000000) / 1000); //cause blocked
return 0;
unsigned tmp, freq, mckr;
int i;
int pll_overclock = false;
//
// When the bootloader initialized the main oscillator correctly,
// there's no problem using the cycle counter. But if it didn't,
// or when using oscillator bypass mode, we must be told the speed
// of the main clock.
//
if (!main_clock) {
do {
tmp = at91_sys_read(AT91_CKGR_MCFR);
} while (!(tmp & AT91_PMC_MAINRDY));
main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
}
main_clk.rate_hz = main_clock;
// report if PLLA is more than mildly overclocked
plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
if (plla.rate_hz > 209000000)
pll_overclock = true;
if (pll_overclock)
;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
at91_pllb_usbfs_clock_init(main_clock);
//
// MCK and CPU derive from one of those primary clocks.
// For now, assume this parentage won't change.
//
mckr = at91_sys_read(AT91_PMC_MCKR);
mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
freq = mck.parent->rate_hz;
freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); // prescale
mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); // mdiv
// Register the PMC's standard clocks
rt_list_init(&clocks);
for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
rt_list_insert_after(&clocks, &pllb.node);
rt_list_insert_after(&clocks, &uhpck.node);
rt_list_insert_after(&clocks, &udpck.node);
// MCK and CPU clock are "always on"
//clk_enable(&mck);
//rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
//
freq / 1000000, (unsigned) mck.rate_hz / 1000000,
//
(unsigned) main_clock / 1000000,
//
((unsigned) main_clock % 1000000) / 1000); //cause blocked
return 0;
}
*/
...
...
@@ -298,6 +284,6 @@ int at91_clock_init(rt_uint32_t main_clock)
void
rt_hw_clock_init
(
void
)
{
//at91_clock_init(18432000);
//at91_clock_init(18432000);
}
bsp/asm9260t/platform/timer0.c
浏览文件 @
75e4c9dd
/*
* File : timer0.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2015, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
bsp/asm9260t/platform/timer0.h
浏览文件 @
75e4c9dd
/*
* File : timer0.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006-2015, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
bsp/asm9260t/platform/uart.c
浏览文件 @
75e4c9dd
/*
* File : interrupt.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2015-04-14 ArdaFu first version
*/
#include "asm9260t.h"
#include "rtthread.h"
#include "uart.h"
...
...
bsp/asm9260t/platform/uart.h
浏览文件 @
75e4c9dd
/*
* File : interrupt.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
@@ -50,16 +36,16 @@ typedef struct
volatile
rt_uint32_t
ISO7816STATUS
[
4
];
}
HW_USART_TypeDef
;
#define USART0
((HW_USART_TypeDef *)UART0_BASE)
#define USART1
((HW_USART_TypeDef *)UART1_BASE)
#define USART2
((HW_USART_TypeDef *)UART2_BASE)
#define USART3
((HW_USART_TypeDef *)UART3_BASE)
#define USART4
((HW_USART_TypeDef *)UART4_BASE)
#define USART5
((HW_USART_TypeDef *)UART5_BASE)
#define USART6
((HW_USART_TypeDef *)UART6_BASE)
#define USART7
((HW_USART_TypeDef *)UART7_BASE)
#define USART8
((HW_USART_TypeDef *)UART8_BASE)
#define USART9
((HW_USART_TypeDef *)UART9_BASE)
#define USART0
((HW_USART_TypeDef *)UART0_BASE)
#define USART1
((HW_USART_TypeDef *)UART1_BASE)
#define USART2
((HW_USART_TypeDef *)UART2_BASE)
#define USART3
((HW_USART_TypeDef *)UART3_BASE)
#define USART4
((HW_USART_TypeDef *)UART4_BASE)
#define USART5
((HW_USART_TypeDef *)UART5_BASE)
#define USART6
((HW_USART_TypeDef *)UART6_BASE)
#define USART7
((HW_USART_TypeDef *)UART7_BASE)
#define USART8
((HW_USART_TypeDef *)UART8_BASE)
#define USART9
((HW_USART_TypeDef *)UART9_BASE)
#define ASM_UART_INTR_RXIS (1UL << 4)
...
...
@@ -105,7 +91,7 @@ typedef struct
extern
void
Hw_UartDisable
(
HW_USART_TypeDef
*
uartBase
);
extern
void
Hw_UartEnable
(
HW_USART_TypeDef
*
uartBase
);
extern
void
Hw_UartReset
(
HW_USART_TypeDef
*
uartBase
);
extern
void
Hw_UartConfig
(
HW_USART_TypeDef
*
uartBase
,
int
baudRate
,
extern
void
Hw_UartConfig
(
HW_USART_TypeDef
*
uartBase
,
int
baudRate
,
int
dataBits
,
int
stopBits
,
int
parity
);
extern
void
Hw_UartInit
(
int
index
);
#endif
bsp/at91sam9260/applications/application.c
浏览文件 @
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/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author
Notes
* 2011-01-13 weety
first version
* Date Author
Notes
* 2011-01-13 weety
first version
*/
/**
...
...
@@ -48,106 +34,106 @@ static int rt_led_app_init(void);
int
main
(
void
)
{
int
timeout
=
0
;
int
timeout
=
0
;
/* Filesystem Initialization */
#ifdef RT_USING_DFS
{
{
#if defined(RT_USING_DFS_ROMFS)
if
(
dfs_mount
(
RT_NULL
,
"/rom"
,
"rom"
,
0
,
&
romfs_root
)
==
0
)
{
rt_kprintf
(
"ROM File System initialized!
\n
"
);
}
else
rt_kprintf
(
"ROM File System initialzation failed!
\n
"
);
if
(
dfs_mount
(
RT_NULL
,
"/rom"
,
"rom"
,
0
,
&
romfs_root
)
==
0
)
{
rt_kprintf
(
"ROM File System initialized!
\n
"
);
}
else
rt_kprintf
(
"ROM File System initialzation failed!
\n
"
);
#endif
#if defined(RT_USING_DFS_UFFS)
{
/* mount flash device as flash directory */
if
(
dfs_mount
(
"nand0"
,
"/nand0"
,
"uffs"
,
0
,
0
)
==
0
)
rt_kprintf
(
"UFFS File System initialized!
\n
"
);
else
rt_kprintf
(
"UFFS File System initialzation failed!
\n
"
);
}
{
/* mount flash device as flash directory */
if
(
dfs_mount
(
"nand0"
,
"/nand0"
,
"uffs"
,
0
,
0
)
==
0
)
rt_kprintf
(
"UFFS File System initialized!
\n
"
);
else
rt_kprintf
(
"UFFS File System initialzation failed!
\n
"
);
}
#endif
#ifdef RT_USING_SDIO
timeout
=
0
;
while
((
rt_device_find
(
"sd0"
)
==
RT_NULL
)
&&
(
timeout
++
<
RT_TICK_PER_SECOND
*
2
))
{
rt_thread_delay
(
1
);
}
if
(
timeout
<
RT_TICK_PER_SECOND
*
2
)
{
/* mount sd card fat partition 1 as root directory */
if
(
dfs_mount
(
"sd0"
,
"/"
,
"elm"
,
0
,
0
)
==
0
)
{
rt_kprintf
(
"File System initialized!
\n
"
);
}
else
rt_kprintf
(
"File System initialzation failed!%d
\n
"
,
rt_get_errno
());
}
else
{
rt_kprintf
(
"No SD card found.
\n
"
);
}
timeout
=
0
;
while
((
rt_device_find
(
"sd0"
)
==
RT_NULL
)
&&
(
timeout
++
<
RT_TICK_PER_SECOND
*
2
))
{
rt_thread_delay
(
1
);
}
if
(
timeout
<
RT_TICK_PER_SECOND
*
2
)
{
/* mount sd card fat partition 1 as root directory */
if
(
dfs_mount
(
"sd0"
,
"/"
,
"elm"
,
0
,
0
)
==
0
)
{
rt_kprintf
(
"File System initialized!
\n
"
);
}
else
rt_kprintf
(
"File System initialzation failed!%d
\n
"
,
rt_get_errno
());
}
else
{
rt_kprintf
(
"No SD card found.
\n
"
);
}
#endif
}
}
#endif
#ifdef RT_USING_LED
rt_led_app_init
();
rt_led_app_init
();
#endif
}
#ifdef RT_USING_LED
void
rt_led_thread_entry
(
void
*
parameter
)
{
rt_uint8_t
cnt
=
0
;
led_init
();
while
(
1
)
{
/* light on leds for one second */
rt_thread_delay
(
40
);
cnt
++
;
if
(
cnt
&
0x01
)
led_on
(
1
);
else
led_off
(
1
);
if
(
cnt
&
0x02
)
led_on
(
2
);
else
led_off
(
2
);
if
(
cnt
&
0x04
)
led_on
(
3
);
else
led_off
(
3
);
}
rt_uint8_t
cnt
=
0
;
led_init
();
while
(
1
)
{
/* light on leds for one second */
rt_thread_delay
(
40
);
cnt
++
;
if
(
cnt
&
0x01
)
led_on
(
1
);
else
led_off
(
1
);
if
(
cnt
&
0x02
)
led_on
(
2
);
else
led_off
(
2
);
if
(
cnt
&
0x04
)
led_on
(
3
);
else
led_off
(
3
);
}
}
#endif
static
int
rt_led_app_init
(
void
)
{
#ifdef RT_USING_LED
rt_thread_t
led_thread
;
rt_thread_t
led_thread
;
#if (RT_THREAD_PRIORITY_MAX == 32)
led_thread
=
rt_thread_create
(
"led"
,
rt_led_thread_entry
,
RT_NULL
,
512
,
20
,
20
);
led_thread
=
rt_thread_create
(
"led"
,
rt_led_thread_entry
,
RT_NULL
,
512
,
20
,
20
);
#else
led_thread
=
rt_thread_create
(
"led"
,
rt_led_thread_entry
,
RT_NULL
,
512
,
200
,
20
);
led_thread
=
rt_thread_create
(
"led"
,
rt_led_thread_entry
,
RT_NULL
,
512
,
200
,
20
);
#endif
if
(
led_thread
!=
RT_NULL
)
rt_thread_startup
(
led_thread
);
if
(
led_thread
!=
RT_NULL
)
rt_thread_startup
(
led_thread
);
#endif
return
0
;
return
0
;
}
/* NFSv3 Initialization */
...
...
@@ -155,14 +141,14 @@ static int rt_led_app_init(void)
#include <dfs_nfs.h>
void
nfs_start
(
void
)
{
nfs_init
();
if
(
dfs_mount
(
RT_NULL
,
"/nfs"
,
"nfs"
,
0
,
RT_NFS_HOST_EXPORT
)
==
0
)
{
rt_kprintf
(
"NFSv3 File System initialized!
\n
"
);
}
else
rt_kprintf
(
"NFSv3 File System initialzation failed!
\n
"
);
nfs_init
();
if
(
dfs_mount
(
RT_NULL
,
"/nfs"
,
"nfs"
,
0
,
RT_NFS_HOST_EXPORT
)
==
0
)
{
rt_kprintf
(
"NFSv3 File System initialized!
\n
"
);
}
else
rt_kprintf
(
"NFSv3 File System initialzation failed!
\n
"
);
}
#include "finsh.h"
...
...
bsp/at91sam9260/drivers/at91_i2c_gpio.c
浏览文件 @
75e4c9dd
/*
* File : at91_i2c_gpio.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author
Notes
* 2012-04-25 weety
first version
* Date Author
Notes
* 2012-04-25 weety
first version
*/
#include <rtdevice.h>
...
...
@@ -29,101 +15,101 @@
static
void
at91_i2c_gpio_init
()
{
at91_sys_write
(
AT91_PMC_PCER
,
1
<<
AT91SAM9260_ID_PIOA
);
//enable PIOA clock
at91_sys_write
(
AT91_PIOA
+
PIO_PUER
,
(
1
<<
23
));
at91_sys_write
(
AT91_PIOA
+
PIO_PER
,
(
1
<<
23
));
at91_sys_write
(
AT91_PIOA
+
PIO_MDER
,
(
1
<<
23
));
at91_sys_write
(
AT91_PIOA
+
PIO_PUER
,
(
1
<<
24
));
at91_sys_write
(
AT91_PIOA
+
PIO_PER
,
(
1
<<
24
));
at91_sys_write
(
AT91_PIOA
+
PIO_MDER
,
(
1
<<
24
));
at91_sys_write
(
AT91_PIOA
+
PIO_OER
,
(
1
<<
23
));
at91_sys_write
(
AT91_PIOA
+
PIO_OER
,
(
1
<<
24
));
at91_sys_write
(
AT91_PIOA
+
PIO_SODR
,
(
1
<<
23
));
at91_sys_write
(
AT91_PIOA
+
PIO_SODR
,
(
1
<<
24
));
at91_sys_write
(
AT91_PMC_PCER
,
1
<<
AT91SAM9260_ID_PIOA
);
//enable PIOA clock
at91_sys_write
(
AT91_PIOA
+
PIO_PUER
,
(
1
<<
23
));
at91_sys_write
(
AT91_PIOA
+
PIO_PER
,
(
1
<<
23
));
at91_sys_write
(
AT91_PIOA
+
PIO_MDER
,
(
1
<<
23
));
at91_sys_write
(
AT91_PIOA
+
PIO_PUER
,
(
1
<<
24
));
at91_sys_write
(
AT91_PIOA
+
PIO_PER
,
(
1
<<
24
));
at91_sys_write
(
AT91_PIOA
+
PIO_MDER
,
(
1
<<
24
));
at91_sys_write
(
AT91_PIOA
+
PIO_OER
,
(
1
<<
23
));
at91_sys_write
(
AT91_PIOA
+
PIO_OER
,
(
1
<<
24
));
at91_sys_write
(
AT91_PIOA
+
PIO_SODR
,
(
1
<<
23
));
at91_sys_write
(
AT91_PIOA
+
PIO_SODR
,
(
1
<<
24
));
}
static
void
at91_set_sda
(
void
*
data
,
rt_int32_t
state
)
{
if
(
state
)
{
at91_sys_write
(
AT91_PIOA
+
PIO_SODR
,
(
1
<<
23
));
}
else
{
at91_sys_write
(
AT91_PIOA
+
PIO_CODR
,
(
1
<<
23
));
}
if
(
state
)
{
at91_sys_write
(
AT91_PIOA
+
PIO_SODR
,
(
1
<<
23
));
}
else
{
at91_sys_write
(
AT91_PIOA
+
PIO_CODR
,
(
1
<<
23
));
}
}
static
void
at91_set_scl
(
void
*
data
,
rt_int32_t
state
)
{
if
(
state
)
{
at91_sys_write
(
AT91_PIOA
+
PIO_SODR
,
(
1
<<
24
));
}
else
{
at91_sys_write
(
AT91_PIOA
+
PIO_CODR
,
(
1
<<
24
));
}
if
(
state
)
{
at91_sys_write
(
AT91_PIOA
+
PIO_SODR
,
(
1
<<
24
));
}
else
{
at91_sys_write
(
AT91_PIOA
+
PIO_CODR
,
(
1
<<
24
));
}
}
static
rt_int32_t
at91_get_sda
(
void
*
data
)
{
return
at91_sys_read
(
AT91_PIOA
+
PIO_PDSR
)
&
(
1
<<
23
);
return
at91_sys_read
(
AT91_PIOA
+
PIO_PDSR
)
&
(
1
<<
23
);
}
static
rt_int32_t
at91_get_scl
(
void
*
data
)
{
return
at91_sys_read
(
AT91_PIOA
+
PIO_PDSR
)
&
(
1
<<
24
);
return
at91_sys_read
(
AT91_PIOA
+
PIO_PDSR
)
&
(
1
<<
24
);
}
static
void
at91_udelay
(
rt_uint32_t
us
)
{
rt_int32_t
i
;
for
(;
us
>
0
;
us
--
)
{
i
=
50000
;
while
(
i
>
0
)
{
i
--
;
}
}
rt_int32_t
i
;
for
(;
us
>
0
;
us
--
)
{
i
=
50000
;
while
(
i
>
0
)
{
i
--
;
}
}
}
static
const
struct
rt_i2c_bit_ops
bit_ops
=
{
RT_NULL
,
at91_set_sda
,
at91_set_scl
,
at91_get_sda
,
at91_get_scl
,
at91_udelay
,
5
,
100
RT_NULL
,
at91_set_sda
,
at91_set_scl
,
at91_get_sda
,
at91_get_scl
,
at91_udelay
,
5
,
100
};
int
at91_i2c_init
(
void
)
{
struct
rt_i2c_bus_device
*
bus
;
struct
rt_i2c_bus_device
*
bus
;
bus
=
rt_malloc
(
sizeof
(
struct
rt_i2c_bus_device
));
if
(
bus
==
RT_NULL
)
{
rt_kprintf
(
"rt_malloc failed
\n
"
);
return
-
RT_ENOMEM
;
}
bus
=
rt_malloc
(
sizeof
(
struct
rt_i2c_bus_device
));
if
(
bus
==
RT_NULL
)
{
rt_kprintf
(
"rt_malloc failed
\n
"
);
return
-
RT_ENOMEM
;
}
rt_memset
((
void
*
)
bus
,
0
,
sizeof
(
struct
rt_i2c_bus_device
));
rt_memset
((
void
*
)
bus
,
0
,
sizeof
(
struct
rt_i2c_bus_device
));
bus
->
priv
=
(
void
*
)
&
bit_ops
;
bus
->
priv
=
(
void
*
)
&
bit_ops
;
at91_i2c_gpio_init
();
at91_i2c_gpio_init
();
rt_i2c_bit_add_bus
(
bus
,
"i2c0"
);
rt_i2c_bit_add_bus
(
bus
,
"i2c0"
);
return
0
;
return
0
;
}
INIT_DEVICE_EXPORT
(
at91_i2c_init
);
...
...
bsp/at91sam9260/drivers/at91_mci.c
浏览文件 @
75e4c9dd
此差异已折叠。
点击以展开。
bsp/at91sam9260/drivers/at91_mci.h
浏览文件 @
75e4c9dd
/*
* File : at91_mci.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
@@ -25,99 +11,99 @@
#ifndef __AT91_MCI_H__
#define __AT91_MCI_H__
#define AT91_MCI_CR
0x00
/* Control Register */
#define
AT91_MCI_MCIEN (1 << 0)
/* Multi-Media Interface Enable */
#define
AT91_MCI_MCIDIS (1 << 1)
/* Multi-Media Interface Disable */
#define
AT91_MCI_PWSEN (1 << 2)
/* Power Save Mode Enable */
#define
AT91_MCI_PWSDIS (1 << 3)
/* Power Save Mode Disable */
#define
AT91_MCI_SWRST (1 << 7)
/* Software Reset */
#define AT91_MCI_CR
0x00
/* Control Register */
#define
AT91_MCI_MCIEN (1 << 0)
/* Multi-Media Interface Enable */
#define
AT91_MCI_MCIDIS (1 << 1)
/* Multi-Media Interface Disable */
#define
AT91_MCI_PWSEN (1 << 2)
/* Power Save Mode Enable */
#define
AT91_MCI_PWSDIS (1 << 3)
/* Power Save Mode Disable */
#define
AT91_MCI_SWRST (1 << 7)
/* Software Reset */
#define AT91_MCI_MR
0x04
/* Mode Register */
#define
AT91_MCI_CLKDIV (0xff << 0)
/* Clock Divider */
#define
AT91_MCI_PWSDIV (7 << 8)
/* Power Saving Divider */
#define
AT91_MCI_RDPROOF (1 << 11)
/* Read Proof Enable [SAM926[03] only] */
#define
AT91_MCI_WRPROOF (1 << 12)
/* Write Proof Enable [SAM926[03] only] */
#define
AT91_MCI_PDCFBYTE (1 << 13)
/* PDC Force Byte Transfer [SAM926[03] only] */
#define
AT91_MCI_PDCPADV (1 << 14)
/* PDC Padding Value */
#define
AT91_MCI_PDCMODE (1 << 15)
/* PDC-orientated Mode */
#define
AT91_MCI_BLKLEN (0xfff << 18)
/* Data Block Length */
#define AT91_MCI_MR
0x04
/* Mode Register */
#define
AT91_MCI_CLKDIV (0xff << 0)
/* Clock Divider */
#define
AT91_MCI_PWSDIV (7 << 8)
/* Power Saving Divider */
#define
AT91_MCI_RDPROOF (1 << 11)
/* Read Proof Enable [SAM926[03] only] */
#define
AT91_MCI_WRPROOF (1 << 12)
/* Write Proof Enable [SAM926[03] only] */
#define
AT91_MCI_PDCFBYTE (1 << 13)
/* PDC Force Byte Transfer [SAM926[03] only] */
#define
AT91_MCI_PDCPADV (1 << 14)
/* PDC Padding Value */
#define
AT91_MCI_PDCMODE (1 << 15)
/* PDC-orientated Mode */
#define
AT91_MCI_BLKLEN (0xfff << 18)
/* Data Block Length */
#define AT91_MCI_DTOR
0x08
/* Data Timeout Register */
#define
AT91_MCI_DTOCYC (0xf << 0)
/* Data Timeout Cycle Number */
#define
AT91_MCI_DTOMUL (7 << 4)
/* Data Timeout Multiplier */
#define
AT91_MCI_DTOMUL_1
(0 << 4)
#define
AT91_MCI_DTOMUL_16
(1 << 4)
#define
AT91_MCI_DTOMUL_128
(2 << 4)
#define
AT91_MCI_DTOMUL_256
(3 << 4)
#define
AT91_MCI_DTOMUL_1K
(4 << 4)
#define
AT91_MCI_DTOMUL_4K
(5 << 4)
#define
AT91_MCI_DTOMUL_64K
(6 << 4)
#define
AT91_MCI_DTOMUL_1M
(7 << 4)
#define AT91_MCI_DTOR
0x08
/* Data Timeout Register */
#define
AT91_MCI_DTOCYC (0xf << 0)
/* Data Timeout Cycle Number */
#define
AT91_MCI_DTOMUL (7 << 4)
/* Data Timeout Multiplier */
#define
AT91_MCI_DTOMUL_1
(0 << 4)
#define
AT91_MCI_DTOMUL_16
(1 << 4)
#define
AT91_MCI_DTOMUL_128
(2 << 4)
#define
AT91_MCI_DTOMUL_256
(3 << 4)
#define
AT91_MCI_DTOMUL_1K
(4 << 4)
#define
AT91_MCI_DTOMUL_4K
(5 << 4)
#define
AT91_MCI_DTOMUL_64K
(6 << 4)
#define
AT91_MCI_DTOMUL_1M
(7 << 4)
#define AT91_MCI_SDCR
0x0c
/* SD Card Register */
#define
AT91_MCI_SDCSEL (3 << 0)
/* SD Card Selector */
#define
AT91_MCI_SDCBUS (1 << 7)
/* 1-bit or 4-bit bus */
#define AT91_MCI_SDCR
0x0c
/* SD Card Register */
#define
AT91_MCI_SDCSEL (3 << 0)
/* SD Card Selector */
#define
AT91_MCI_SDCBUS (1 << 7)
/* 1-bit or 4-bit bus */
#define AT91_MCI_ARGR
0x10
/* Argument Register */
#define AT91_MCI_ARGR
0x10
/* Argument Register */
#define AT91_MCI_CMDR
0x14
/* Command Register */
#define
AT91_MCI_CMDNB (0x3f << 0)
/* Command Number */
#define
AT91_MCI_RSPTYP (3 << 6)
/* Response Type */
#define
AT91_MCI_RSPTYP_NONE
(0 << 6)
#define
AT91_MCI_RSPTYP_48
(1 << 6)
#define
AT91_MCI_RSPTYP_136
(2 << 6)
#define
AT91_MCI_SPCMD (7 << 8)
/* Special Command */
#define
AT91_MCI_SPCMD_NONE
(0 << 8)
#define
AT91_MCI_SPCMD_INIT
(1 << 8)
#define
AT91_MCI_SPCMD_SYNC
(2 << 8)
#define
AT91_MCI_SPCMD_ICMD
(4 << 8)
#define
AT91_MCI_SPCMD_IRESP
(5 << 8)
#define
AT91_MCI_OPDCMD (1 << 11)
/* Open Drain Command */
#define
AT91_MCI_MAXLAT (1 << 12)
/* Max Latency for Command to Response */
#define
AT91_MCI_TRCMD (3 << 16)
/* Transfer Command */
#define
AT91_MCI_TRCMD_NONE
(0 << 16)
#define
AT91_MCI_TRCMD_START
(1 << 16)
#define
AT91_MCI_TRCMD_STOP
(2 << 16)
#define
AT91_MCI_TRDIR (1 << 18)
/* Transfer Direction */
#define
AT91_MCI_TRTYP (3 << 19)
/* Transfer Type */
#define
AT91_MCI_TRTYP_BLOCK
(0 << 19)
#define
AT91_MCI_TRTYP_MULTIPLE
(1 << 19)
#define
AT91_MCI_TRTYP_STREAM
(2 << 19)
#define AT91_MCI_CMDR
0x14
/* Command Register */
#define
AT91_MCI_CMDNB (0x3f << 0)
/* Command Number */
#define
AT91_MCI_RSPTYP (3 << 6)
/* Response Type */
#define
AT91_MCI_RSPTYP_NONE
(0 << 6)
#define
AT91_MCI_RSPTYP_48
(1 << 6)
#define
AT91_MCI_RSPTYP_136
(2 << 6)
#define
AT91_MCI_SPCMD (7 << 8)
/* Special Command */
#define
AT91_MCI_SPCMD_NONE
(0 << 8)
#define
AT91_MCI_SPCMD_INIT
(1 << 8)
#define
AT91_MCI_SPCMD_SYNC
(2 << 8)
#define
AT91_MCI_SPCMD_ICMD
(4 << 8)
#define
AT91_MCI_SPCMD_IRESP
(5 << 8)
#define
AT91_MCI_OPDCMD (1 << 11)
/* Open Drain Command */
#define
AT91_MCI_MAXLAT (1 << 12)
/* Max Latency for Command to Response */
#define
AT91_MCI_TRCMD (3 << 16)
/* Transfer Command */
#define
AT91_MCI_TRCMD_NONE
(0 << 16)
#define
AT91_MCI_TRCMD_START
(1 << 16)
#define
AT91_MCI_TRCMD_STOP
(2 << 16)
#define
AT91_MCI_TRDIR (1 << 18)
/* Transfer Direction */
#define
AT91_MCI_TRTYP (3 << 19)
/* Transfer Type */
#define
AT91_MCI_TRTYP_BLOCK
(0 << 19)
#define
AT91_MCI_TRTYP_MULTIPLE
(1 << 19)
#define
AT91_MCI_TRTYP_STREAM
(2 << 19)
#define AT91_MCI_BLKR
0x18
/* Block Register */
#define
AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0)
/* Block count */
#define
AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16)
/* Block lenght */
#define AT91_MCI_BLKR
0x18
/* Block Register */
#define
AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0)
/* Block count */
#define
AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16)
/* Block lenght */
#define AT91_MCI_RSPR(n)
(0x20 + ((n) * 4))
/* Response Registers 0-3 */
#define AT91_MCR_RDR
0x30
/* Receive Data Register */
#define AT91_MCR_TDR
0x34
/* Transmit Data Register */
#define AT91_MCI_RSPR(n)
(0x20 + ((n) * 4))
/* Response Registers 0-3 */
#define AT91_MCR_RDR
0x30
/* Receive Data Register */
#define AT91_MCR_TDR
0x34
/* Transmit Data Register */
#define AT91_MCI_SR
0x40
/* Status Register */
#define
AT91_MCI_CMDRDY (1U << 0)
/* Command Ready */
#define
AT91_MCI_RXRDY (1U << 1)
/* Receiver Ready */
#define
AT91_MCI_TXRDY (1U << 2)
/* Transmit Ready */
#define
AT91_MCI_BLKE (1U << 3)
/* Data Block Ended */
#define
AT91_MCI_DTIP (1U << 4)
/* Data Transfer in Progress */
#define
AT91_MCI_NOTBUSY (1U << 5)
/* Data Not Busy */
#define
AT91_MCI_ENDRX (1U << 6)
/* End of RX Buffer */
#define
AT91_MCI_ENDTX (1U << 7)
/* End fo TX Buffer */
#define
AT91_MCI_SDIOIRQA (1U << 8)
/* SDIO Interrupt for Slot A */
#define
AT91_MCI_SDIOIRQB (1U << 9)
/* SDIO Interrupt for Slot B */
#define
AT91_MCI_RXBUFF (1U << 14)
/* RX Buffer Full */
#define
AT91_MCI_TXBUFE (1U << 15)
/* TX Buffer Empty */
#define
AT91_MCI_RINDE (1U << 16)
/* Response Index Error */
#define
AT91_MCI_RDIRE (1U << 17)
/* Response Direction Error */
#define
AT91_MCI_RCRCE (1U << 18)
/* Response CRC Error */
#define
AT91_MCI_RENDE (1U << 19)
/* Response End Bit Error */
#define
AT91_MCI_RTOE (1U << 20)
/* Reponse Time-out Error */
#define
AT91_MCI_DCRCE (1U << 21)
/* Data CRC Error */
#define
AT91_MCI_DTOE (1U << 22)
/* Data Time-out Error */
#define
AT91_MCI_OVRE (1U << 30)
/* Overrun */
#define
AT91_MCI_UNRE (1U << 31)
/* Underrun */
#define AT91_MCI_SR
0x40
/* Status Register */
#define
AT91_MCI_CMDRDY (1U << 0)
/* Command Ready */
#define
AT91_MCI_RXRDY (1U << 1)
/* Receiver Ready */
#define
AT91_MCI_TXRDY (1U << 2)
/* Transmit Ready */
#define
AT91_MCI_BLKE (1U << 3)
/* Data Block Ended */
#define
AT91_MCI_DTIP (1U << 4)
/* Data Transfer in Progress */
#define
AT91_MCI_NOTBUSY (1U << 5)
/* Data Not Busy */
#define
AT91_MCI_ENDRX (1U << 6)
/* End of RX Buffer */
#define
AT91_MCI_ENDTX (1U << 7)
/* End fo TX Buffer */
#define
AT91_MCI_SDIOIRQA (1U << 8)
/* SDIO Interrupt for Slot A */
#define
AT91_MCI_SDIOIRQB (1U << 9)
/* SDIO Interrupt for Slot B */
#define
AT91_MCI_RXBUFF (1U << 14)
/* RX Buffer Full */
#define
AT91_MCI_TXBUFE (1U << 15)
/* TX Buffer Empty */
#define
AT91_MCI_RINDE (1U << 16)
/* Response Index Error */
#define
AT91_MCI_RDIRE (1U << 17)
/* Response Direction Error */
#define
AT91_MCI_RCRCE (1U << 18)
/* Response CRC Error */
#define
AT91_MCI_RENDE (1U << 19)
/* Response End Bit Error */
#define
AT91_MCI_RTOE (1U << 20)
/* Reponse Time-out Error */
#define
AT91_MCI_DCRCE (1U << 21)
/* Data CRC Error */
#define
AT91_MCI_DTOE (1U << 22)
/* Data Time-out Error */
#define
AT91_MCI_OVRE (1U << 30)
/* Overrun */
#define
AT91_MCI_UNRE (1U << 31)
/* Underrun */
#define AT91_MCI_IER
0x44
/* Interrupt Enable Register */
#define AT91_MCI_IDR
0x48
/* Interrupt Disable Register */
#define AT91_MCI_IMR
0x4c
/* Interrupt Mask Register */
#define AT91_MCI_IER
0x44
/* Interrupt Enable Register */
#define AT91_MCI_IDR
0x48
/* Interrupt Disable Register */
#define AT91_MCI_IMR
0x4c
/* Interrupt Mask Register */
extern
int
at91_mci_init
(
void
);
...
...
bsp/at91sam9260/drivers/board.c
浏览文件 @
75e4c9dd
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
@@ -54,56 +40,56 @@ extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
extern
void
rt_dbgu_isr
(
void
);
static
struct
mem_desc
at91_mem_desc
[]
=
{
{
0x00000000
,
0xFFFFFFFF
,
0x00000000
,
RW_NCNB
},
/* None cached for 4G memory */
{
0x20000000
,
0x24000000
-
1
,
0x20000000
,
RW_CB
},
/* 64M cached SDRAM memory */
{
0x00000000
,
0x100000
,
0x20000000
,
RW_CB
},
/* isr vector table */
{
0x90000000
,
0x90400000
-
1
,
0x00200000
,
RW_NCNB
},
/* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */
{
0xA0000000
,
0xA4000000
-
1
,
0x20000000
,
RW_NCNB
}
/* 64M none-cached SDRAM memory */
{
0x00000000
,
0xFFFFFFFF
,
0x00000000
,
RW_NCNB
},
/* None cached for 4G memory */
{
0x20000000
,
0x24000000
-
1
,
0x20000000
,
RW_CB
},
/* 64M cached SDRAM memory */
{
0x00000000
,
0x100000
,
0x20000000
,
RW_CB
},
/* isr vector table */
{
0x90000000
,
0x90400000
-
1
,
0x00200000
,
RW_NCNB
},
/* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */
{
0xA0000000
,
0xA4000000
-
1
,
0x20000000
,
RW_NCNB
}
/* 64M none-cached SDRAM memory */
};
#define PIT_CPIV(x)
((x) & AT91_PIT_CPIV)
#define PIT_PICNT(x)
(((x) & AT91_PIT_PICNT) >> 20)
#define PIT_CPIV(x)
((x) & AT91_PIT_CPIV)
#define PIT_PICNT(x)
(((x) & AT91_PIT_PICNT) >> 20)
static
rt_uint32_t
pit_cycle
;
/* write-once */
static
rt_uint32_t
pit_cnt
;
/* access only w/system irq blocked */
static
rt_uint32_t
pit_cycle
;
/* write-once */
static
rt_uint32_t
pit_cnt
;
/* access only w/system irq blocked */
/**
* This function will handle rtos timer
*/
void
rt_timer_handler
(
int
vector
,
void
*
param
)
{
#ifdef RT_USING_DBGU
if
(
at91_sys_read
(
AT91_DBGU
+
AT91_US_CSR
)
&
0x1
)
{
rt_dbgu_isr
();
}
#endif
if
(
at91_sys_read
(
AT91_PIT_SR
)
&
AT91_PIT_PITS
)
{
unsigned
nr_ticks
;
/* Get number of ticks performed before irq, and ack it */
nr_ticks
=
PIT_PICNT
(
at91_sys_read
(
AT91_PIT_PIVR
));
rt_tick_increase
();
}
#ifdef RT_USING_DBGU
if
(
at91_sys_read
(
AT91_DBGU
+
AT91_US_CSR
)
&
0x1
)
{
rt_dbgu_isr
();
}
#endif
if
(
at91_sys_read
(
AT91_PIT_SR
)
&
AT91_PIT_PITS
)
{
unsigned
nr_ticks
;
/* Get number of ticks performed before irq, and ack it */
nr_ticks
=
PIT_PICNT
(
at91_sys_read
(
AT91_PIT_PIVR
));
rt_tick_increase
();
}
}
static
void
at91sam926x_pit_reset
(
void
)
{
/* Disable timer and irqs */
at91_sys_write
(
AT91_PIT_MR
,
0
);
/* Clear any pending interrupts, wait for PIT to stop counting */
while
(
PIT_CPIV
(
at91_sys_read
(
AT91_PIT_PIVR
))
!=
0
)
;
/* Start PIT but don't enable IRQ */
//at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
pit_cnt
+=
pit_cycle
*
PIT_PICNT
(
at91_sys_read
(
AT91_PIT_PIVR
));
at91_sys_write
(
AT91_PIT_MR
,
(
pit_cycle
-
1
)
|
AT91_PIT_PITEN
|
AT91_PIT_PITIEN
);
rt_kprintf
(
"PIT_MR=0x%08x
\n
"
,
at91_sys_read
(
AT91_PIT_MR
));
/* Disable timer and irqs */
at91_sys_write
(
AT91_PIT_MR
,
0
);
/* Clear any pending interrupts, wait for PIT to stop counting */
while
(
PIT_CPIV
(
at91_sys_read
(
AT91_PIT_PIVR
))
!=
0
)
;
/* Start PIT but don't enable IRQ */
//at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
pit_cnt
+=
pit_cycle
*
PIT_PICNT
(
at91_sys_read
(
AT91_PIT_PIVR
));
at91_sys_write
(
AT91_PIT_MR
,
(
pit_cycle
-
1
)
|
AT91_PIT_PITEN
|
AT91_PIT_PITIEN
);
rt_kprintf
(
"PIT_MR=0x%08x
\n
"
,
at91_sys_read
(
AT91_PIT_MR
));
}
/*
...
...
@@ -111,19 +97,19 @@ static void at91sam926x_pit_reset(void)
*/
static
void
at91sam926x_pit_init
(
void
)
{
rt_uint32_t
pit_rate
;
rt_uint32_t
bits
;
rt_uint32_t
pit_rate
;
rt_uint32_t
bits
;
/*
* Use our actual MCK to figure out how many MCK/16 ticks per
* 1/HZ period (instead of a compile-time constant LATCH).
*/
pit_rate
=
clk_get_rate
(
clk_get
(
"mck"
))
/
16
;
rt_kprintf
(
"pit_rate=%dHZ
\n
"
,
pit_rate
);
pit_cycle
=
(
pit_rate
+
RT_TICK_PER_SECOND
/
2
)
/
RT_TICK_PER_SECOND
;
/*
* Use our actual MCK to figure out how many MCK/16 ticks per
* 1/HZ period (instead of a compile-time constant LATCH).
*/
pit_rate
=
clk_get_rate
(
clk_get
(
"mck"
))
/
16
;
rt_kprintf
(
"pit_rate=%dHZ
\n
"
,
pit_rate
);
pit_cycle
=
(
pit_rate
+
RT_TICK_PER_SECOND
/
2
)
/
RT_TICK_PER_SECOND
;
/* Initialize and enable the timer */
at91sam926x_pit_reset
();
/* Initialize and enable the timer */
at91sam926x_pit_reset
();
}
...
...
@@ -132,69 +118,69 @@ static void at91sam926x_pit_init(void)
*/
void
rt_hw_timer_init
()
{
at91sam926x_pit_init
();
at91sam926x_pit_init
();
/* install interrupt handler */
rt_hw_interrupt_install
(
AT91_ID_SYS
,
rt_timer_handler
,
RT_NULL
,
"system"
);
rt_hw_interrupt_umask
(
AT91_ID_SYS
);
/* install interrupt handler */
rt_hw_interrupt_install
(
AT91_ID_SYS
,
rt_timer_handler
,
RT_NULL
,
"system"
);
rt_hw_interrupt_umask
(
AT91_ID_SYS
);
}
void
at91_tc1_init
()
{
at91_sys_write
(
AT91_PMC_PCER
,
1
<<
AT91SAM9260_ID_TC0
);
writel
(
AT91_TC_TC0XC0S_NONE
|
AT91_TC_TC1XC1S_NONE
|
AT91_TC_TC2XC2S_NONE
,
AT91SAM9260_BASE_TCB0
+
AT91_TC_BMR
);
writel
(
AT91_TC_CLKDIS
,
AT91SAM9260_BASE_TC0
+
AT91_TC_CCR
);
writel
(
AT91_TC_TIMER_CLOCK4
,
AT91SAM9260_BASE_TC0
+
AT91_TC_CMR
);
writel
(
0xffff
,
AT91SAM9260_BASE_TC0
+
AT91_TC_CV
);
at91_sys_write
(
AT91_PMC_PCER
,
1
<<
AT91SAM9260_ID_TC0
);
writel
(
AT91_TC_TC0XC0S_NONE
|
AT91_TC_TC1XC1S_NONE
|
AT91_TC_TC2XC2S_NONE
,
AT91SAM9260_BASE_TCB0
+
AT91_TC_BMR
);
writel
(
AT91_TC_CLKDIS
,
AT91SAM9260_BASE_TC0
+
AT91_TC_CCR
);
writel
(
AT91_TC_TIMER_CLOCK4
,
AT91SAM9260_BASE_TC0
+
AT91_TC_CMR
);
writel
(
0xffff
,
AT91SAM9260_BASE_TC0
+
AT91_TC_CV
);
}
#define RXRDY
0x01
#define TXRDY
(1 << 1)
#define BPS
115200
/* serial baudrate */
#define RXRDY
0x01
#define TXRDY
(1 << 1)
#define BPS
115200
/* serial baudrate */
typedef
struct
uartport
{
volatile
rt_uint32_t
CR
;
volatile
rt_uint32_t
MR
;
volatile
rt_uint32_t
IER
;
volatile
rt_uint32_t
IDR
;
volatile
rt_uint32_t
IMR
;
volatile
rt_uint32_t
CSR
;
volatile
rt_uint32_t
RHR
;
volatile
rt_uint32_t
THR
;
volatile
rt_uint32_t
BRGR
;
volatile
rt_uint32_t
RTOR
;
volatile
rt_uint32_t
TTGR
;
volatile
rt_uint32_t
reserved0
[
5
];
volatile
rt_uint32_t
FIDI
;
volatile
rt_uint32_t
NER
;
volatile
rt_uint32_t
reserved1
;
volatile
rt_uint32_t
IFR
;
volatile
rt_uint32_t
reserved2
[
44
];
volatile
rt_uint32_t
RPR
;
volatile
rt_uint32_t
RCR
;
volatile
rt_uint32_t
TPR
;
volatile
rt_uint32_t
TCR
;
volatile
rt_uint32_t
RNPR
;
volatile
rt_uint32_t
RNCR
;
volatile
rt_uint32_t
TNPR
;
volatile
rt_uint32_t
TNCR
;
volatile
rt_uint32_t
PTCR
;
volatile
rt_uint32_t
PTSR
;
volatile
rt_uint32_t
CR
;
volatile
rt_uint32_t
MR
;
volatile
rt_uint32_t
IER
;
volatile
rt_uint32_t
IDR
;
volatile
rt_uint32_t
IMR
;
volatile
rt_uint32_t
CSR
;
volatile
rt_uint32_t
RHR
;
volatile
rt_uint32_t
THR
;
volatile
rt_uint32_t
BRGR
;
volatile
rt_uint32_t
RTOR
;
volatile
rt_uint32_t
TTGR
;
volatile
rt_uint32_t
reserved0
[
5
];
volatile
rt_uint32_t
FIDI
;
volatile
rt_uint32_t
NER
;
volatile
rt_uint32_t
reserved1
;
volatile
rt_uint32_t
IFR
;
volatile
rt_uint32_t
reserved2
[
44
];
volatile
rt_uint32_t
RPR
;
volatile
rt_uint32_t
RCR
;
volatile
rt_uint32_t
TPR
;
volatile
rt_uint32_t
TCR
;
volatile
rt_uint32_t
RNPR
;
volatile
rt_uint32_t
RNCR
;
volatile
rt_uint32_t
TNPR
;
volatile
rt_uint32_t
TNCR
;
volatile
rt_uint32_t
PTCR
;
volatile
rt_uint32_t
PTSR
;
}
uartport
;
#define CIDR FIDI
#define EXID NER
#define FNR reserved1
#define DBGU
((struct uartport *)AT91SAM9260_BASE_DBGU)
#define DBGU
((struct uartport *)AT91SAM9260_BASE_DBGU)
static
void
at91_usart_putc
(
char
c
)
{
while
(
!
(
DBGU
->
CSR
&
TXRDY
));
DBGU
->
THR
=
c
;
DBGU
->
THR
=
c
;
}
/**
...
...
@@ -205,33 +191,33 @@ static void at91_usart_putc(char c)
*/
void
rt_hw_console_output
(
const
char
*
str
)
{
while
(
*
str
)
{
if
(
*
str
==
'\n'
)
{
at91_usart_putc
(
'\r'
);
}
at91_usart_putc
(
*
str
++
);
}
while
(
*
str
)
{
if
(
*
str
==
'\n'
)
{
at91_usart_putc
(
'\r'
);
}
at91_usart_putc
(
*
str
++
);
}
}
static
void
rt_hw_console_init
(
void
)
{
int
div
;
int
mode
=
0
;
DBGU
->
CR
=
AT91_US_RSTTX
|
AT91_US_RSTRX
|
AT91_US_RXDIS
|
AT91_US_TXDIS
;
mode
|=
AT91_US_USMODE_NORMAL
|
AT91_US_USCLKS_MCK
|
AT91_US_CHMODE_NORMAL
;
mode
|=
AT91_US_CHRL_8
;
mode
|=
AT91_US_NBSTOP_1
;
mode
|=
AT91_US_PAR_NONE
;
DBGU
->
MR
=
mode
;
div
=
(
clk_get_rate
(
clk_get
(
"mck"
))
/
16
+
BPS
/
2
)
/
BPS
;
DBGU
->
BRGR
=
div
;
DBGU
->
CR
=
AT91_US_RXEN
|
AT91_US_TXEN
;
int
div
;
int
mode
=
0
;
DBGU
->
CR
=
AT91_US_RSTTX
|
AT91_US_RSTRX
|
AT91_US_RXDIS
|
AT91_US_TXDIS
;
mode
|=
AT91_US_USMODE_NORMAL
|
AT91_US_USCLKS_MCK
|
AT91_US_CHMODE_NORMAL
;
mode
|=
AT91_US_CHRL_8
;
mode
|=
AT91_US_NBSTOP_1
;
mode
|=
AT91_US_PAR_NONE
;
DBGU
->
MR
=
mode
;
div
=
(
clk_get_rate
(
clk_get
(
"mck"
))
/
16
+
BPS
/
2
)
/
BPS
;
DBGU
->
BRGR
=
div
;
DBGU
->
CR
=
AT91_US_RXEN
|
AT91_US_TXEN
;
}
...
...
@@ -240,31 +226,31 @@ static void rt_hw_console_init(void)
*/
void
rt_hw_board_init
()
{
/* initialize the system clock */
rt_hw_clock_init
();
/* initialize the system clock */
rt_hw_clock_init
();
/* initialize console */
rt_hw_console_init
();
/* initialize console */
rt_hw_console_init
();
/* initialize mmu */
rt_hw_mmu_init
(
at91_mem_desc
,
sizeof
(
at91_mem_desc
)
/
sizeof
(
at91_mem_desc
[
0
]));
/* initialize mmu */
rt_hw_mmu_init
(
at91_mem_desc
,
sizeof
(
at91_mem_desc
)
/
sizeof
(
at91_mem_desc
[
0
]));
/* initialize hardware interrupt */
rt_hw_interrupt_init
();
/* initialize hardware interrupt */
rt_hw_interrupt_init
();
/* initialize early device */
/* initialize early device */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init
();
rt_components_board_init
();
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device
(
RT_CONSOLE_DEVICE_NAME
);
rt_console_set_device
(
RT_CONSOLE_DEVICE_NAME
);
#endif
/* initialize timer0 */
rt_hw_timer_init
();
/* initialize timer0 */
rt_hw_timer_init
();
/* initialize board */
#ifdef RT_USING_HEAP
rt_system_heap_init
((
void
*
)
HEAP_BEGIN
,
(
void
*
)
HEAP_END
);
rt_system_heap_init
((
void
*
)
HEAP_BEGIN
,
(
void
*
)
HEAP_END
);
#endif
}
...
...
bsp/at91sam9260/drivers/board.h
浏览文件 @
75e4c9dd
/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
bsp/at91sam9260/drivers/led.c
浏览文件 @
75e4c9dd
/*
* File : led.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
@@ -28,59 +14,59 @@
#if 1
// GB9260 board
#define PIO_LED
AT91_PIOB
#define LED1
(1 << 25)
// LED_SYS
#define LED2
(0)
#define LED3
(1 << 23)
// LED_USR
#define LED_ALL
(LED1 | LED2 | LED3)
#define PIO_LED
AT91_PIOB
#define LED1
(1 << 25)
// LED_SYS
#define LED2
(0)
#define LED3
(1 << 23)
// LED_USR
#define LED_ALL
(LED1 | LED2 | LED3)
#else
#define PIO_LED
AT91_PIOC
#define LED1
(1 << 8)
#define LED2
(1 << 11)
#define LED3
(1 << 6)
#define LED_ALL
(LED1 | LED2 | LED3)
#define PIO_LED
AT91_PIOC
#define LED1
(1 << 8)
#define LED2
(1 << 11)
#define LED3
(1 << 6)
#define LED_ALL
(LED1 | LED2 | LED3)
#endif
void
led_init
(
void
)
{
at91_sys_write
(
PIO_LED
+
0x00
,
LED_ALL
);
at91_sys_write
(
PIO_LED
+
0x10
,
LED_ALL
);
at91_sys_write
(
PIO_LED
+
0x64
,
LED_ALL
);
at91_sys_write
(
PIO_LED
+
0x30
,
LED_ALL
);
at91_sys_write
(
PIO_LED
+
0x00
,
LED_ALL
);
at91_sys_write
(
PIO_LED
+
0x10
,
LED_ALL
);
at91_sys_write
(
PIO_LED
+
0x64
,
LED_ALL
);
at91_sys_write
(
PIO_LED
+
0x30
,
LED_ALL
);
}
void
led_on
(
int
num
)
{
switch
(
num
)
{
case
1
:
at91_sys_write
(
PIO_LED
+
0x34
,
LED1
);
break
;
case
2
:
at91_sys_write
(
PIO_LED
+
0x34
,
LED2
);
break
;
case
3
:
at91_sys_write
(
PIO_LED
+
0x34
,
LED3
);
break
;
default:
break
;
}
switch
(
num
)
{
case
1
:
at91_sys_write
(
PIO_LED
+
0x34
,
LED1
);
break
;
case
2
:
at91_sys_write
(
PIO_LED
+
0x34
,
LED2
);
break
;
case
3
:
at91_sys_write
(
PIO_LED
+
0x34
,
LED3
);
break
;
default:
break
;
}
}
void
led_off
(
int
num
)
{
switch
(
num
)
{
case
1
:
at91_sys_write
(
PIO_LED
+
0x30
,
LED1
);
break
;
case
2
:
at91_sys_write
(
PIO_LED
+
0x30
,
LED2
);
break
;
case
3
:
at91_sys_write
(
PIO_LED
+
0x30
,
LED3
);
break
;
default:
break
;
}
switch
(
num
)
{
case
1
:
at91_sys_write
(
PIO_LED
+
0x30
,
LED1
);
break
;
case
2
:
at91_sys_write
(
PIO_LED
+
0x30
,
LED2
);
break
;
case
3
:
at91_sys_write
(
PIO_LED
+
0x30
,
LED3
);
break
;
default:
break
;
}
}
bsp/at91sam9260/drivers/led.h
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/*
* File : led.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
bsp/at91sam9260/drivers/macb.c
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bsp/at91sam9260/drivers/macb.h
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bsp/at91sam9260/drivers/mii.h
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/*
* File : mii.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
@@ -36,7 +22,7 @@
#define MII_EXPANSION 0x06
/* Expansion register */
#define MII_CTRL1000 0x09
/* 1000BASE-T control */
#define MII_STAT1000 0x0a
/* 1000BASE-T status */
#define MII_ESTATUS
0x0f
/* Extended Status */
#define MII_ESTATUS
0x0f
/* Extended Status */
#define MII_DCOUNTER 0x12
/* Disconnect counter */
#define MII_FCSCOUNTER 0x13
/* False carrier counter */
#define MII_NWAYTEST 0x14
/* N-way auto-neg test reg */
...
...
@@ -51,7 +37,7 @@
/* Basic mode control register. */
#define BMCR_RESV 0x003f
/* Unused... */
#define BMCR_SPEED1000
0x0040
/* MSB of Speed (1000) */
#define BMCR_SPEED1000
0x0040
/* MSB of Speed (1000) */
#define BMCR_CTST 0x0080
/* Collision test */
#define BMCR_FULLDPLX 0x0100
/* Full duplex */
#define BMCR_ANRESTART 0x0200
/* Auto negotiation restart */
...
...
@@ -70,7 +56,7 @@
#define BMSR_RFAULT 0x0010
/* Remote fault detected */
#define BMSR_ANEGCOMPLETE 0x0020
/* Auto-negotiation complete */
#define BMSR_RESV 0x00c0
/* Unused... */
#define BMSR_ESTATEN
0x0100
/* Extended Status in R15 */
#define BMSR_ESTATEN
0x0100
/* Extended Status in R15 */
#define BMSR_100HALF2 0x0200
/* Can do 100BASE-T2 HDX */
#define BMSR_100FULL2 0x0400
/* Can do 100BASE-T2 FDX */
#define BMSR_10HALF 0x0800
/* Can do 10mbps, half-duplex */
...
...
@@ -99,7 +85,7 @@
#define ADVERTISE_NPAGE 0x8000
/* Next page bit */
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
ADVERTISE_CSMA)
ADVERTISE_CSMA)
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
ADVERTISE_100HALF | ADVERTISE_100FULL)
...
...
@@ -121,8 +107,8 @@
#define LPA_LPACK 0x4000
/* Link partner acked us */
#define LPA_NPAGE 0x8000
/* Next page bit */
#define LPA_DUPLEX
(LPA_10FULL | LPA_100FULL)
#define LPA_100
(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
#define LPA_DUPLEX
(LPA_10FULL | LPA_100FULL)
#define LPA_100
(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
/* Expansion register for auto-negotiation. */
#define EXPANSION_NWAY 0x0001
/* Can do N-way auto-nego */
...
...
@@ -132,8 +118,8 @@
#define EXPANSION_MFAULTS 0x0010
/* Multiple faults detected */
#define EXPANSION_RESV 0xffe0
/* Unused... */
#define ESTATUS_1000_TFULL
0x2000
/* Can do 1000BT Full */
#define ESTATUS_1000_THALF
0x1000
/* Can do 1000BT Half */
#define ESTATUS_1000_TFULL
0x2000
/* Can do 1000BT Full */
#define ESTATUS_1000_THALF
0x1000
/* Can do 1000BT Half */
/* N-way test register. */
#define NWAYTEST_RESV1 0x00ff
/* Unused... */
...
...
@@ -151,8 +137,8 @@
#define LPA_1000HALF 0x0400
/* Link partner 1000BASE-T half duplex */
/* Flow control flags */
#define FLOW_CTRL_TX
0x01
#define FLOW_CTRL_RX
0x02
#define FLOW_CTRL_TX
0x01
#define FLOW_CTRL_RX
0x02
/**
* mii_nway_result
...
...
bsp/at91sam9260/drivers/usart.c
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bsp/at91sam9260/platform/at91_aic.h
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/*
* File : at91_aic.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
@@ -29,41 +15,41 @@
extern
"C"
{
#endif
#define AIC_IRQS
32
#define AT91_AIC_SMR(n)
(AT91_AIC + ((n) * 4))
/* Source Mode Registers 0-31 */
#define
AT91_AIC_PRIOR (7 << 0)
/* Priority Level */
#define
AT91_AIC_SRCTYPE (3 << 5)
/* Interrupt Source Type */
#define
AT91_AIC_SRCTYPE_LOW
(0 << 5)
#define
AT91_AIC_SRCTYPE_FALLING
(1 << 5)
#define
AT91_AIC_SRCTYPE_HIGH
(2 << 5)
#define
AT91_AIC_SRCTYPE_RISING
(3 << 5)
#define AT91_AIC_SVR(n)
(AT91_AIC + 0x80 + ((n) * 4))
/* Source Vector Registers 0-31 */
#define AT91_AIC_IVR
(AT91_AIC + 0x100)
/* Interrupt Vector Register */
#define AT91_AIC_FVR
(AT91_AIC + 0x104)
/* Fast Interrupt Vector Register */
#define AT91_AIC_ISR
(AT91_AIC + 0x108)
/* Interrupt Status Register */
#define
AT91_AIC_IRQID (0x1f << 0)
/* Current Interrupt Identifier */
#define AT91_AIC_IPR
(AT91_AIC + 0x10c)
/* Interrupt Pending Register */
#define AT91_AIC_IMR
(AT91_AIC + 0x110)
/* Interrupt Mask Register */
#define AT91_AIC_CISR
(AT91_AIC + 0x114)
/* Core Interrupt Status Register */
#define
AT91_AIC_NFIQ (1 << 0)
/* nFIQ Status */
#define
AT91_AIC_NIRQ (1 << 1)
/* nIRQ Status */
#define AT91_AIC_IECR
(AT91_AIC + 0x120)
/* Interrupt Enable Command Register */
#define AT91_AIC_IDCR
(AT91_AIC + 0x124)
/* Interrupt Disable Command Register */
#define AT91_AIC_ICCR
(AT91_AIC + 0x128)
/* Interrupt Clear Command Register */
#define AT91_AIC_ISCR
(AT91_AIC + 0x12c)
/* Interrupt Set Command Register */
#define AT91_AIC_EOICR
(AT91_AIC + 0x130)
/* End of Interrupt Command Register */
#define AT91_AIC_SPU
(AT91_AIC + 0x134)
/* Spurious Interrupt Vector Register */
#define AT91_AIC_DCR
(AT91_AIC + 0x138)
/* Debug Control Register */
#define
AT91_AIC_DCR_PROT (1 << 0)
/* Protection Mode */
#define
AT91_AIC_DCR_GMSK (1 << 1)
/* General Mask */
#define AT91_AIC_FFER
(AT91_AIC + 0x140)
/* Fast Forcing Enable Register [SAM9 only] */
#define AT91_AIC_FFDR
(AT91_AIC + 0x144)
/* Fast Forcing Disable Register [SAM9 only] */
#define AT91_AIC_FFSR
(AT91_AIC + 0x148)
/* Fast Forcing Status Register [SAM9 only] */
#define AIC_IRQS
32
#define AT91_AIC_SMR(n)
(AT91_AIC + ((n) * 4))
/* Source Mode Registers 0-31 */
#define
AT91_AIC_PRIOR (7 << 0)
/* Priority Level */
#define
AT91_AIC_SRCTYPE (3 << 5)
/* Interrupt Source Type */
#define
AT91_AIC_SRCTYPE_LOW
(0 << 5)
#define
AT91_AIC_SRCTYPE_FALLING
(1 << 5)
#define
AT91_AIC_SRCTYPE_HIGH
(2 << 5)
#define
AT91_AIC_SRCTYPE_RISING
(3 << 5)
#define AT91_AIC_SVR(n)
(AT91_AIC + 0x80 + ((n) * 4))
/* Source Vector Registers 0-31 */
#define AT91_AIC_IVR
(AT91_AIC + 0x100)
/* Interrupt Vector Register */
#define AT91_AIC_FVR
(AT91_AIC + 0x104)
/* Fast Interrupt Vector Register */
#define AT91_AIC_ISR
(AT91_AIC + 0x108)
/* Interrupt Status Register */
#define
AT91_AIC_IRQID (0x1f << 0)
/* Current Interrupt Identifier */
#define AT91_AIC_IPR
(AT91_AIC + 0x10c)
/* Interrupt Pending Register */
#define AT91_AIC_IMR
(AT91_AIC + 0x110)
/* Interrupt Mask Register */
#define AT91_AIC_CISR
(AT91_AIC + 0x114)
/* Core Interrupt Status Register */
#define
AT91_AIC_NFIQ (1 << 0)
/* nFIQ Status */
#define
AT91_AIC_NIRQ (1 << 1)
/* nIRQ Status */
#define AT91_AIC_IECR
(AT91_AIC + 0x120)
/* Interrupt Enable Command Register */
#define AT91_AIC_IDCR
(AT91_AIC + 0x124)
/* Interrupt Disable Command Register */
#define AT91_AIC_ICCR
(AT91_AIC + 0x128)
/* Interrupt Clear Command Register */
#define AT91_AIC_ISCR
(AT91_AIC + 0x12c)
/* Interrupt Set Command Register */
#define AT91_AIC_EOICR
(AT91_AIC + 0x130)
/* End of Interrupt Command Register */
#define AT91_AIC_SPU
(AT91_AIC + 0x134)
/* Spurious Interrupt Vector Register */
#define AT91_AIC_DCR
(AT91_AIC + 0x138)
/* Debug Control Register */
#define
AT91_AIC_DCR_PROT (1 << 0)
/* Protection Mode */
#define
AT91_AIC_DCR_GMSK (1 << 1)
/* General Mask */
#define AT91_AIC_FFER
(AT91_AIC + 0x140)
/* Fast Forcing Enable Register [SAM9 only] */
#define AT91_AIC_FFDR
(AT91_AIC + 0x144)
/* Fast Forcing Disable Register [SAM9 only] */
#define AT91_AIC_FFSR
(AT91_AIC + 0x148)
/* Fast Forcing Status Register [SAM9 only] */
#ifdef __cplusplus
}
...
...
bsp/at91sam9260/platform/at91_pdc.h
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/*
* File : at91_pdc.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
@@ -25,21 +11,21 @@
#ifndef __AT91_PDC_H__
#define __AT91_PDC_H__
#define AT91_PDC_RPR
0x100
/* Receive Pointer Register */
#define AT91_PDC_RCR
0x104
/* Receive Counter Register */
#define AT91_PDC_TPR
0x108
/* Transmit Pointer Register */
#define AT91_PDC_TCR
0x10c
/* Transmit Counter Register */
#define AT91_PDC_RNPR
0x110
/* Receive Next Pointer Register */
#define AT91_PDC_RNCR
0x114
/* Receive Next Counter Register */
#define AT91_PDC_TNPR
0x118
/* Transmit Next Pointer Register */
#define AT91_PDC_TNCR
0x11c
/* Transmit Next Counter Register */
#define AT91_PDC_RPR
0x100
/* Receive Pointer Register */
#define AT91_PDC_RCR
0x104
/* Receive Counter Register */
#define AT91_PDC_TPR
0x108
/* Transmit Pointer Register */
#define AT91_PDC_TCR
0x10c
/* Transmit Counter Register */
#define AT91_PDC_RNPR
0x110
/* Receive Next Pointer Register */
#define AT91_PDC_RNCR
0x114
/* Receive Next Counter Register */
#define AT91_PDC_TNPR
0x118
/* Transmit Next Pointer Register */
#define AT91_PDC_TNCR
0x11c
/* Transmit Next Counter Register */
#define AT91_PDC_PTCR
0x120
/* Transfer Control Register */
#define
AT91_PDC_RXTEN (1 << 0)
/* Receiver Transfer Enable */
#define
AT91_PDC_RXTDIS (1 << 1)
/* Receiver Transfer Disable */
#define
AT91_PDC_TXTEN (1 << 8)
/* Transmitter Transfer Enable */
#define
AT91_PDC_TXTDIS (1 << 9)
/* Transmitter Transfer Disable */
#define AT91_PDC_PTCR
0x120
/* Transfer Control Register */
#define
AT91_PDC_RXTEN (1 << 0)
/* Receiver Transfer Enable */
#define
AT91_PDC_RXTDIS (1 << 1)
/* Receiver Transfer Disable */
#define
AT91_PDC_TXTEN (1 << 8)
/* Transmitter Transfer Enable */
#define
AT91_PDC_TXTDIS (1 << 9)
/* Transmitter Transfer Disable */
#define AT91_PDC_PTSR
0x124
/* Transfer Status Register */
#define AT91_PDC_PTSR
0x124
/* Transfer Status Register */
#endif
bsp/at91sam9260/platform/at91_pio.h
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/*
* File : at91_pio.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
@@ -30,35 +15,35 @@
extern
"C"
{
#endif
#define PIO_PER
0x00
/* Enable Register */
#define PIO_PDR
0x04
/* Disable Register */
#define PIO_PSR
0x08
/* Status Register */
#define PIO_OER
0x10
/* Output Enable Register */
#define PIO_ODR
0x14
/* Output Disable Register */
#define PIO_OSR
0x18
/* Output Status Register */
#define PIO_IFER
0x20
/* Glitch Input Filter Enable */
#define PIO_IFDR
0x24
/* Glitch Input Filter Disable */
#define PIO_IFSR
0x28
/* Glitch Input Filter Status */
#define PIO_SODR
0x30
/* Set Output Data Register */
#define PIO_CODR
0x34
/* Clear Output Data Register */
#define PIO_ODSR
0x38
/* Output Data Status Register */
#define PIO_PDSR
0x3c
/* Pin Data Status Register */
#define PIO_IER
0x40
/* Interrupt Enable Register */
#define PIO_IDR
0x44
/* Interrupt Disable Register */
#define PIO_IMR
0x48
/* Interrupt Mask Register */
#define PIO_ISR
0x4c
/* Interrupt Status Register */
#define PIO_MDER
0x50
/* Multi-driver Enable Register */
#define PIO_MDDR
0x54
/* Multi-driver Disable Register */
#define PIO_MDSR
0x58
/* Multi-driver Status Register */
#define PIO_PUDR
0x60
/* Pull-up Disable Register */
#define PIO_PUER
0x64
/* Pull-up Enable Register */
#define PIO_PUSR
0x68
/* Pull-up Status Register */
#define PIO_ASR
0x70
/* Peripheral A Select Register */
#define PIO_BSR
0x74
/* Peripheral B Select Register */
#define PIO_ABSR
0x78
/* AB Status Register */
#define PIO_OWER
0xa0
/* Output Write Enable Register */
#define PIO_OWDR
0xa4
/* Output Write Disable Register */
#define PIO_OWSR
0xa8
/* Output Write Status Register */
#define PIO_PER
0x00
/* Enable Register */
#define PIO_PDR
0x04
/* Disable Register */
#define PIO_PSR
0x08
/* Status Register */
#define PIO_OER
0x10
/* Output Enable Register */
#define PIO_ODR
0x14
/* Output Disable Register */
#define PIO_OSR
0x18
/* Output Status Register */
#define PIO_IFER
0x20
/* Glitch Input Filter Enable */
#define PIO_IFDR
0x24
/* Glitch Input Filter Disable */
#define PIO_IFSR
0x28
/* Glitch Input Filter Status */
#define PIO_SODR
0x30
/* Set Output Data Register */
#define PIO_CODR
0x34
/* Clear Output Data Register */
#define PIO_ODSR
0x38
/* Output Data Status Register */
#define PIO_PDSR
0x3c
/* Pin Data Status Register */
#define PIO_IER
0x40
/* Interrupt Enable Register */
#define PIO_IDR
0x44
/* Interrupt Disable Register */
#define PIO_IMR
0x48
/* Interrupt Mask Register */
#define PIO_ISR
0x4c
/* Interrupt Status Register */
#define PIO_MDER
0x50
/* Multi-driver Enable Register */
#define PIO_MDDR
0x54
/* Multi-driver Disable Register */
#define PIO_MDSR
0x58
/* Multi-driver Status Register */
#define PIO_PUDR
0x60
/* Pull-up Disable Register */
#define PIO_PUER
0x64
/* Pull-up Enable Register */
#define PIO_PUSR
0x68
/* Pull-up Status Register */
#define PIO_ASR
0x70
/* Peripheral A Select Register */
#define PIO_BSR
0x74
/* Peripheral B Select Register */
#define PIO_ABSR
0x78
/* AB Status Register */
#define PIO_OWER
0xa0
/* Output Write Enable Register */
#define PIO_OWDR
0xa4
/* Output Write Disable Register */
#define PIO_OWSR
0xa8
/* Output Write Status Register */
#ifdef __cplusplus
}
...
...
bsp/at91sam9260/platform/at91_pit.h
浏览文件 @
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/*
* File : at91_pit.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
@@ -29,18 +15,18 @@
extern
"C"
{
#endif
#define AT91_PIT_MR
(AT91_PIT + 0x00)
/* Mode Register */
#define
AT91_PIT_PITIEN (1 << 25)
/* Timer Interrupt Enable */
#define
AT91_PIT_PITEN (1 << 24)
/* Timer Enabled */
#define
AT91_PIT_PIV (0xfffff)
/* Periodic Interval Value */
#define AT91_PIT_MR
(AT91_PIT + 0x00)
/* Mode Register */
#define
AT91_PIT_PITIEN (1 << 25)
/* Timer Interrupt Enable */
#define
AT91_PIT_PITEN (1 << 24)
/* Timer Enabled */
#define
AT91_PIT_PIV (0xfffff)
/* Periodic Interval Value */
#define AT91_PIT_SR
(AT91_PIT + 0x04)
/* Status Register */
#define
AT91_PIT_PITS (1 << 0)
/* Timer Status */
#define AT91_PIT_SR
(AT91_PIT + 0x04)
/* Status Register */
#define
AT91_PIT_PITS (1 << 0)
/* Timer Status */
#define AT91_PIT_PIVR
(AT91_PIT + 0x08)
/* Periodic Interval Value Register */
#define AT91_PIT_PIIR
(AT91_PIT + 0x0c)
/* Periodic Interval Image Register */
#define
AT91_PIT_PICNT (0xfff << 20)
/* Interval Counter */
#define
AT91_PIT_CPIV (0xfffff)
/* Inverval Value */
#define AT91_PIT_PIVR
(AT91_PIT + 0x08)
/* Periodic Interval Value Register */
#define AT91_PIT_PIIR
(AT91_PIT + 0x0c)
/* Periodic Interval Image Register */
#define
AT91_PIT_PICNT (0xfff << 20)
/* Interval Counter */
#define
AT91_PIT_CPIV (0xfffff)
/* Inverval Value */
#ifdef __cplusplus
}
...
...
bsp/at91sam9260/platform/at91_pmc.h
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bsp/at91sam9260/platform/at91_rstc.h
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bsp/at91sam9260/platform/at91_serial.h
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bsp/at91sam9260/platform/interrupt.h
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/*
* File : interrupt.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
...
...
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bsp/beaglebone/applications/board.h
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/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2013, RT-Thread Development Team
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
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...
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