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提交 561eac93 编写于 作者: B bernard.xiong@gmail.com
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kick off unnecessary code. 

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1637 bbd45198-f89e-11dd-88c7-29a3b14d5316
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wifi/os/os_defs.h 已删除 100644 → 0
浏览文件 @ b29605dc
/*
* Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
*/
#ifndef _OS_HEADER1_
#define _OS_HEADER1_
#endif /* _OS_HEADER1 */
wifi/os/os_headers.h 已删除 100644 → 0
浏览文件 @ b29605dc
/*
* Copyright Marvell International Ltd. and/or its affiliates, 2003-2006
*/
#ifndef _OS_HEADERS_H
#define _OS_HEADERS_H
#ifndef __ATTRIB_ALIGN__
#define __ATTRIB_ALIGN__ (__aligned(4)) //changed by dennis for compiler compatibility
#endif
#ifndef __ATTRIB_PACK__
//#define __ATTRIB_PACK__ __attribute__ ((packed))
//#define __ATTRIB_PACK__ //changed by dennis for compiler compatibility
#endif
/* RT_Thread header files */
#include <rtconfig.h>
#include <rtthread.h>
#include <rtdef.h>
#include <stdio.h>
#include <string.h>
/* New Code to synchronize between IEEE Power save and PM*/
#ifdef ENABLE_PM
#endif
/* ASM files */
/* Net header files */
/* Wireless header */
#endif
wifi/os/os_timers.h 已删除 100644 → 0
浏览文件 @ b29605dc
/*
* Copyright Marvell International Ltd. and/or its affiliates, 2003-2006
*/
#ifndef _OS_TIMERS_H
#define _OS_TIMERS_H
#include "os_defs.h"
typedef struct __WLAN_DRV_TIMER
{
//struct timer_list tl;
struct rt_timer tl;
void (*timeoutfunction)(void* parameter);
void (*timer_function) (void *context);
void *timer_parameter;
void *function_context;
unsigned int time_period;
char * name;
BOOLEAN timer_is_periodic;
BOOLEAN timer_is_canceled;
char init_flag; /*0:uninitialized 1:initialized 2:has been used at least once*/
} WLAN_DRV_TIMER, *PWLAN_DRV_TIMER;
static void TimerHandler(void* fcontext)
{
PWLAN_DRV_TIMER timer = (PWLAN_DRV_TIMER) fcontext;
timer->timer_function(timer->function_context);
// if (timer->timer_is_periodic == TRUE) {
// mod_timer(&timer->tl, jiffies + ((timer->time_period * HZ) / 1000));
// }
}
static void
InitializeTimer(PWLAN_DRV_TIMER timer,
void (*TimerFunction) (void *context), void *FunctionContext,char *name)
{
timer->timeoutfunction = TimerHandler;
timer->timer_parameter=timer;
if(name!=NULL)
timer->name=name;
// then tell the proxy which function to call and what to pass it
timer->timer_function = TimerFunction;
timer->function_context = FunctionContext;
timer->timer_is_canceled = FALSE;
timer->init_flag=1;
}
static void
SetTimer(PWLAN_DRV_TIMER timer, unsigned int MillisecondPeriod)
{
/* timer->time_period = MillisecondPeriod;
timer->timer_is_periodic = FALSE;
timer->tl.expires = jiffies + (MillisecondPeriod * HZ) / 1000;
add_timer(&timer->tl);
timer->timer_is_canceled = FALSE;
*/
}
static void
ModTimer(PWLAN_DRV_TIMER timer, unsigned int MillisecondPeriod)
{
int tick= (MillisecondPeriod/1000)*RT_TICK_PER_SECOND;
timer->timer_is_periodic = FALSE;
timer->time_period = MillisecondPeriod;
if(timer->init_flag==1)
{
rt_timer_init(&timer->tl, timer->name, timer->timeoutfunction,timer->timer_parameter,
tick,RT_TIMER_FLAG_ONE_SHOT);
timer->init_flag=2;
}else if(timer->init_flag==2){
rt_timer_control(&timer->tl, RT_TIMER_CTRL_SET_TIME, &tick);
}
rt_timer_start(&timer->tl);
timer->timer_is_periodic = FALSE;
}
static void
SetPeriodicTimer(PWLAN_DRV_TIMER timer, unsigned int MillisecondPeriod)
{
/* timer->time_period = MillisecondPeriod;
timer->timer_is_periodic = TRUE;
timer->tl.expires = jiffies + (MillisecondPeriod * HZ) / 1000;
add_timer(&timer->tl);
timer->timer_is_canceled = FALSE;
*/
}
#define FreeTimer(x) do {} while (0)
static void CancelTimer(WLAN_DRV_TIMER * timer)
{
/* del_timer(&timer->tl);
timer->timer_is_canceled = TRUE;
*/
rt_timer_detach(&timer->tl);
}
#endif /* _OS_TIMERS_H */
wifi/spi/gspi8686.h 已删除 100644 → 0
浏览文件 @ b29605dc
此差异已折叠。
wifi/spi/gspi_debug.h 已删除 100644 → 0
浏览文件 @ b29605dc
/*
* Debugging macros
*
* Copyright Marvell International Ltd. and/or its affiliates, 2003-2006
*/
#define DEBUG_SSP_LEVEL3
#ifdef DEBUG_SSP_LEVEL0
#define spi_debug1(...)
#define spi_debug2(...)
#define spi_debug3(...)
#endif
#ifdef DEBUG_SSP_LEVEL1
#define spi_debug1 rt_kprintf
#define spi_debug2 //rt_kprintf
#define spi_debug3 //rt_kprintf
#endif
#ifdef DEBUG_SSP_LEVEL2
#define spi_debug1 rt_kprintf
#define spi_debug2 rt_kprintf
#define spi_debug3 //rt_kprintf
#endif
#ifdef DEBUG_SSP_LEVEL3
#define spi_debug1 rt_kprintf
#define spi_debug2 rt_kprintf
#define spi_debug3 rt_kprintf
#endif
wifi/spi/gspi_io.c 已删除 100644 → 0
浏览文件 @ b29605dc
/*
* File: gspi_io.c
* Desc: Low level SSP driver on pxa27x for GSPI
*
* Copyright Marvell International Ltd. and/or its affiliates, 2003-2006
*/
/********************************************************
Change log:
01/30/06: Add kernel 2.6 support for GSPI8xxx/Bulverde
********************************************************/
#include "sep4020.h"
#include "rtthread.h"
#include "gspi_io.h"
#include "gspi_debug.h"
static int DMA_ENABLE=1;
int g_dummy_clk_reg = 0;
int g_dummy_clk_ioport = 0;
int g_bus_mode_reg = 0x02;
gspihost_info_t *G_gspiinfo;
static struct rt_semaphore gspi_lock;
static struct rt_event txrxevent; //only set or rec the 0x01
#define DMA_TX_ONLY (1)
#define DMA_TX_RX (2)
#define DMA_Dummy_TX (4)
#define DMA_NO_ACTION (0)
static char DMA_ACTION;
#define MaskWarning(x) ((x)=(x))
extern void rt_hw_interrupt_install(rt_uint32_t vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler);
extern void rt_hw_interrupt_umask(rt_uint32_t vector);
static int gspi_acquire_io(void)
{
rt_sem_take(&gspi_lock, RT_WAITING_FOREVER);
return 0;
}
static void gspi_release_io(void)
{
rt_sem_release(&gspi_lock);
return;
}
static char transmittembuf[2048];
void setup_write_dma(char * data ,int n)
{
unsigned int regval=0;
int i;
/*clear the interupt*/
/*0 is tx channel */
*(volatile unsigned long*)DMAC_INTINTERRCLR_V |= 0x1;
*(volatile unsigned long*)DMAC_INTINTERRCLR_V &= (~0x1); //clear the erro interupt
*(volatile unsigned long*)DMAC_INTTCCLEAR_V |= 0x1;
*(volatile unsigned long*)DMAC_INTTCCLEAR_V &= (~0x1); //clear the interupt
/*set source address*/
*(volatile unsigned long*)DMAC_C0SRCADDR_V = (unsigned int)data;
/*set target address*/
*(volatile unsigned long*)DMAC_C0DESTADDR_V = SSI_DR;
/*clear the size*/
//*(volatile unsigned long*)DMAC_C0CONTROL_V = 0;
//desc->dcmd |= DCMD_ENDIRQEN | n;
/*set transfer size,data width is 2 bytes,burst size is 4*2bytes,source Address Increment*/
regval=((n/2) <<14)+(0x1<<12)+(0x1<<9)+(0x1<<6)+((0x0)<<3)+(0x0);
*(volatile unsigned long*)DMAC_C0CONTROL_V = regval;
/*write data from memory to ssi*/
// *(volatile unsigned long*)DMAC_C0CONFIGURATION_V=0;
*(volatile unsigned long*)DMAC_C0DESCRIPTOR_V = 0;
/* 2) start DMA channel */
/*spi dma set*/
*(volatile unsigned long*)SSI_DMATDLR_V=0x2; // (0x10009050)//tx DMA threadthold
if(DMA_ACTION==DMA_TX_RX)
{
#if 0
*(volatile unsigned long*)SSI_DMARDLR_V=0x2;
*(volatile unsigned long*)SSI_DMACR_V|=(0x3); //0x1 rxDMAenable 0x2 txDMAenable
*(volatile unsigned long*)DMAC_C1CONFIGURATION_V = ((0x5)<<7) +((0x2)<<1)+0x01;
*(volatile unsigned long*)DMAC_C0CONFIGURATION_V = ((0x5)<<11)+((0x1)<<1)+0x01;
#else
*(volatile unsigned long*)SSI_DMARDLR_V=0x4;
*(volatile unsigned long*)SSI_DMACR_V|=(0x1); //0x1 rxDMAenable 0x2 txDMAenable
*(volatile unsigned long*)DMAC_C1CONFIGURATION_V = ((0x5)<<7) +((0x2)<<1)+0x01;
for(i=0;i<n/2;i++)
{
while((*(volatile unsigned long*)SSI_SR_V&2)==0);
*(volatile unsigned long* )SSI_DR_V = 0;
}
#endif
}else if(DMA_ACTION==DMA_TX_ONLY)
{
*(volatile unsigned long*)SSI_DMACR_V|=(0x1<<1); //0x1 rxDMAenable 0x2 txDMAenable
*(volatile unsigned long*)DMAC_C0CONFIGURATION_V = ((0x5)<<11)+((0x1)<<1)+0x01;
}
}
int gspi_write_data_direct(u8 * data, u16 reg, u16 n)
{
int i;
u16 *dat;
rt_uint32_t e;
gspi_acquire_io();
/* N bytes are sent wrt to 16 bytes, convert it to 8 bytes */
n = (n * 2);
/*active CS signal*/
*(volatile unsigned long*)(GPIO_PORTD_DATA_V)&=~0x04;
reg |= 0x8000;
rt_memcpy(transmittembuf, &reg, sizeof(u16));
rt_memcpy(transmittembuf + sizeof(u16), data, (n - 2));
if((n>16)&&(DMA_ENABLE==1))
{
//Write data by DMA mode
DMA_ACTION=DMA_TX_ONLY;
setup_write_dma(transmittembuf,n);
rt_event_recv(&txrxevent,0x01,RT_EVENT_FLAG_OR|RT_EVENT_FLAG_CLEAR,RT_WAITING_FOREVER,&e);
}else{
//Write data through SSDR by CPU mode
dat = (u16 *) transmittembuf;
*(volatile unsigned long*)SSI_DMACR_V&=(~0x3); //0x1 rxDMAenable 0x2 txDMAenable
for (i = 0; i < (n / 2); i++) {
while((*(volatile unsigned long*)SSI_SR_V&2)==0){}
*(volatile unsigned long*)SSI_DR_V = *dat++; //add for 4020
}
if ((n % 4) != 0) {
while((*(volatile unsigned long*)SSI_SR_V&2)==0){}
*(volatile unsigned long*)SSI_DR_V = 0;//add for 4020
}
while((*(volatile unsigned long*)SSI_SR_V&1)==1);
}
/*inactive CS frame*/
*(volatile unsigned long*)(GPIO_PORTD_DATA_V)|=0x04;
gspi_release_io();
return 0;
}
int gspi_write_reg( u16 reg, u16 val)
{
gspi_write_data_direct((u8 *) & val, reg, 2);
return 0;
}
int gspi_write_data( u16 * data, u16 size)
{
gspi_write_data_direct((u8 *) & data[1], data[0], 2);
return 0;
}
static char rectembuf[2048+1024];
static char rxtxdummybuf[2048+1024];
void
gspi_write_to_read(int n,u16 reg,u16*data)
{
u16 temp;
/*config the receive channel*/
/*set source address*/
*(volatile unsigned long*)DMAC_C1SRCADDR_V = SSI_DR;
/*set target address*/
*(volatile unsigned long*)DMAC_C1DESTADDR_V = (unsigned int)data;
/*clear the size*/
// *(volatile unsigned long*)DMAC_C1CONTROL_V = 0; //~(0x3ffd000)
/*set transfer size,data width is 2 bytes,burst size is 4*2bytes,source Address Increment*/
*(volatile unsigned long*)DMAC_C1CONTROL_V = ((n /2)<<14)+(1<<13) + (1<<9) + (1<<6)+((0x3)<<3) +(0x3);
/*receive data from ssi*/
*(volatile unsigned long*)DMAC_C1CONFIGURATION_V = ((0x5)<<7) +((0x2)<<1)+0x01;
*(volatile unsigned long*)DMAC_C1DESCRIPTOR_V = 0;
#if 0
/*config the transfer channel*/
/*set source address*/
*(volatile unsigned long*)DMAC_C0SRCADDR_V = gspiinfo->phys_addr_rw;
/*set target address*/
*(volatile unsigned long*)DMAC_C0DESTADDR_V = SSI_DR;
/*clear the size*/
*(volatile unsigned long*)DMAC_C0CONTROL_V = ~(0x3ffd000);
/*set transfer size,data width is 2 bytes,burst size is 4*2bytes,source Address Increment*/
*(volatile unsigned long*)DMAC_C0CONTROL_V = (n <<14)|(1<<12) | (1<<9) | (1<<6) |((011)<<3) | (011);
/*write data from memory to ssi*/
*(volatile unsigned long*)DMAC_C0CONFIGURATION_V = ((0101)<<11) | ((01)<<1);
/*set address of next descripor */
*(volatile unsigned long*)DMAC_C0DESCRIPTOR_V = 0;
*(volatile unsigned long*)DMAC_C1DESCRIPTOR_V = 0;
/* Start Rx for read */
*(volatile unsigned long*)DMAC_C1CONFIGURATION_V = 0x01; //enable channel 1
/* Start Tx for dummy write */
*(volatile unsigned long*)DMAC_C0CONFIGURATION_V = 0x01; //enable channel 0
#endif
#if 1
/* Write the register to read */
*(volatile unsigned long*)SSI_DMACR_V&=(~0x3); //0x1 rxDMAenable 0x2 txDMAenable
*(volatile unsigned long* )SSI_DR_V = reg;
while((*(volatile unsigned long*)SSI_SR_V&8))
temp = *(volatile unsigned long* )SSI_DR_V;
temp=temp;
#endif
setup_write_dma(rxtxdummybuf ,n);
}
void setup_read_dma(u16 reg, u16 * data, int n)
{
/*clear the interupt*/
*(volatile unsigned long*)DMAC_INTINTERRCLR_V |= 0x2;
*(volatile unsigned long*)DMAC_INTINTERRCLR_V &= (~0x2); //clear the erro interupt
*(volatile unsigned long*)DMAC_INTTCCLEAR_V |= 0x2;
*(volatile unsigned long*)DMAC_INTTCCLEAR_V &= (~0x2);
gspi_write_to_read(n, reg,data);
}
int gspi_read_data_direct(u8 * data, u16 reg, u16 n)
{
int fifonum=0;
int i;
u32 nothing;
u16 *dat;
rt_uint32_t e;
int retry = 0;
int timeout = 100;
int dmaflag=0;
MaskWarning(nothing);
if (gspi_acquire_io()) {
return -1;
}
for(fifonum=0;fifonum<16;fifonum++)//clear fifo add by vincent for 4020
{
nothing = *(volatile unsigned long* )SSI_DR_V;
}
n = ((n + g_dummy_clk_ioport) * 2);
/*active SPI CS */
*(volatile unsigned long*)(GPIO_PORTD_DATA_V)&=~0x04;
///Process the data
#if 1
if(n>16&&(DMA_ENABLE==1))
//if((DMA_ENABLE==1))
{
DMA_ACTION=DMA_TX_RX;
dmaflag=1;
do {
retry = 0;
spi_debug3("DMA MODEL");
DMA_ACTION=DMA_TX_RX;
setup_read_dma(reg,(u16*) rectembuf, n);
rt_event_recv(&txrxevent,0x01,RT_EVENT_FLAG_OR|RT_EVENT_FLAG_CLEAR,RT_WAITING_FOREVER,&e);
if (rectembuf[(g_dummy_clk_ioport + 1) * 2] == 0xff) {
if (!rt_memcmp(&rectembuf[(g_dummy_clk_ioport + 1) * 2],&rxtxdummybuf[2], 5)) {
retry = 1;
}
}
} while ( retry && --timeout);
if (!timeout)
spi_debug1("Timeout for gspi_read_data_direct\n");
}else
#endif
{
dat=(u16*)rectembuf;
*(volatile unsigned long*)SSI_DMACR_V&=(~0x3); //0x1 rxDMAenable 0x2 txDMAenable
while((*(volatile unsigned long*)SSI_SR_V&2)==0);
*(volatile unsigned long* )SSI_DR_V = reg;
for (i = 0; i < (n / 2); i++) {
while((*(volatile unsigned long*)SSI_SR_V&2)==0);
*(volatile unsigned long* )SSI_DR_V = 0;
while((*(volatile unsigned long*)SSI_SR_V&8)==0);
*dat = *(volatile unsigned long* )SSI_DR_V;
dat++;
}
}
*(volatile unsigned long*)(GPIO_PORTD_DATA_V)|=0x04;
if(dmaflag==1)
rt_memcpy(data, rectembuf + (g_dummy_clk_ioport + 1) * 2+12,
(n - (g_dummy_clk_ioport + 1) * 2+12));
else
rt_memcpy(data, rectembuf + (g_dummy_clk_ioport + 1) * 2,
(n - (g_dummy_clk_ioport + 1) * 2));
gspi_release_io();
return 0;
}
int gspi_read_data( u16 * data, u16 size)
{
return gspi_read_data_direct((u8 *) & data[1], data[0], 2);
}
int gspi_read_reg( u16 reg, u16 * val)
{
gspi_read_data_direct((u8 *) val, reg, 2);
return 0;
}
extern void sbi_interrupt(int vector);
static void spi_interrupt(int dev)
{
unsigned int intstate;
unsigned int rcl;
MaskWarning(rcl);
intstate=*(volatile unsigned long*)SSI_ISR_V;
// spi_debug1("spi spi_interrupt\r\n");
if(intstate&0x01)
{
spi_debug1("spi tx fifo empty\r\n");
}
if(intstate&(0x01<<1))
{
spi_debug1("spi tx fifo up over\r\n");
rcl=*(volatile unsigned long*)SSI_TXOICR_V;
}
if(intstate&(0x01<<2))
{
spi_debug1("spi Rx fifo down over\r\n");
rcl=*(volatile unsigned long*)SSI_RXUICR_V;
}
if(intstate&(0x01<<3))
{
spi_debug1("spi rx fifo up over\r\n");
rcl=*(volatile unsigned long*)SSI_RXOICR_V;
}
if(intstate&(0x01<<4))
{
spi_debug1("spi rx fifo full\r\n");
}
rcl=*(volatile unsigned long*)SSI_ICR_V;
}
static void dma_interrupt(int dev)
{
unsigned int intstatus;
unsigned int endstatus;
unsigned int errstatus;
unsigned int rcl;
rcl=rcl;
intstatus=*(volatile unsigned long*)DMAC_INTSTATUS_V;
endstatus=*(volatile unsigned long*)DMAC_INTTCSTATUS_V;
errstatus=*(volatile unsigned long*)DMAC_INTERRORSTATUS_V;
spi_debug1("dma int int 0x%x,end 0x%x,err0x%x\r\n",intstatus,endstatus,errstatus);
if(intstatus&0x01) //channel 0 tx channel
{
if(endstatus&0x01)
{
*(volatile unsigned long*)DMAC_INTTCCLEAR_V=endstatus|0x01;
*(volatile unsigned long*)DMAC_INTTCCLEAR_V=endstatus&(~0x01);
}
if(errstatus&0x01)
{
*(volatile unsigned long*)DMAC_INTERRORSTATUS_V=endstatus|0x01;
*(volatile unsigned long*)DMAC_INTERRORSTATUS_V=endstatus&(~0x01);
}
if(DMA_ACTION==DMA_TX_ONLY)
{
rt_event_send(&txrxevent, 0X01);
}
*(volatile unsigned long*)SSI_DMACR_V&=(~0x01); //0x1 rxDMAenable 0x2 txDMAenable
}
if(intstatus&0x02) //channel 1 rx channel
{
if(endstatus&0x02)
{
*(volatile unsigned long*)DMAC_INTTCCLEAR_V=endstatus|0x02;
*(volatile unsigned long*)DMAC_INTTCCLEAR_V=endstatus&(~0x02);
}
if(errstatus&0x02)
{
*(volatile unsigned long*)DMAC_INTERRORSTATUS_V=endstatus|0x02;
*(volatile unsigned long*)DMAC_INTERRORSTATUS_V=endstatus&(~0x02);
}
if(DMA_ACTION==DMA_TX_RX)
{
rt_event_send(&txrxevent, 0X01);
*(volatile unsigned long*)SSI_DMACR_V&=(~0x02); //0x1 rxDMAenable 0x2 txDMAenable
}
}
// *(volatile unsigned long*)(SSI_SSIENR_V)= 0x00; //disable SSI
// *(volatile unsigned long*)(SSI_SER_V)= 0x00; //disable SSI channel0
rcl=*(volatile unsigned long*)SSI_ICR_V;
rcl=*(volatile unsigned long*)SSI_RXOICR_V;
rcl=*(volatile unsigned long*)SSI_RXUICR_V;
// *(volatile unsigned long*)(SSI_SSIENR_V)= 0x01; //disable SSI
// *(volatile unsigned long*)(SSI_SER_V)= 0x01; //disable SSI channel0
DMA_ACTION=0;
}
extern void rt_hw_interrupt_install(rt_uint32_t vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler);
int gspi_register_irq(int * irqnum)
{
disable_irq(INTSRC_EXINT4) ;
*(volatile unsigned long*)(GPIO_PORTA_DIR_V) |= (0X1)<<4;
*(volatile unsigned long*)(GPIO_PORTA_SEL_V )|= (0X1)<<4;
*(volatile unsigned long*)(GPIO_PORTA_INCTL_V) |= (0X1)<<4;
*(volatile unsigned long*)(GPIO_PORTA_INTRCTL_V) |= (0X11)<<8;//low level enable irq
*(volatile unsigned long*)(GPIO_PORTA_INTRCLR_V) |= (0X1)<<4; //add for 4020 GPA6
*irqnum= INTSRC_EXINT4;
rt_hw_interrupt_install(INTSRC_EXINT4, sbi_interrupt, RT_NULL);
rt_hw_interrupt_umask(INTSRC_EXINT4);
return 0;
}
void gspi_irq_clear(void)
{
*(volatile unsigned long*)(GPIO_PORTA_INTRCLR_V) |= (0X1)<<4; //add for 4020 GPA6
}
static int dma_init( void )
{
// *(volatile unsigned long*)(DMAC_ENBLDCHNS_V ) = (1<<0)+(1<<1); //enable the channels
if(DMA_ENABLE==1)
{
rt_memset(rxtxdummybuf,0x00,(2048+1024));
rt_hw_interrupt_install(INTSRC_SSI, spi_interrupt, RT_NULL);
rt_hw_interrupt_umask(INTSRC_SSI);
enable_irq(INTSRC_SSI);
}
rt_hw_interrupt_install(INTSRC_DMAC, dma_interrupt, RT_NULL);
rt_hw_interrupt_umask(INTSRC_DMAC);
enable_irq(INTSRC_DMAC);
spi_debug3("\nDMA Initialization done....\n");
return 0;
}
static int gspihost_init_hw(void)
{
*(volatile unsigned long*)(GPIO_PORTD_DIR_V)&=~0x04;
*(volatile unsigned long*)(GPIO_PORTD_SEL_V)&=~0x1b;
*(volatile unsigned long*)(GPIO_PORTD_SEL_V)|= 0x04;
*(volatile unsigned long*)(SSI_SSIENR_V)= 0x00; //disable SSI
*(volatile unsigned long*)(SSI_BAUDR_V) = 0x08; //set baudrate
*(volatile unsigned long*)(SSI_TXFLR_V) = 0x00;
*(volatile unsigned long*)(SSI_RXFLR_V) = 0x00;
*(volatile unsigned long*)(SSI_CONTROL0_V) = 0x0f; //?configure SSI channel0
*(volatile unsigned long*)(SSI_IMR_V) = 0x00;//0x1f; //mask all irqs of ssi
*(volatile unsigned long*)(SSI_SER_V)= 0x01; //enable SSI channel0
*(volatile unsigned long*)(SSI_SSIENR_V)= 0x01; //enable SSI
return 0;
}
int gspihost_init(void)
{
int ret=RT_EOK;
spi_debug1("gspihost_init\n");
ret=rt_sem_init(&gspi_lock, "wifi_gspi", 1, RT_IPC_FLAG_FIFO);
if(ret!=RT_EOK)
ret=rt_event_init(&txrxevent, "spievent", RT_IPC_FLAG_FIFO);
if(ret!=RT_EOK)
return ret;
gspihost_init_hw();
if( DMA_ENABLE==1)
dma_init();
return 0;
}
wifi/spi/gspi_io.h 已删除 100644 → 0
浏览文件 @ b29605dc
/*
* File: gspi_io.h
*
* Copyright Marvell International Ltd. and/or its affiliates, 2003-2006
*/
#ifndef _GSPI_IO_H
#define _GSPI_IO_H
typedef char s8;
typedef unsigned char u8;
typedef signed short s16;
typedef unsigned short u16;
typedef signed long s32;
typedef unsigned long u32;
typedef signed long long s64;
typedef unsigned long long u64;
#define GPIO_PORTA_DIR_V (0x1000f004)
#define GPIO_PORTA_SEL_V (0x1000f008)
#define GPIO_PORTA_INCTL_V (0x1000f00c)
#define GPIO_PORTA_INTRCTL_V (0x1000f010)
#define GPIO_PORTA_INTRCLR_V (0x1000f014)
#define GPIO_PORTD_DIR_V (0x1000f034)
#define GPIO_PORTD_SEL_V (0x1000f038)
#define GPIO_PORTD_DATA_V (0x1000f040)
#define SSI_CONTROL0_V (0x10009000)
#define SSI_CONTROL1_V (0x10009004)
#define SSI_SSIENR_V (0x10009008)
#define SSI_SER_V (0x10009010)
#define SSI_BAUDR_V (0x10009014)
#define SSI_TXFLR_V (0x10009020)
#define SSI_RXFLR_V (0x1000901C)
#define SSI_SR_V (0x10009028)
#define SSI_IMR_V (0x1000902c)
#define SSI_ISR_V (0x10009030)
#define SSI_TXOICR_V (0x10009038)
#define SSI_RXOICR_V (0x1000903C)
#define SSI_RXUICR_V (0x10009040)
#define SSI_DR_V (0x10009060)
#define SSI_DMACR_V (0x1000904C)
#define SSI_ICR_V (0x10009048)
#define SSI_DMATDLR_V (0x10009050)
#define SSI_DMARDLR_V (0x10009054)
#define DMAC_INTSTATUS_V (0x11001020)
#define DMAC_INTTCSTATUS_V (0x11001050)
#define DMAC_INTTCCLEAR_V (0x11001060)
#define DMAC_INTINTERRCLR_V (0x11001090)
#define DMAC_INTTCCLEAR_V (0x11001060)
#define DMAC_INTERRORSTATUS_V (0x11001090)
#define DMAC_INTERRCLR_V (0x11001080)
#define DMAC_C0SRCADDR_V (0x11001000)
#define DMAC_C1SRCADDR_V (0x11001100)
#define DMAC_C0DESTADDR_V (0x11001004)
#define DMAC_C1DESTADDR_V (0x11001104)
#define DMAC_C0CONTROL_V (0x1100100C)
#define DMAC_C1CONTROL_V (0x1100110C)
#define DMAC_C0CONFIGURATION_V (0x11001010)
#define DMAC_C1CONFIGURATION_V (0x11001110)
#define DMAC_C0DESCRIPTOR_V (0x11001014)
#define DMAC_C1DESCRIPTOR_V (0x11001114)
#define DMAC_ENBLDCHNS_V (0x110010B0)
#define GSPI_OK 0
typedef struct gspihost_info gspihost_info_t;
typedef gspihost_info_t *gspihost_info_p;
typedef struct gspi_card_rec *gspi_card_rec_p;
typedef struct gspi_card_rec io_card_rec_t;
typedef io_card_rec_t *io_card_rec_p;
struct gspi_card_rec
{
u8 magic[4];
gspihost_info_p ctrlr; // Back Reference to Host Controller
int (*add) (gspi_card_rec_p card);
int (*remove) (gspi_card_rec_p card);
// IRQ_RET_TYPE(*user_isr) (int, void *, struct pt_regs *);
void *user_arg;
u16 chiprev;
};
struct gspihost_info
{
int irq;
u16 dev_id;
int dma_init; /* physical address */
unsigned char *iodata; /* I/O data buffer */
unsigned char *iorw; /* I/O data buffer */
gspi_card_rec_p card;
};
extern int gspi_read_reg(u16 reg, u16 * data);
extern int gspi_write_reg(u16 reg, u16 data);
extern int gspi_read_data(u16 * data, u16 size);
extern int gspi_write_data(u16 * data, u16 size);
//extern int gspi_read_data_direct(u8 * data, u16 reg, u16 size);
extern int gspi_write_data_direct(u8 * data, u16 reg, u16 n);
extern int gspi_read_data_direct(u8 * data, u16 reg, u16 n);
//extern int gspi_write_data_direct(u8 * data, u16 reg, u16 size);
extern void gspi_irq_clear(void);//FOR 4020
extern int gspihost_init(void);
#endif /* _GSPI_IO_H */
wifi/spi/helper.h 已删除 100644 → 0
浏览文件 @ b29605dc
此差异已折叠。
wifi/spi/if_gspi.c 已删除 100644 → 0
浏览文件 @ b29605dc
此差异已折叠。
wifi/spi/if_gspi.h 已删除 100644 → 0
浏览文件 @ b29605dc
/** @file if_gspi.h
* @brief This file contains MSU registers definition
*
* Copyright Marvell International Ltd. and/or its affiliates, 2003-2006
*/
/********************************************************
Change log:
09/26/05: Add Doxygen format comments
********************************************************/
#ifndef __GSPIREG_H_
#define __GSPIREG_H_
#include "..\wlan\include.h" //changed by dennis
/* GSPI Registers Offset. All the resgisters are at DWORD boundary */
#define DEVICEID_CTRL_REG 0x00
#define CHIPREV_REG 0x02
#define IO_READBASE_REG 0x04
#define IO_WRITEBASE_REG 0x08
#define IO_RDWRPORT_REG 0x0C
#define CMD_READBASE_REG 0x10
#define CMD_WRITEBASE_REG 0x14
#define CMD_RDWRPORT_REG 0x18
#define DATA_READBASE_REG 0x1C
#define DATA_WRITEBASE_REG 0x20
#define DATA_RDWRPORT_REG 0x24
#define SCRATCH_1_REG 0x28
#define SCRATCH_2_REG 0x2C
#define SCRATCH_3_REG 0x30
#define SCRATCH_4_REG 0x34
#define TX_FRAME_SEQ_NUM_REG 0x38
#define TX_FRAME_STATUS_REG 0x3C
#define HOST_INT_CTRL_REG 0x40
#define CARD_INT_CAUSE_REG 0x44
#define CARD_INT_STATUS_REG 0x48
#define CARD_INT_EVENT_MASK_REG 0x4C
#define CARD_INT_STATUS_MASK_REG 0x50
#define CARD_INT_RESET_SELECT_REG 0x54
#define HOST_INT_CAUSE_REG 0x58
#define HOST_INT_STATUS_REG 0x5C
#define HOST_INT_EVENT_MASK_REG 0x60
#define HOST_INT_STATUS_MASK_REG 0x64
#define HOST_INT_RESET_SELECT_REG 0x68
#define DELAY_READ_REG 0x6C
#define SPU_BUS_MODE_REG 0x70
#define BUS_MODE_16_NO_DELAY 0x02
/* Bit definition for CARD_INT_CAUSE (Card Interrupt Cause) */
#define CIC_TxDnLdOvr B_BIT_0
#define CIC_RxUpLdOvr B_BIT_1
#define CIC_CmdDnLdOvr B_BIT_2
#define CIC_HostEvent B_BIT_3
#define CIC_CmdUpLdOvr B_BIT_4
#define CIC_PwrDown B_BIT_5
/* Bit definition for HOST_INT_STATUS (Host Interrupt Status) */
#define GHIS_TxDnLdRdy B_BIT_0
#define GHIS_RxUpLdRdy B_BIT_1
#define GHIS_CmdDnLdRdy B_BIT_2
#define GHIS_CardEvent B_BIT_3
#define GHIS_CmdUpLdRdy B_BIT_4
#define GHIS_IOWrFifoOvrflow B_BIT_5
#define GHIS_IORdFifoUndrflow B_BIT_6
#define GHIS_DATAWrFifoOvrflow B_BIT_7
#define GHIS_DATARdFifoUndrflow B_BIT_8
#define GHIS_CMDWrFifoOvrflow B_BIT_9
#define GHIS_CMDRdFifoUndrflow B_BIT_10
/* Bit definition for HOST_INT_STATUS_MASK_REG (Host Interrupt Status Mask) */
#define HISM_TxDnLdRdy B_BIT_0
#define HISM_RxUpLdRdy B_BIT_1
#define HISM_CmdDnLdRdy B_BIT_2
#define HISM_CardEvent B_BIT_3
#define HISM_CmdUpLdRdy B_BIT_4
#define HISM_IOWrFifoOvrflow B_BIT_5
#define HISM_IORdFifoUndrflow B_BIT_6
#define HISM_DATAWrFifoOvrflow B_BIT_7
#define HISM_DATARdFifoUndrflow B_BIT_8
#define HISM_CMDWrFifoOvrflow B_BIT_9
#define HISM_CMDRdFifoUndrflow B_BIT_10
/* Bit definition for HOST_INT_CTRL_REG (Host Interrupt Control) */
#define HIC_WakeUp B_BIT_0
#define HIC_WlanRdy B_BIT_1
#define HIC_TxDnldAuto B_BIT_5
#define HIC_RxUpldAuto B_BIT_6
#define HIC_CmdDnldAuto B_BIT_7
#define HIC_CmdUpldAuto B_BIT_8
/* Bit definition for SPU_BUS_MODE_REG (SPU Bus mode register)*/
#define SBM_DataFormat_2 B_BIT_2
/* Value to check once the firmware is downloaded */
#define FIRMWARE_DNLD_OK 0x88888888
/* Value to write to indicate end of firmware dnld */
#define FIRMWARE_DNLD_END 0x0000
#define FIRMWARE_DNLD_PCKCNT 64
#endif /* __GSPIREG_H_ */
wifi/spi/if_gspi_debug.h 已删除 100644 → 0
浏览文件 @ b29605dc
/** @file if_gspi.h
* @brief This file contains MSU registers definition
*
* Copyright Marvell International Ltd. and/or its affiliates, 2003-2006
*/
/********************************************************
Change log:
09/26/05: Add Doxygen format comments
********************************************************/
#ifndef __IF_GSPI_DEBUG_H_
#define __IF_GSPI_DEBUG_H_
#define DEBUG_IF_SSP_LEVEL3
#ifdef DEBUG_IF_SSP_LEVEL0
#define ifspi_debug1(...)
#define ifspi_debug2(...)
#define ifspi_debug3(...)
#endif
#ifdef DEBUG_IF_SSP_LEVEL1
#define ifspi_debug1(a...) rt_kprintf(a)
#define ifspi_debug2(a...) do{}while(0)
#define ifspi_debug3(a...) do{}while(0)
#endif
#ifdef DEBUG_IF_SSP_LEVEL2
#define ifspi_debug1(a...) rt_kprintf(a)
#define ifspi_debug2(a...) rt_kprintf(a)
#define ifspi_debug3(a...) do{}while(0)
#endif
#ifdef DEBUG_IF_SSP_LEVEL3
#define ifspi_debug1(a...) rt_kprintf(a)
#define ifspi_debug2(a...) rt_kprintf(a)
#define ifspi_debug3(a...) rt_kprintf(a)
#endif
#endif /* __GSPIREG_H_ */
wifi/wlan/gspibin.h 已删除 100644 → 0
浏览文件 @ b29605dc
此差异已折叠。
wifi/wlan/helper_gspi.h 已删除 100644 → 0
浏览文件 @ b29605dc
char helpgspibin[]={
0x03,0x00,0x00,0xEA,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x50,0x00,0x9F,0xE5,0x10,0x0F,0x01,0xEE,0x00,0x00,0xE0,0xE3,
0x48,0x10,0x9F,0xE5,0x0C,0x00,0x81,0xE5,0x18,0x00,0x91,0xE5,0x20,0x08,0xA0,0xE1,
0x0B,0x00,0x50,0xE3,0x04,0x00,0x00,0x0A,0x1B,0x00,0x50,0xE3,0x02,0x00,0x00,0x0A,
0x2C,0x00,0x9F,0xE5,0x30,0x00,0x81,0xE5,0x01,0x00,0x00,0xEA,0x24,0x00,0x9F,0xE5,
0x30,0x00,0x81,0xE5,0x20,0xD0,0x9F,0xE5,0x20,0x00,0x9F,0xE5,0x00,0x10,0x90,0xE5,
0x1C,0x20,0x9F,0xE5,0x00,0x10,0x82,0xE5,0x06,0x00,0x00,0xEA,0x74,0x1F,0x00,0x00,
0x00,0x20,0x00,0x80,0x12,0x09,0x00,0x00,0xE7,0x3A,0x07,0x14,0x00,0x20,0x00,0x04,
0x04,0x00,0x00,0x00,0xFC,0xFF,0x00,0x00,0xC4,0x80,0x8F,0xE2,0x03,0x00,0x98,0xE8,
0x08,0x00,0x80,0xE0,0x08,0x10,0x81,0xE0,0x01,0xB0,0x40,0xE2,0x01,0x00,0x50,0xE1,
0x13,0x00,0x00,0x0A,0x70,0x00,0xB0,0xE8,0x05,0x00,0x54,0xE1,0xFA,0xFF,0xFF,0x0A,
0x01,0x00,0x14,0xE3,0x0B,0x40,0x84,0x10,0x01,0x00,0x15,0xE3,0x0B,0x50,0x85,0x10,
0x02,0x00,0x15,0xE3,0x09,0x50,0x85,0x10,0x03,0x50,0xC5,0xE3,0x10,0x60,0x56,0xE2,
0x8C,0x10,0xB4,0x28,0x8C,0x10,0xA5,0x28,0xFB,0xFF,0xFF,0x8A,0x86,0x6E,0xB0,0xE1,
0x0C,0x00,0xB4,0x28,0x0C,0x00,0xA5,0x28,0x04,0x70,0x94,0x44,0x04,0x70,0x85,0x44,
0xE9,0xFF,0xFF,0xEA,0x08,0x20,0x98,0xE5,0x0C,0x30,0x98,0xE5,0x08,0x20,0x82,0xE0,
0x08,0x30,0x83,0xE0,0x01,0xC0,0x42,0xE2,0x00,0x70,0xA0,0xE3,0x00,0x00,0xA0,0xE3,
0x00,0x60,0xA0,0xE3,0x00,0xB0,0xA0,0xE3,0x03,0x00,0x52,0xE1,0x10,0x00,0x00,0x0B,
0x30,0x00,0xB2,0xE8,0x01,0x00,0x14,0xE3,0x0C,0x40,0x84,0x10,0x02,0x00,0x14,0xE3,
0x09,0x40,0x84,0x10,0x03,0x40,0xC4,0xE3,0x10,0x50,0x55,0xE2,0xC1,0x08,0xA4,0x28,
0xFC,0xFF,0xFF,0x8A,0x85,0x5E,0xB0,0xE1,0x41,0x00,0xA4,0x28,0x04,0x70,0x84,0x44,
0xF0,0xFF,0xFF,0xEA,0x18,0x00,0x00,0x00,0x3C,0x00,0x00,0x00,0x3C,0x00,0x00,0x00,
0x54,0x00,0x00,0x00,0x04,0xF0,0x1F,0xE5,0x80,0x01,0x00,0xC0,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA8,0x01,0x00,0x00,0x00,0x00,0x00,0xC0,
0x3C,0x06,0x00,0x00,0xE4,0x07,0x00,0x00,0x00,0x08,0x00,0xC0,0x78,0x00,0x00,0x00,
0xA8,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x3C,0x06,0x00,0xC0,0x00,0x00,0x00,0x00,
0x78,0x08,0x00,0xC0,0x70,0x00,0x00,0x00,0x70,0x47,0x70,0x47,0x00,0x47,0x08,0x47,
0x10,0x47,0x18,0x47,0x20,0x47,0x28,0x47,0x30,0x47,0x38,0x47,0x78,0x47,0x00,0x00,
0x03,0x00,0x52,0xE3,0x83,0x00,0x00,0x9A,0x03,0xC0,0x10,0xE2,0x08,0x00,0x00,0x0A,
0x01,0x30,0xD1,0xE4,0x02,0x00,0x5C,0xE3,0x0C,0x20,0x82,0xE0,0x01,0xC0,0xD1,0x94,
0x01,0x30,0xC0,0xE4,0x01,0x30,0xD1,0x34,0x04,0x20,0x42,0xE2,0x01,0xC0,0xC0,0x94,
0x01,0x30,0xC0,0x34,0x03,0x30,0x11,0xE2,0x63,0x00,0x00,0x0A,0x04,0x20,0x52,0xE2,
0x74,0x00,0x00,0x3A,0x03,0xC0,0x31,0xE7,0x02,0x00,0x53,0xE3,0x08,0x00,0x00,0x0A,
0x0F,0x00,0x00,0x8A,0x2C,0x34,0xA0,0xE1,0x04,0xC0,0xB1,0xE5,0x04,0x20,0x52,0xE2,
0x0C,0x3C,0x83,0xE1,0x04,0x30,0x80,0xE4,0xF9,0xFF,0xFF,0x2A,0x01,0x10,0x81,0xE2,
0x68,0x00,0x00,0xEA,0x2C,0x38,0xA0,0xE1,0x04,0xC0,0xB1,0xE5,0x04,0x20,0x52,0xE2,
0x0C,0x38,0x83,0xE1,0x04,0x30,0x80,0xE4,0xF9,0xFF,0xFF,0x2A,0x02,0x10,0x81,0xE2,
0x60,0x00,0x00,0xEA,0x2C,0x3C,0xA0,0xE1,0x04,0xC0,0xB1,0xE5,0x04,0x20,0x52,0xE2,
0x0C,0x34,0x83,0xE1,0x04,0x30,0x80,0xE4,0xF9,0xFF,0xFF,0x2A,0x03,0x10,0x81,0xE2,
0x58,0x00,0x00,0xEA,0x78,0x47,0x00,0x00,0x1E,0xFF,0x2F,0xE1,0x78,0x47,0x00,0x00,
0x0E,0x50,0xA0,0xE1,0x3C,0x00,0x00,0xEB,0x05,0xE0,0xA0,0xE1,0x00,0x40,0xA0,0xE1,
0x0D,0x10,0xA0,0xE1,0x0A,0x30,0xA0,0xE1,0x07,0x00,0xC0,0xE3,0x60,0xD0,0x80,0xE2,
0x10,0x40,0x2D,0xE9,0xF0,0x00,0x00,0xEB,0x10,0x40,0xBD,0xE8,0x07,0xD0,0xC1,0xE3,
0x00,0x60,0xA0,0xE3,0x00,0x70,0xA0,0xE3,0x00,0x80,0xA0,0xE3,0x00,0xB0,0xA0,0xE3,
0x04,0xC0,0xA0,0xE1,0xC0,0x09,0xAC,0xE8,0xC0,0x09,0xAC,0xE8,0xC0,0x09,0xAC,0xE8,
0xC0,0x09,0xAC,0xE8,0x1F,0x40,0x2D,0xE9,0x00,0x00,0xA0,0xE3,0x00,0x10,0xA0,0xE3,
0xFF,0xFF,0xFF,0xEB,0x40,0x10,0x81,0xE2,0x01,0x60,0x80,0xE0,0x44,0x6F,0x86,0xE2,
0x1C,0x60,0x84,0xE5,0x18,0x10,0x84,0xE5,0x01,0x00,0xA0,0xE3,0x14,0x00,0x84,0xE5,
0x1F,0x40,0xBD,0xE8,0x02,0x10,0xA0,0xE1,0x1E,0xFF,0x2F,0xE1,0x78,0x47,0x00,0x00,
0x10,0x40,0x2D,0xE9,0x00,0x20,0xA0,0xE1,0x00,0x00,0xA0,0xE3,0xFF,0xFF,0xFF,0xEB,
0x10,0x40,0xBD,0xE8,0x1E,0xFF,0x2F,0xE1,0xD4,0xFF,0xFF,0xEB,0x36,0x00,0x00,0xFA,
0x1C,0xC0,0x9F,0xE5,0x0F,0xC0,0x8C,0xE0,0x01,0x00,0x1C,0xE3,0x0D,0xE0,0x8F,0x12,
0x0F,0xE0,0xA0,0x01,0x1C,0xFF,0x2F,0xE1,0x01,0xC0,0x8F,0xE2,0x1C,0xFF,0x2F,0xE1,
0x00,0xF0,0x52,0xF8,0xC5,0x03,0x00,0x00,0x78,0x47,0x00,0x00,0x01,0x40,0x2D,0xE9,
0x50,0x00,0x00,0xFB,0x01,0x40,0xBD,0xE8,0x01,0x00,0x00,0xEA,0x78,0x47,0x00,0x00,
0x00,0x00,0xE0,0xE3,0x53,0x00,0x00,0xEA,0x78,0x47,0x00,0x00,0x00,0x00,0x9F,0xE5,
0x1E,0xFF,0x2F,0xE1,0x88,0x08,0x00,0xC0,0x78,0x47,0x00,0x00,0x10,0x40,0x2D,0xE9,
0x20,0x20,0x52,0xE2,0x05,0x00,0x00,0x3A,0x18,0x50,0xB1,0x28,0x18,0x50,0xA0,0x28,
0x18,0x50,0xB1,0x28,0x18,0x50,0xA0,0x28,0x20,0x20,0x52,0x22,0xF9,0xFF,0xFF,0x2A,
0x02,0xCE,0xB0,0xE1,0x18,0x50,0xB1,0x28,0x18,0x50,0xA0,0x28,0x18,0x00,0xB1,0x48,
0x18,0x00,0xA0,0x48,0x10,0x40,0xBD,0xE8,0x02,0xCF,0xB0,0xE1,0x04,0x30,0x91,0x24,
0x04,0x30,0x80,0x24,0x1E,0xFF,0x2F,0x01,0x82,0x2F,0xB0,0xE1,0x01,0x20,0xD1,0x44,
0x01,0x30,0xD1,0x24,0x01,0xC0,0xD1,0x24,0x01,0x20,0xC0,0x44,0x01,0x30,0xC0,0x24,
0x01,0xC0,0xC0,0x24,0x1E,0xFF,0x2F,0xE1,0x10,0xB5,0x04,0x1C,0x00,0xF0,0x00,0xF8,
0x20,0x1C,0xFF,0xF7,0xAC,0xEF,0x10,0xBC,0x08,0xBC,0x18,0x47,0xF0,0xB5,0x04,0x1C,
0x0D,0x1C,0x83,0xB0,0x00,0xF0,0xDA,0xE9,0x00,0x94,0x01,0x95,0x00,0x20,0x00,0xF0,
0x00,0xF8,0x02,0x90,0x26,0x48,0x69,0x46,0x78,0x44,0x00,0xF0,0x00,0xF8,0x05,0x1C,
0x0E,0x1C,0x00,0xA9,0x03,0xC9,0x00,0xF0,0x00,0xF8,0x00,0xF0,0x00,0xF8,0x00,0xF0,
0x00,0xF8,0x00,0x21,0x00,0x20,0x00,0xF0,0x00,0xF8,0x07,0x1C,0xFF,0xF7,0x96,0xEF,
0x04,0x1C,0x00,0x21,0x07,0x62,0x00,0x20,0x00,0xF0,0x00,0xF8,0x41,0x1C,0x61,0x62,
0x00,0x21,0x00,0x20,0x00,0xF0,0x00,0xF8,0x00,0x21,0xA0,0x62,0x00,0x20,0x00,0xF0,
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0x00,0x47,0x00,0x00,0xFE,0xB5,0x00,0x20,0x02,0x90,0x01,0x90,0x4D,0x48,0x01,0x26,
0xC0,0x6B,0x05,0x28,0x19,0xD2,0x02,0xA3,0x1B,0x5C,0x5B,0x00,0x9F,0x44,0x00,0x00,
0x03,0x04,0x04,0x04,0x04,0x00,0x00,0x26,0x47,0x4A,0x00,0x21,0x11,0x60,0x84,0x00,
0x46,0x48,0x51,0x60,0x91,0x60,0x46,0x4D,0x01,0x59,0x28,0x1C,0xFF,0xF7,0x37,0xFE,
0x44,0x48,0x00,0x59,0xFF,0xF7,0x32,0xFE,0x00,0xE0,0xFE,0xE7,0x01,0x98,0x00,0x28,
0x09,0xD0,0x41,0x48,0x80,0x69,0x00,0x0C,0x00,0x02,0x10,0x21,0x08,0x43,0x05,0x1C,
0x00,0x20,0x01,0x90,0x00,0xE0,0x10,0x25,0x3C,0x4F,0x28,0x1C,0x39,0x59,0xFF,0xF7,
0x1E,0xFE,0x00,0x2E,0x04,0xD0,0x3A,0x48,0x00,0x59,0xFF,0xF7,0x17,0xFE,0x00,0x26,
0x00,0x20,0x00,0x90,0x37,0x48,0x00,0x59,0xFF,0xF7,0x10,0xFE,0x30,0x48,0x2E,0x4F,
0x0F,0xC8,0x0F,0xC7,0x10,0x3F,0x38,0x68,0x01,0x28,0x0F,0xD0,0x04,0x28,0x0D,0xD0,
0x01,0x20,0x2E,0x4F,0x05,0x43,0x28,0x1C,0x39,0x59,0xFF,0xF7,0x00,0xFE,0x2C,0x48,
0x00,0x59,0xFF,0xF7,0xFB,0xFD,0x00,0x98,0x00,0x28,0xE3,0xD0,0x22,0x48,0x00,0x68,
0x01,0x28,0x18,0xD0,0x04,0x28,0x0C,0xD1,0x24,0x4F,0x00,0x20,0x39,0x59,0xFF,0xF7,
0xEE,0xFD,0x23,0x48,0x00,0x59,0xFF,0xF7,0xE9,0xFD,0x1B,0x48,0x40,0x68,0xFF,0xF7,
0x8F,0xFF,0x19,0x49,0x00,0x20,0x08,0x60,0x48,0x60,0x88,0x60,0xC8,0x60,0x02,0x98,
0x00,0x28,0xAB,0xD0,0xFE,0xBD,0x19,0x4F,0x13,0x48,0x39,0x59,0x85,0x68,0x28,0x1C,
0xFF,0xF7,0xD5,0xFD,0x16,0x48,0x00,0x59,0xFF,0xF7,0xD0,0xFD,0x00,0x20,0x00,0x90,
0x14,0x48,0x00,0x59,0xFF,0xF7,0xCA,0xFD,0x13,0x48,0x00,0x59,0xFF,0xF7,0xC6,0xFD,
0x00,0x28,0x01,0xD1,0x01,0x26,0xDC,0xE7,0x01,0x20,0x05,0x43,0x28,0x1C,0x39,0x59,
0xFF,0xF7,0xBD,0xFD,0x0A,0x48,0x00,0x59,0xFF,0xF7,0xB8,0xFD,0x00,0x98,0x00,0x28,
0xCF,0xD1,0xE5,0xE7,0xC0,0xFF,0x00,0x00,0x78,0x08,0x00,0xC0,0x14,0x08,0x00,0xC0,
0x00,0x0A,0x00,0xC0,0x00,0x08,0x00,0xC0,0x00,0x20,0x00,0x80,0x64,0x08,0x00,0xC0,
0x3C,0x08,0x00,0xC0,0x28,0x08,0x00,0xC0,0x50,0x08,0x00,0xC0,0x04,0x00,0x9F,0xE5,
0x40,0x1D,0x80,0xE2,0x0E,0xF0,0xA0,0xE1,0x00,0x10,0x00,0x04,0x01,0x49,0x05,0x20,
0x48,0x61,0x70,0x47,0x00,0x0C,0x00,0x80,0x70,0x47,0x00,0x00,0x00,0x20,0x70,0x47,
0x70,0x47,0x00,0x00,0x70,0x47,0x00,0x00,0x70,0x47,0x00,0x00,0x03,0x48,0x04,0x49,
0x08,0x80,0x40,0x07,0x41,0x88,0x41,0x80,0x70,0x47,0x00,0x00,0x04,0x80,0x00,0x00,
0x20,0x00,0x00,0x80,0x01,0x21,0xC9,0x07,0x48,0x88,0x40,0x07,0xFC,0xD5,0x70,0x47,
0x02,0x49,0x03,0x48,0x01,0x80,0x8F,0x21,0xC1,0x83,0x70,0x47,0x04,0x80,0x00,0x00,
0x20,0x00,0x00,0x80,0x01,0x21,0xC9,0x07,0x88,0x62,0x70,0x47,0x01,0x21,0xC9,0x07,
0x88,0x63,0x70,0x47,0x05,0x4A,0x80,0xB5,0x12,0x1D,0x05,0xCA,0x02,0x49,0x04,0x3A,
0xFF,0xF7,0x66,0xED,0x00,0x20,0x80,0xBD,0x00,0x0A,0x00,0xC0,0x78,0x08,0x00,0xC0,
0x80,0xB5,0xFF,0xF7,0xFF,0xFE,0x00,0x20,0x80,0xBD,0x00,0x00,0x04,0x21,0x48,0x07,
0x41,0x63,0x00,0x21,0x41,0x62,0x70,0x47,0x01,0x21,0xC9,0x07,0x48,0x6A,0x40,0x07,
0xFC,0xD5,0x70,0x47,0x01,0x21,0xC8,0x07,0x01,0x62,0x04,0x21,0x41,0x63,0x70,0x47,
0x01,0x21,0xC9,0x07,0x88,0x81,0x70,0x47,0x01,0x21,0xC9,0x07,0xC8,0x63,0x70,0x47,
0x02,0x48,0x00,0x21,0x01,0x81,0x0D,0x21,0x01,0x80,0x70,0x47,0x20,0x01,0x00,0x80,
0x02,0x49,0x08,0x89,0xC0,0x07,0xFC,0xD5,0x70,0x47,0x00,0x00,0x20,0x01,0x00,0x80,
0x03,0x48,0x0D,0x21,0x01,0x80,0x00,0x21,0x81,0x81,0x01,0x21,0x81,0x80,0x70,0x47,
0x20,0x01,0x00,0x80,0x01,0x49,0x08,0x61,0x70,0x47,0x00,0x00,0x00,0x01,0x00,0x80,
0x01,0x49,0x48,0x61,0x70,0x47,0x00,0x00,0x00,0x01,0x00,0x80,0x01,0x49,0x04,0x20,
0x08,0x83,0x70,0x47,0x40,0x00,0x00,0x80,0x03,0x49,0x08,0x89,0x40,0x07,0xFC,0xD5,
0x00,0x20,0x08,0x81,0x70,0x47,0x00,0x00,0x40,0x00,0x00,0x80,0x01,0x49,0x04,0x20,
0x08,0x83,0x70,0x47,0x40,0x00,0x00,0x80,0x01,0x21,0xC9,0x07,0x88,0x62,0x70,0x47,
0x01,0x21,0xC9,0x07,0x48,0x61,0x70,0x47,0x78,0x47,0x00,0x00,0x10,0x40,0x2D,0xE9,
0x45,0xFF,0xFF,0xEB,0x00,0x10,0xA0,0xE3,0x00,0x10,0x80,0xE5,0x10,0x40,0xBD,0xE8,
0x1E,0xFF,0x2F,0xE1,0x19,0x05,0x00,0xC0,0xE9,0x04,0x00,0xC0,0xB9,0x05,0x00,0xC0,
0x05,0x06,0x00,0xC0,0x7D,0x05,0x00,0xC0,0x35,0x05,0x00,0xC0,0xF1,0x04,0x00,0xC0,
0xD9,0x05,0x00,0xC0,0x19,0x06,0x00,0xC0,0x91,0x05,0x00,0xC0,0x0D,0x05,0x00,0xC0,
0xE1,0x04,0x00,0xC0,0xA9,0x05,0x00,0xC0,0xF1,0x05,0x00,0xC0,0x71,0x05,0x00,0xC0,
0xF5,0x04,0x00,0xC0,0xD5,0x04,0x00,0xC0,0x99,0x05,0x00,0xC0,0xE5,0x05,0x00,0xC0,
0x65,0x05,0x00,0xC0,0x3D,0x05,0x00,0xC0,0xE5,0x04,0x00,0xC0,0x3D,0x05,0x00,0xC0,
0x3D,0x05,0x00,0xC0,0x3D,0x05,0x00,0xC0,0x2D,0x05,0x00,0xC0,0xED,0x04,0x00,0xC0,
0xCD,0x05,0x00,0xC0,0x11,0x06,0x00,0xC0,0x89,0x05,0x00,0xC0};
wifi/wlan/host.h 已删除 100644 → 0
浏览文件 @ b29605dc
/** @file host.h
*
* @brief This file contains definitions of WLAN commands.
*
* Copyright Marvell International Ltd. and/or its affiliates, 2003-2007
*/
/********************************************************
Change log:
10/11/05: Add Doxygen format comments
01/11/06: Remove assoc response codes; full IEEE assoc resp now returned
04/06/06: Add TSPEC, queue metrics, and MSDU expiry support
04/10/06: Add power_adapt_cfg_ext command
04/18/06: Remove old Subscrive Event and add new Subscribe Event
implementation through generic hostcmd API
05/03/06: Add auto_tx hostcmd
05/04/06: Add IBSS coalescing related new hostcmd and event
08/28/06: Add LED_CTRL hostcmd
********************************************************/
#ifndef _HOST_H_
#define _HOST_H_
/** PUBLIC DEFINITIONS */
#define DEFAULT_AD_HOC_CHANNEL 6
#define DEFAULT_AD_HOC_CHANNEL_A 36
/** IEEE 802.11 OIDs */
#define OID_802_11_INFRASTRUCTURE_MODE 0x00008001
#define OID_802_11_FRAGMENTATION_THRESHOLD 0x00008002
#define OID_802_11_RTS_THRESHOLD 0x00008003
#define OID_802_11_ADD_WEP 0x00008004
#define OID_802_11_REMOVE_WEP 0x00008005
#define OID_802_11_TX_RETRYCOUNT 0x00008006
#define OID_802_11D_ENABLE 0x00008007
#define HostCmd_OPTION_WAITFORRSP 0x0002
/** Host Command ID */
#define HostCmd_CMD_GET_HW_SPEC 0x0003
#define HostCmd_CMD_802_11_RESET 0x0005
#define HostCmd_CMD_802_11_SCAN 0x0006
#define HostCmd_CMD_802_11_GET_LOG 0x000b
#define HostCmd_CMD_MAC_MULTICAST_ADR 0x0010
#define HostCmd_CMD_802_11_EEPROM_ACCESS 0x0059
#define HostCmd_CMD_802_11_ASSOCIATE 0x0012
#define HostCmd_CMD_802_11_SET_WEP 0x0013
#define HostCmd_CMD_802_11_SNMP_MIB 0x0016
#define HostCmd_CMD_MAC_REG_ACCESS 0x0019
#define HostCmd_CMD_BBP_REG_ACCESS 0x001a
#define HostCmd_CMD_RF_REG_ACCESS 0x001b
#define HostCmd_CMD_802_11_RADIO_CONTROL 0x001c
#define HostCmd_CMD_802_11_RF_CHANNEL 0x001d
#define HostCmd_CMD_802_11_RF_TX_POWER 0x001e
#define HostCmd_CMD_802_11_RSSI 0x001f
#define HostCmd_CMD_802_11_RF_ANTENNA 0x0020
#define HostCmd_CMD_802_11_PS_MODE 0x0021
#define HostCmd_CMD_802_11_DEAUTHENTICATE 0x0024
#define HostCmd_CMD_MAC_CONTROL 0x0028
#define HostCmd_CMD_802_11_AD_HOC_START 0x002b
#define HostCmd_CMD_802_11_AD_HOC_JOIN 0x002c
#define HostCmd_CMD_802_11_KEY_MATERIAL 0x005e
#define HostCmd_CMD_802_11_DEEP_SLEEP 0x003e
#define HostCmd_CMD_802_11_AD_HOC_STOP 0x0040
#define HostCmd_CMD_802_11_HOST_SLEEP_CFG 0x0043
#define HostCmd_CMD_802_11_WAKEUP_CONFIRM 0x0044
#define HostCmd_CMD_802_11_MAC_ADDRESS 0x004D
#define HostCmd_CMD_802_11_EEPROM_ACCESS 0x0059
#define HostCmd_CMD_GSPI_BUS_CONFIG 0x005A
#define HostCmd_CMD_802_11_BAND_CONFIG 0x0058
#define HostCmd_CMD_802_11D_DOMAIN_INFO 0x005b
#define HostCmd_CMD_802_11_SLEEP_PARAMS 0x0066
#define HostCmd_CMD_802_11_INACTIVITY_TIMEOUT 0x0067
#define HostCmd_CMD_802_11_SLEEP_PERIOD 0x0068
#define HostCmd_CMD_802_11_BCA_CONFIG_TIMESHARE 0x0069
#define HostCmd_CMD_802_11_BG_SCAN_CONFIG 0x006b
#define HostCmd_CMD_802_11_BG_SCAN_QUERY 0x006c
#define HostCmd_CMD_802_11_CAL_DATA_EXT 0x006d
#define HostCmd_CMD_WMM_ADDTS_REQ 0x006E
#define HostCmd_CMD_WMM_DELTS_REQ 0x006F
#define HostCmd_CMD_WMM_QUEUE_CONFIG 0x0070
#define HostCmd_CMD_WMM_GET_STATUS 0x0071
#define HostCmd_CMD_802_11_TPC_CFG 0x0072
#define HostCmd_CMD_802_11_FW_WAKE_METHOD 0x0074
#define HostCmd_CMD_802_11_LED_CONTROL 0x004e
#define HostCmd_CMD_802_11_SUBSCRIBE_EVENT 0x0075
#define HostCmd_CMD_802_11_RATE_ADAPT_RATESET 0x0076
#define HostCmd_CMD_802_11_CRYPTO 0x0078
#define HostCmd_CMD_802_11_TX_RATE_QUERY 0x007f
#define HostCmd_CMD_802_11_POWER_ADAPT_CFG_EXT 0x007e
#define HostCmd_CMD_GET_TSF 0x0080
#define HostCmd_CMD_WMM_QUEUE_STATS 0x0081
#define HostCmd_CMD_802_11_AUTO_TX 0x0082
#define HostCmd_CMD_802_11_IBSS_COALESCING_STATUS 0x0083
#define HostCmd_CMD_MEM_ACCESS 0x0086
#ifdef MFG_CMD_SUPPORT
#define HostCmd_CMD_MFG_COMMAND 0x0089
#define HostCmd_RET_MFG_COMMAND 0x8089
#endif
#define HostCmd_CMD_TX_PKT_STATS 0x008d
#define HostCmd_CMD_802_11_LDO_CONFIG 0x0096
#define HostCmd_CMD_VERSION_EXT 0x0097
/* For the IEEE Power Save */
#define HostCmd_SubCmd_Enter_PS 0x0030
#define HostCmd_SubCmd_Exit_PS 0x0031
#define HostCmd_SubCmd_Sleep_Confirmed 0x0034
#define HostCmd_SubCmd_Full_PowerDown 0x0035
#define HostCmd_SubCmd_Full_PowerUp 0x0036
/* Command RET code, MSB is set to 1 */
#define HostCmd_RET_HW_SPEC_INFO 0x8003
#define HostCmd_RET_802_11_RESET 0x8005
#define HostCmd_RET_802_11_SCAN 0x8006
#define HostCmd_RET_802_11_GET_LOG 0x800b
#define HostCmd_RET_MAC_CONTROL 0x8028
#define HostCmd_RET_MAC_MULTICAST_ADR 0x8010
#define HostCmd_RET_802_11_DEAUTHENTICATE 0x8024
#define HostCmd_RET_802_11_ASSOCIATE 0x8012
#define HostCmd_RET_802_11_SET_WEP 0x8013
#define HostCmd_RET_802_3_STAT 0x8015
#define HostCmd_RET_802_11_SNMP_MIB 0x8016
#define HostCmd_RET_MAC_REG_ACCESS 0x8019
#define HostCmd_RET_BBP_REG_ACCESS 0x801a
#define HostCmd_RET_RF_REG_ACCESS 0x801b
#define HostCmd_RET_802_11_RADIO_CONTROL 0x801c
#define HostCmd_RET_802_11_RF_CHANNEL 0x801d
#define HostCmd_RET_802_11_RSSI 0x801f
#define HostCmd_RET_802_11_RF_TX_POWER 0x801e
#define HostCmd_RET_802_11_RF_ANTENNA 0x8020
#define HostCmd_RET_802_11_PS_MODE 0x8021
#define HostCmd_RET_802_11_AD_HOC_START 0x802B
#define HostCmd_RET_802_11_AD_HOC_JOIN 0x802C
#define HostCmd_RET_802_11_KEY_MATERIAL 0x805e
#define HostCmd_ACT_SET 0x0001
#define HostCmd_ACT_GET 0x0000
#define HostCmd_RET_802_11_AD_HOC_STOP 0x8040
#define HostCmd_RET_802_11_HOST_SLEEP_CFG 0x8043
#define HostCmd_RET_802_11_WAKEUP_CONFIRM 0x8044
#define HostCmd_RET_802_11_MAC_ADDRESS 0x804D
#define HostCmd_RET_802_11_EEPROM_ACCESS 0x8059
#define HostCmd_RET_CMD_GSPI_BUS_CONFIG 0x805A
#define HostCmd_RET_802_11_BAND_CONFIG 0x8058
#define HostCmd_RET_802_11_SLEEP_PARAMS 0x8066
#define HostCmd_RET_802_11_INACTIVITY_TIMEOUT 0x8067
#define HostCmd_RET_802_11_SLEEP_PERIOD 0x8068
#define HostCmd_RET_802_11_BCA_CONFIG_TIMESHARE 0x8069
#define HostCmd_RET_802_11D_DOMAIN_INFO 0x805B
#define HostCmd_RET_802_11_BG_SCAN_CONFIG 0x806b
#define HostCmd_RET_802_11_BG_SCAN_QUERY 0x806c
#define HostCmd_RET_802_11_CAL_DATA_EXT 0x806d
#define HostCmd_RET_WMM_ADDTS_REQ 0x806E
#define HostCmd_RET_WMM_DELTS_REQ 0x806F
#define HostCmd_RET_WMM_QUEUE_CONFIG 0x8070
#define HostCmd_RET_WMM_GET_STATUS 0x8071
#define HostCmd_RET_802_11_TPC_CFG 0x8072
#define HostCmd_RET_802_11_LED_CONTROL 0x804e
#define HostCmd_RET_802_11_FW_WAKE_METHOD 0x8074
#define HostCmd_RET_802_11_SUBSCRIBE_EVENT 0x8075
#define HostCmd_RET_802_11_RATE_ADAPT_RATESET 0x8076
#define HostCmd_RET_802_11_CRYPTO 0x8078
#define HostCmd_RTE_802_11_TX_RATE_QUERY 0x807f
#define HostCmd_RET_GET_TSF 0x8080
#define HostCmd_RET_WMM_QUEUE_STATS 0x8081
#define HostCmd_RET_802_11_POWER_ADAPT_CFG_EXT 0x807e
#define HostCmd_RET_802_11_AUTO_TX 0x8082
#define HostCmd_RET_802_11_IBSS_COALESCING_STATUS 0x8083
#define HostCmd_RET_MEM_ACCESS 0x8086
#define HostCmd_RET_802_11_LDO_CONFIG 0x8096
#define HostCmd_RET_VERSION_EXT 0x8097
/** General Result Code*/
/* OK */
#define HostCmd_RESULT_OK 0x0000
/* Genenral error */
#define HostCmd_RESULT_ERROR 0x0001
/* Command is not valid */
#define HostCmd_RESULT_NOT_SUPPORT 0x0002
/* Command is pending */
#define HostCmd_RESULT_PENDING 0x0003
/* System is busy (command ignored) */
#define HostCmd_RESULT_BUSY 0x0004
/* Data buffer is not big enough */
#define HostCmd_RESULT_PARTIAL_DATA 0x0005
/* Definition of action or option for each command */
/* Define general purpose action */
#define HostCmd_ACT_GEN_READ 0x0000
#define HostCmd_ACT_GEN_WRITE 0x0001
#define HostCmd_ACT_GEN_GET 0x0000
#define HostCmd_ACT_GEN_SET 0x0001
#define HostCmd_ACT_GEN_REMOVE 0x0002
#define HostCmd_ACT_GEN_OFF 0x0000
#define HostCmd_ACT_GEN_ON 0x0001
/* Define action or option for HostCmd_CMD_802_11_SET_WEP */
#define HostCmd_ACT_ADD 0x0002
#define HostCmd_ACT_REMOVE 0x0004
#define HostCmd_TYPE_WEP_40_BIT 0x0001
#define HostCmd_TYPE_WEP_104_BIT 0x0002
#define HostCmd_WEP_KEY_INDEX_MASK 0x3fff
/* Define action or option for HostCmd_CMD_802_11_SCAN */
#define HostCmd_BSS_TYPE_BSS 0x0001
#define HostCmd_BSS_TYPE_IBSS 0x0002
#define HostCmd_BSS_TYPE_ANY 0x0003
/* Define action or option for HostCmd_CMD_802_11_SCAN */
#define HostCmd_SCAN_TYPE_ACTIVE 0x0000
#define HostCmd_SCAN_TYPE_PASSIVE 0x0001
/* Radio type definitions for the channel TLV */
#define HostCmd_SCAN_RADIO_TYPE_BG 0
#define HostCmd_SCAN_RADIO_TYPE_A 1
/* Define action or option for HostCmd_CMD_MAC_CONTROL */
#define HostCmd_ACT_MAC_RX_ON 0x0001
#define HostCmd_ACT_MAC_TX_ON 0x0002
#define HostCmd_ACT_MAC_LOOPBACK_ON 0x0004
#define HostCmd_ACT_MAC_WEP_ENABLE 0x0008
#define HostCmd_ACT_MAC_ETHERNETII_ENABLE 0x0010
#define HostCmd_ACT_MAC_PROMISCUOUS_ENABLE 0x0080
#define HostCmd_ACT_MAC_ALL_MULTICAST_ENABLE 0x0100
#define HostCmd_ACT_MAC_STRICT_PROTECTION_ENABLE 0x0400
#define HostCmd_ACT_MAC_ADHOC_G_PROTECTION_ON 0x2000
/* Define action or option or constant for HostCmd_CMD_MAC_MULTICAST_ADR */
#define HostCmd_SIZE_MAC_ADR 6
#define HostCmd_MAX_MCAST_ADRS 32
#define RADIO_ON 0x01
#define RADIO_OFF 0x00
/* Define action or option for CMD_802_11_RF_CHANNEL */
#define HostCmd_OPT_802_11_RF_CHANNEL_GET 0x00
#define HostCmd_OPT_802_11_RF_CHANNEL_SET 0x01
#define HostCmd_ACT_SET_RX 0x0001
#define HostCmd_ACT_SET_TX 0x0002
#define HostCmd_ACT_SET_BOTH 0x0003
#define HostCmd_ACT_GET_RX 0x0004
#define HostCmd_ACT_GET_TX 0x0008
#define HostCmd_ACT_GET_BOTH 0x000c
/** Card Event definition */
#define MACREG_INT_CODE_DUMMY_HOST_WAKEUP_SIGNAL 0x00000001
#define MACREG_INT_CODE_LINK_LOST_WITH_SCAN 0x00000002
#define MACREG_INT_CODE_LINK_LOST 0x00000003
#define MACREG_INT_CODE_LINK_SENSED 0x00000004
#define MACREG_INT_CODE_MIB_CHANGED 0x00000006
#define MACREG_INT_CODE_INIT_DONE 0x00000007
#define MACREG_INT_CODE_DEAUTHENTICATED 0x00000008
#define MACREG_INT_CODE_DISASSOCIATED 0x00000009
#define MACREG_INT_CODE_PS_AWAKE 0x0000000a
#define MACREG_INT_CODE_PS_SLEEP 0x0000000b
#define MACREG_INT_CODE_MIC_ERR_MULTICAST 0x0000000d
#define MACREG_INT_CODE_MIC_ERR_UNICAST 0x0000000e
#define MACREG_INT_CODE_WM_AWAKE 0x0000000f
#define MACREG_INT_CODE_DEEP_SLEEP_AWAKE 0x00000010
#define MACREG_INT_CODE_ADHOC_BCN_LOST 0x00000011
#define MACREG_INT_CODE_HOST_SLEEP_AWAKE 0x00000012
#define MACREG_INT_CODE_WMM_STATUS_CHANGE 0x00000017
#define MACREG_INT_CODE_BG_SCAN_REPORT 0x00000018
#define MACREG_INT_CODE_RSSI_LOW 0x00000019
#define MACREG_INT_CODE_SNR_LOW 0x0000001a
#define MACREG_INT_CODE_MAX_FAIL 0x0000001b
#define MACREG_INT_CODE_RSSI_HIGH 0x0000001c
#define MACREG_INT_CODE_SNR_HIGH 0x0000001d
#define MACREG_INT_CODE_IBSS_COALESCED 0x0000001e
/* Define bitmap conditions for HOST_SLEEP_CFG */
#define HOST_SLEEP_CFG_CANCEL 0xffffffff
#endif /* _HOST_H_ */
wifi/wlan/hostcmd.h 已删除 100644 → 0
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wifi/wlan/include.h 已删除 100644 → 0
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/** @file include.h
*
* @brief This file contains all the necessary include file.
*
* Copyright Marvell International Ltd. and/or its affiliates, 2003-2007
*/
/********************************************************
Change log:
10/11/05: Add Doxygen format comments
01/11/06: Conditional include file removal/addition
01/30/06: Add kernel 2.6 support
********************************************************/
#ifndef _INCLUDE_H_
#define _INCLUDE_H_
#include "..\os\os_headers.h"
#include "wlan_debug.h"
#include "wlan_types.h"
#include "wlan_defs.h"
#include "wlan_thread.h" //dennis
#include "wlan_wmm.h"
#include "wlan_11d.h"
#include "host.h"
#include "hostcmd.h"
#include "wlan_scan.h"
#include "wlan_join.h"
#include "wlan_dev.h"
#include "sbi.h"
#include "..\spi\gspi_io.h"
#include "wlan_wext.h"
#include "wlan_decl.h"
#endif /* _INCLUDE_H_ */
wifi/wlan/rt_wlan_dev.c 已删除 100644 → 0
浏览文件 @ b29605dc
#include <rtthread.h>
#include <netif/ethernetif.h>
#include "rt_wlan_dev.h"
#include "wlan_dev.h"
#include <rtthread.h>
#define WLAN_DEV 1
#if WLAN_DEV
#define DEV_TRACE rt_kprintf
#else
#define DEV_TRACE(...)
#endif
#define MAX_ADDR_LEN 6
static struct rt_wlan_dev wlan_eth;
extern int wlan_init_module(struct rt_wlan_dev * wlan_dev);
/* RT-Thread Device Interface */
/* initialize the interface */
static rt_err_t rt_wlan_dev_init(rt_device_t dev)
{
return RT_EOK;
}
static rt_err_t rt_wlan_dev_open(rt_device_t dev, rt_uint16_t oflag)
{
rt_err_t error=RT_EOK;
if(dev==RT_NULL||dev->user_data==RT_NULL)
{
error=-RT_EEMPTY;
goto done;
}
done:
return error;
}
static rt_err_t rt_wlan_dev_close(rt_device_t dev)
{
return RT_EOK;
}
static rt_size_t rt_wlan_dev_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
{
rt_set_errno(-RT_ENOSYS);
return 0;
}
static rt_size_t rt_wlan_dev_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
{
rt_set_errno(-RT_ENOSYS);
return 0;
}
rt_err_t rt_wlan_dev_control(rt_device_t dev, rt_uint8_t cmd, void *args)
{
rt_err_t error=RT_EOK;
struct rt_wlan_dev * wlan_dev;
wlan_private *priv = NULL;
struct WLAN_IO_CTRL_PAR * par;
char addressbuf[6]={0xff,0xff,0xff,0xff,0xff,0xff};
if(dev==RT_NULL||dev->user_data==RT_NULL)
{
error=-RT_EEMPTY;
goto done;
}
wlan_dev=dev->user_data;
priv=wlan_dev->priv;
switch (cmd)
{
case NIOCTL_GADDR:
/* get mac address */
//if (args) rt_memcpy(args, dm9000_device.dev_addr, 6);
//else return -RT_ERROR;
if(rt_memcmp(priv->adapter->CurrentAddr,addressbuf,6)==0)
{
error=-RT_ERROR;
break;
}
else{
rt_memcpy((u8*)args,priv->adapter->CurrentAddr,6);
}
break;
default :
break;
}
done:
return error;
}
/* ethernet device interface */
/* transmit packet. */
extern void
netif_set_addr(struct netif *netif, struct ip_addr *ipaddr, struct ip_addr *netmask,
struct ip_addr *gw);
int wlan_set_addr(rt_uint32_t ipaddr,rt_uint32_t mask,rt_uint32_t gwaddr)
{
struct ip_addr myip,gwip,maskip;
/* myip 192.168.1.66->C0,A8,1,42*/
myip.addr=ipaddr;
/*gwip 192.168.1.1->C0,A8,1,1 */
gwip.addr=gwaddr;
/*maskip255.255.255.0,FF,FF,FF,0*/
maskip.addr=mask;
netif_set_addr(wlan_eth.parent.netif,&myip,&maskip,&gwip);
}
extern rt_err_t rt_wlan_dev_tx( rt_device_t dev, struct pbuf* p);
extern struct pbuf *rt_wlan_dev_rx(rt_device_t dev);
int rt_hw_wlan_dev_init(void)
{
rt_int32_t value=0;
rt_err_t error=RT_EOK;
/*
* SRAM Tx/Rx pointer automatically return to start address,
* Packet Transmitted, Packet Received
*/
wlan_eth.parent.parent.init = rt_wlan_dev_init;
wlan_eth.parent.parent.open = rt_wlan_dev_open;
wlan_eth.parent.parent.close = rt_wlan_dev_close;
wlan_eth.parent.parent.read = rt_wlan_dev_read;
wlan_eth.parent.parent.write = rt_wlan_dev_write;
wlan_eth.parent.parent.control = rt_wlan_dev_control;
wlan_eth.parent.parent.user_data =(void *)&wlan_eth ;
wlan_eth.parent.eth_rx = rt_wlan_dev_rx;
wlan_eth.parent.eth_tx = rt_wlan_dev_tx;
value=gspihost_init();
if(value<0)
{
error=-RT_ERROR;
goto done;
}
value=wlan_init_module(&wlan_eth);
if(value<0)
{
error=-RT_ERROR;
goto done;
}
eth_device_init(&(wlan_eth.parent), "wlan_eth0");
done:
return error;
}
wifi/wlan/rt_wlan_dev.h 已删除 100644 → 0
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#ifndef __RT_WLAN_DEV_H__
#define __RT_WLAN_DEV_H__
#include <netif/ethernetif.h>
#include "lwipopts.h"
#include "wlan_types.h"
#define WLANMACADDRESSLENGTH (6)
//#define CMD
struct WLAN_IO_CTRL_PAR
{
/** parameters Header */
u16 inputlength;
u16 outputlength;
/** Command Body */
union
{
u8 MacAdd[MRVDRV_ETH_ADDR_LEN];
} params;
};
struct rt_wlan_dev
{
/* inherit from ethernet device */
struct eth_device parent;
void * priv ;
unsigned int irq;
char name[16];
char dev_addr[6];
};
int rt_hw_wlan_dev_init(void);
#endif
wifi/wlan/sbi.h 已删除 100644 → 0
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/** @file sbi.h
*
* @brief This file contains IF layer definitions.
*
* Copyright Marvell International Ltd. and/or its affiliates, 2003-2006
*/
/********************************************************
Change log:
10/11/05: Add Doxygen format comments
01/05/06: Add kernel 2.6.x support
********************************************************/
#ifndef _SBI_H_
#define _SBI_H_
/**Bit Definition*/
#define B_BIT_0 0x01
#define B_BIT_1 0x02
#define B_BIT_2 0x04
#define B_BIT_3 0x08
#define B_BIT_4 0x10
#define B_BIT_5 0x20
#define B_BIT_6 0x40
#define B_BIT_7 0x80
#define B_BIT_8 0x100
#define B_BIT_9 0X200
#define B_BIT_10 0x400
/** INT Status Bit Definition*/
#define HIS_RxUpLdRdy B_BIT_0
#define HIS_TxDnLdRdy B_BIT_1
#define HIS_CmdDnLdRdy B_BIT_2
#define HIS_CardEvent B_BIT_3
#define HIS_CmdUpLdRdy B_BIT_4
#define HIS_WrFifoOvrflow B_BIT_5
#define HIS_RdFifoUndrflow B_BIT_6
#define HIS_WlanReady B_BIT_7
#define HIM_DISABLE 0xff
#define HIM_ENABLE 0x03
#define FIRMWARE_READY 0xfedc
#ifndef DEV_NAME_LEN
#define DEV_NAME_LEN 32
#endif
#define MAXKEYLEN 13
/* The number of times to try when polling for status bits */
#define MAX_POLL_TRIES 100
/* The number of times to try when waiting for downloaded firmware to
become active. (polling the scratch register). */
#define MAX_FIRMWARE_POLL_TRIES 100
#define FIRMWARE_TRANSFER_NBLOCK 2
#define SBI_EVENT_CAUSE_SHIFT 3
#define GSPI_BUS_DELAY_TIME_MODE 1
#define GSPI_BUS_DELAY_CLK_MODE 0
typedef enum _mv_sd_type
{
MVSD_DAT = 0,
MVSD_CMD = 1,
MVSD_EVENT = 3
} mv_sd_type;
/** Function Prototype Declaration */
typedef wlan_private *(*wlan_notifier_fn_add) (void *dev_id);
typedef int (*wlan_notifier_fn_remove) (void *dev_id);
//typedef IRQ_RET_TYPE(*isr_notifier_fn_t) (s32 irq, void *dev_id,struct pt_regs * reg);
typedef IRQ_RET_TYPE(*isr_notifier_fn_t) (s32 irq, void *dev_id,void* reg);
typedef IRQ_RET_TYPE(*handler_fn_t) (s32 irq, void *dev_id, void *);
/* Probe and Check if the card is present*/
int sbi_probe_card(void *card);
int sbi_register_dev(wlan_private * priv);
int sbi_disable_host_int(wlan_private * priv);
int sbi_get_int_status(wlan_private * priv, u8 *);
int sbi_register(wlan_notifier_fn_add, wlan_notifier_fn_remove, void *);
void sbi_unregister(void);
int sbi_prog_firmware(wlan_private *);
//int sbi_verify_fw_download(wlan_private *);
int sbi_prog_helper(wlan_private *);
int sbi_prog_firmware_w_helper(wlan_private *);
int sbi_read_event_cause(wlan_private *);
//int sbi_host_to_card(wlan_private * priv, u8 type, u8 * payload, u16 nb);
int sbi_card_to_host(wlan_private * priv, u32 type, u32 * nb, u8 * payload,
u16 npayload);
int sbi_enable_host_int(wlan_private *);
int sbi_exit_deep_sleep(wlan_private *);
int sbi_reset_deepsleep_wakeup(wlan_private *);
#ifdef ENABLE_PM
int sbi_suspend(wlan_private *);
int sbi_resume(wlan_private *);
#endif
int sbi_get_cis_info(wlan_private * priv);
#endif /* _SBI_H */
wifi/wlan/wlan_11d.c 已删除 100644 → 0
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wifi/wlan/wlan_11d.h 已删除 100644 → 0
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/** @file wlan_11d.h
* @brief This header file contains data structures and
* function declarations of 802.11d
*
* Copyright © Marvell International Ltd. and/or its affiliates, 2003-2006
*/
/*************************************************************
Change log:
09/26/05: add Doxygen format comments
************************************************************/
#ifndef _WLAN_11D_
#define _WLAN_11D_
#define MAX_CHAN_NUM 255
#define UNIVERSAL_REGION_CODE 0xff
/** (Beaconsize(256)-5(IEId,len,contrystr(3))/3(FirstChan,NoOfChan,MaxPwr)
*/
#define MAX_NO_OF_CHAN 40
typedef struct _REGION_CHANNEL *PREGION_CHANNEL;
typedef enum
{
DISABLE_11D = 0,
ENABLE_11D = 1,
} state_11d_t;
/** domain regulatory information */
typedef struct _wlan_802_11d_domain_reg
{
/** country Code*/
u8 CountryCode[COUNTRY_CODE_LEN];
/** No. of subband*/
u8 NoOfSubband;
IEEEtypes_SubbandSet_t Subband[MRVDRV_MAX_SUBBAND_802_11D];
} wlan_802_11d_domain_reg_t;
typedef struct _chan_power_11d
{
u8 chan;
u8 pwr;
} __ATTRIB_PACK__ chan_power_11d_t;
typedef struct _parsed_region_chan_11d
{
u8 band;
u8 region;
s8 CountryCode[COUNTRY_CODE_LEN];
chan_power_11d_t chanPwr[MAX_NO_OF_CHAN];
u8 NoOfChan;
} __ATTRIB_PACK__ parsed_region_chan_11d_t;
/** Data for state machine */
typedef struct _wlan_802_11d_state
{
/** True for Enabling 11D*/
BOOLEAN Enable11D;
} wlan_802_11d_state_t;
typedef struct _region_code_mapping
{
s8 region[COUNTRY_CODE_LEN];
u8 code;
} region_code_mapping_t;
/* function prototypes*/
int wlan_generate_domain_info_11d(parsed_region_chan_11d_t *
parsed_region_chan,
wlan_802_11d_domain_reg_t * domaininfo);
int wlan_parse_domain_info_11d(IEEEtypes_CountryInfoFullSet_t * CountryInfo,
u8 band,
parsed_region_chan_11d_t * parsed_region_chan);
u8 wlan_get_scan_type_11d(u8 chan,
parsed_region_chan_11d_t * parsed_region_chan);
u32 chan_2_freq(u8 chan, u8 band);
int wlan_set_domain_info_11d(wlan_private * priv);
state_11d_t wlan_get_state_11d(wlan_private * priv);
void wlan_init_11d(wlan_private * priv);
int wlan_enable_11d(wlan_private * priv, state_11d_t flag);
int wlan_set_universaltable(wlan_private * priv, u8 band);
void wlan_generate_parsed_region_chan_11d(PREGION_CHANNEL region_chan,
parsed_region_chan_11d_t *
parsed_region_chan);
int wlan_cmd_802_11d_domain_info(wlan_private * priv,
HostCmd_DS_COMMAND * cmd, u16 cmdno,
u16 CmdOption);
//int wlan_cmd_enable_11d(wlan_private * priv, struct iwreq *wrq);
int wlan_ret_802_11d_domain_info(wlan_private * priv,
HostCmd_DS_COMMAND * resp);
int wlan_parse_dnld_countryinfo_11d(wlan_private * priv);
int wlan_create_dnld_countryinfo_11d(wlan_private * priv);
#endif /* _WLAN_11D_ */
wifi/wlan/wlan_cmd.c 已删除 100644 → 0
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wifi/wlan/wlan_cmdresp.c 已删除 100644 → 0
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wifi/wlan/wlan_debug.h 已删除 100644 → 0
浏览文件 @ b29605dc
#ifndef _WLAN_DEBUG_H
#define _WLAN_DEBUG_H
#define WLAN_DEBUG_LEVEL_3
#ifdef WLAN_DEBUG_LEVEL_0
#define wlan_debug1(...)
#define wlan_debug2(...)
#define wlan_debug3(...)
#endif
#ifdef WLAN_DEBUG_LEVEL_1
#define wlan_debug1(a...) rt_kprintf(a)
#define wlan_debug2(...)
#define wlan_debug3(...)
#endif
#ifdef WLAN_DEBUG_LEVEL_2
#define wlan_debug1(a...) rt_kprintf(a)
#define wlan_debug2(a...) rt_kprintf(a)
#define wlan_debug3(...)
#endif
#ifdef WLAN_DEBUG_LEVEL_3
#define wlan_debug1(a...) rt_kprintf(a)
#define wlan_debug2(a...) rt_kprintf(a)
#define wlan_debug3(a...) rt_kprintf(a)
#endif
#define WLANEPARAMETER 101;
#endif
wifi/wlan/wlan_decl.h 已删除 100644 → 0
浏览文件 @ b29605dc
/** @file wlan_decl.h
* @brief This file contains declaration referring to
* functions defined in other source files
*
* Copyright © Marvell International Ltd. and/or its affiliates, 2003-2007
*/
/******************************************************
Change log:
09/29/05: add Doxygen format comments
01/05/06: Add kernel 2.6.x support
01/11/06: Conditionalize new scan/join structures.
Move wlan_wext statics to their source file.
******************************************************/
#ifndef _WLAN_DECL_H_
#define _WLAN_DECL_H_
/** Function Prototype Declaration */
int wlan_init_fw(wlan_private * priv);
int wlan_tx_packet(wlan_private * priv, struct pbuf *skb);
void wlan_free_adapter(wlan_private * priv);
int SendNullPacket(wlan_private * priv, u8 flags);
BOOLEAN CheckLastPacketIndication(wlan_private * priv);
void Wep_encrypt(wlan_private * priv, u8 * Buf, u32 Len);
int FreeCmdBuffer(wlan_private * priv);
void CleanUpCmdCtrlNode(CmdCtrlNode * pTempNode);
CmdCtrlNode *GetFreeCmdCtrlNode(wlan_private * priv);
void SetCmdCtrlNode(wlan_private * priv,
CmdCtrlNode * pTempNode,
WLAN_OID cmd_oid, u16 wait_option, void *pdata_buf);
BOOLEAN Is_Command_Allowed(wlan_private * priv);
int PrepareAndSendCommand(wlan_private * priv,
u16 cmd_no,
u16 cmd_action,
u16 wait_option, WLAN_OID cmd_oid, void *pdata_buf);
void QueueCmd(wlan_adapter * Adapter, CmdCtrlNode * CmdNode, BOOLEAN addtail);
int SetDeepSleep(wlan_private * priv, BOOLEAN bDeepSleep);
int AllocateCmdBuffer(wlan_private * priv);
int ExecuteNextCommand(wlan_private * priv);
int wlan_process_event(wlan_private * priv);
void wlan_interrupt(struct rt_wlan_dev *);
u32 index_to_data_rate(u8 index);
u8 data_rate_to_index(u32 rate);
void HexDump(char *prompt, u8 * data, int len);
void get_version(wlan_adapter * adapter, char *version, int maxlen);
void wlan_read_write_rfreg(wlan_private * priv);
int wlan_process_rx_command(wlan_private * priv);
void wlan_process_tx(wlan_private * priv);
void CleanupAndInsertCmd(wlan_private * priv, CmdCtrlNode * pTempCmd);
void MrvDrvCommandTimerFunction(void *FunctionContext);
int wlan_set_regiontable(wlan_private * priv, u8 region, u8 band);
void wlan_clean_txrx(wlan_private * priv);
int wlan_host_sleep_activated_event(wlan_private * priv);
struct pbuf *ProcessRxedPacket(wlan_private * priv, struct sk_buff *);
void PSSleep(wlan_private * priv, int wait_option);
void PSConfirmSleep(wlan_private * priv, u16 PSMode);
void PSWakeup(wlan_private * priv, int wait_option);
void wlan_send_rxskbQ(wlan_private * priv);
extern void MacEventDisconnected(wlan_private * priv);
void INIT_LIST_HEAD(struct list_head *list);
void list_add_tail(struct list_head *new, struct list_head *head);
void list_add(struct list_head *new, struct list_head *head);
int list_empty(const struct list_head *head);
void list_del(struct list_head *entry);
#endif /* _WLAN_DECL_H_ */
wifi/wlan/wlan_defs.h 已删除 100644 → 0
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wifi/wlan/wlan_dev.h 已删除 100644 → 0
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wifi/wlan/wlan_fw.c 已删除 100644 → 0
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wifi/wlan/wlan_join.c 已删除 100644 → 0
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wifi/wlan/wlan_join.h 已删除 100644 → 0
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wifi/wlan/wlan_main.c 已删除 100644 → 0
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wifi/wlan/wlan_rx.c 已删除 100644 → 0
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wifi/wlan/wlan_scan.c 已删除 100644 → 0
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wifi/wlan/wlan_scan.h 已删除 100644 → 0
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wifi/wlan/wlan_thread.h 已删除 100644 → 0
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wifi/wlan/wlan_tx.c 已删除 100644 → 0
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wifi/wlan/wlan_types.h 已删除 100644 → 0
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wifi/wlan/wlan_utilites.c 已删除 100644 → 0
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wifi/wlan/wlan_version.h 已删除 100644 → 0
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/** @file wlan_version.h
* @brief This file contains wlan driver version number.
*
* Copyright Marvell International Ltd. and/or its affiliates, 2003-2006
*/
/********************************************************
Change log:
10/04/05: Add Doxygen format comments
********************************************************/
//#include "../release_version.h"
const char driver_version[] =
// "gspi8686-%s-" DRIVER_RELEASE_VERSION "-(" "FP" FPNUM ")"
//#ifdef DEBUG_LEVEL2
"-dbg"
//#endif
" ";
wifi/wlan/wlan_wext.c 已删除 100644 → 0
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wifi/wlan/wlan_wext.h 已删除 100644 → 0
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wifi/wlan/wlan_wmm.c 已删除 100644 → 0
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wifi/wlan/wlan_wmm.h 已删除 100644 → 0
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此差异已折叠。
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