Merge remote-tracking branch 'upstream/master'

bsp/stm32/README.md

@@ -9,6 +9,7 @@ STM32 系列 BSP 目前支持情况如下表所示：
 | [stm32f407-atk-explorer](stm32f407-atk-explorer/)    | 正点原子 F407 探索者开发板 |
 | [stm32f429-atk-apollo](stm32f429-atk-apollo/)      | 正点原子 F429 阿波罗开发板 |
 | [stm32f429-fire-challenger](stm32f429-fire-challenger/) | 野火 F429 挑战者开发板     |
+| [stm32l475-atk-pandora](stm32l475-atk-pandora/) | 正点原子 L475 潘多拉 IoT 开发板    |
 | [stm32f767-fire-challenger](stm32f767-fire-challenger/) | 野火 F767 挑战者开发板     |
 
 了解每个 BSP 的详细情况可以阅读该 BSP 下的 readme 文件，如需使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档：

bsp/stm32/docs/STM32系列BSP添加教程.md

@@ -130,6 +130,8 @@ STM32 BSP 由三部分组成，分别是 (1) 通用库、(2) BSP 模板和 (3)
 
 ![修改启动文件和芯片型号](./figures/SConscript.png)
 
+注意：如果在文件夹中找不到相应系列的 .s 文件，可能是多个系列的芯片重用了相同的启动文件，此时可以在 CubeMX 中生成目标芯片的工程，查看使用了哪个启动文件，然后再修改启动文件名。
+
 #### 修改工程模板
 
 **template** 文件是生成 MDK/IAR 工程的模板文件，通过修改该文件可以设置工程中使用的芯片型号以及下载方式。MDK4/MDK5/IAR 的工程模板文件，如下图所示：

bsp/stm32/libraries/HAL_Drivers/SConscript

@@ -13,7 +13,13 @@ if GetDepend(['RT_USING_PIN']):
     
 if GetDepend(['RT_USING_SERIAL']):
     src += ['drv_usart.c']
-    
+
+if GetDepend(['RT_USING_HWTIMER']):
+    src += ['drv_hwtimer.c']
+
+if GetDepend(['RT_USING_PWM']):
+    src += ['drv_pwm.c']
+
 if GetDepend(['RT_USING_SPI']):
     src += ['drv_spi.c']
 
@@ -22,10 +28,7 @@ if GetDepend(['RT_USING_QSPI']):
 
 if GetDepend(['RT_USING_USB_DEVICE']):
     src += ['drv_usb.c']
-    
-if GetDepend(['RT_USING_SDCARD']):
-    src += ['drv_sdcard.c']
-    
+
 if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
     src += ['drv_soft_i2c.c']
 
@@ -56,6 +59,9 @@ if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32L4']):
 if GetDepend(['BSP_USING_WDT']):
     src += ['drv_wdt.c']
 
+if GetDepend(['BSP_USING_SDIO']):
+    src += ['drv_sdio.c']
+
 src += ['drv_common.c']
 
 path =  [cwd]

bsp/stm32/libraries/HAL_Drivers/config/f1/pwm_config.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f1/sdio_config.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32f1xx_hal.h"
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDIO,                                \
+        .dma_rx.dma_rcc = RCC_AHBENR_DMA2EN,             \
+        .dma_tx.dma_rcc = RCC_AHBENR_DMA2EN,             \
+        .dma_rx.Instance = DMA2_Channel4,                \
+        .dma_rx.dma_irq = DMA2_Channel4_IRQn,            \
+        .dma_tx.Instance = DMA2_Channel4,                \
+        .dma_tx.dma_irq = DMA2_Channel4_IRQn,            \
+    }
+
+#define SPI1_DMA_RX_IRQHandler           DMA2_Channel4_IRQHandler    
+#define SPI1_DMA_TX_IRQHandler           DMA2_Channel4_IRQHandler
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

bsp/stm32/libraries/HAL_Drivers/config/f1/tim_config.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM2
+#ifndef TIM2_CONFIG
+#define TIM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .tim_irqn                = TIM2_IRQn,    \
+       .name                    = "timer2",     \
+    }
+#endif /* TIM2_CONFIG */
+#endif /* BSP_USING_TIM2 */
+
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CONFIG
+#define TIM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .tim_irqn                = TIM3_IRQn,    \
+       .name                    = "timer3",     \
+    }
+#endif /* TIM3_CONFIG */
+#endif /* BSP_USING_TIM3 */
+
+#ifdef BSP_USING_TIM4
+#ifndef TIM4_CONFIG
+#define TIM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .tim_irqn                = TIM4_IRQn,    \
+       .name                    = "timer4",     \
+    }
+#endif /* TIM4_CONFIG */
+#endif /* BSP_USING_TIM4 */
+
+#ifdef BSP_USING_TIM5
+#ifndef TIM5_CONFIG
+#define TIM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .tim_irqn                = TIM5_IRQn,    \
+       .name                    = "timer5",     \
+    }
+#endif /* TIM5_CONFIG */
+#endif /* BSP_USING_TIM5 */
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f4/pwm_config.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/f4/sdio_config.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32f4xx_hal.h"
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDIO,                                \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Stream3,                 \
+        .dma_rx.channel = DMA_CHANNEL_4,                 \
+        .dma_rx.dma_irq = DMA2_Stream3_IRQn,             \
+        .dma_tx.Instance = DMA2_Stream6,                 \
+        .dma_tx.channel = DMA_CHANNEL_4,                 \
+        .dma_tx.dma_irq = DMA2_Stream6_IRQn,             \
+    }
+
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream6_IRQHandler
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

bsp/stm32/libraries/HAL_Drivers/config/f4/tim_config.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 3000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM11
+#ifndef TIM11_CONFIG
+#define TIM11_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM11,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM11_IRQn,  \
+       .name                    = "timer11",                \
+    }
+#endif /* TIM11_CONFIG */
+#endif /* BSP_USING_TIM11 */
+
+#ifdef BSP_USING_TIM13
+#ifndef TIM13_CONFIG
+#define TIM13_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM13,                    \
+       .tim_irqn                = TIM8_UP_TIM13_IRQn,       \
+       .name                    = "timer13",                \
+    }
+#endif /* TIM13_CONFIG */
+#endif /* BSP_USING_TIM13 */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM14,                    \
+       .tim_irqn                = TIM8_TRG_COM_TIM14_IRQn,  \
+       .name                    = "timer14",                \
+    }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/l4/pwm_config.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#endif /* __PWM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/config/l4/tim_config.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-12     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM15
+#ifndef TIM15_CONFIG
+#define TIM15_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM15,                    \
+       .tim_irqn                = TIM1_BRK_TIM15_IRQn,      \
+       .name                    = "timer15",                \
+    }
+#endif /* TIM15_CONFIG */
+#endif /* BSP_USING_TIM15 */
+
+#ifdef BSP_USING_TIM16
+#ifndef TIM16_CONFIG
+#define TIM16_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM16,                    \
+       .tim_irqn                = TIM1_UP_TIM16_IRQn,       \
+       .name                    = "timer16",                \
+    }
+#endif /* TIM16_CONFIG */
+#endif /* BSP_USING_TIM16 */
+
+#ifdef BSP_USING_TIM17
+#ifndef TIM17_CONFIG
+#define TIM17_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM17,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM17_IRQn,  \
+       .name                    = "timer17",                \
+    }
+#endif /* TIM17_CONFIG */
+#endif /* BSP_USING_TIM17 */
+
+#endif /* __TIM_CONFIG_H__ */

bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_f4.c

@@ -91,22 +91,30 @@ static rt_uint32_t GetSector(rt_uint32_t Address)
     {
         sector = FLASH_SECTOR_7;
     }
+#if defined(FLASH_SECTOR_8)
     else if((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8))
     {
         sector = FLASH_SECTOR_8;
     }
+#endif
+#if defined(FLASH_SECTOR_9)
     else if((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9))
     {
         sector = FLASH_SECTOR_9;
     }
+#endif
+#if defined(FLASH_SECTOR_10)
     else if((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10))
     {
         sector = FLASH_SECTOR_10;
     }
+#endif
+#if defined(FLASH_SECTOR_11)
     else if((Address < ADDR_FLASH_SECTOR_12) && (Address >= ADDR_FLASH_SECTOR_11))
     {
         sector = FLASH_SECTOR_11;
     }
+#endif
 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
     else if((Address < ADDR_FLASH_SECTOR_13) && (Address >= ADDR_FLASH_SECTOR_12))
     {
@@ -219,7 +227,7 @@ int stm32_flash_write(long offset, const rt_uint8_t *buf, size_t size)
 
     HAL_FLASH_Unlock();
 
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGSERR);
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR);
 
     for (size_t i = 0; i < size; i++, addr++, buf++)
     {
@@ -278,17 +286,19 @@ int stm32_flash_erase(long offset, size_t size)
     /* Unlock the Flash to enable the flash control register access */
     HAL_FLASH_Unlock();
 
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR);
+
     /* Get the 1st sector to erase */
     FirstSector = GetSector(addr);
     /* Get the number of sector to erase from 1st sector*/
-    NbOfSectors = GetSector(addr + size) - FirstSector + 1;
+    NbOfSectors = GetSector(addr + size - 1) - FirstSector + 1;
     /* Fill EraseInit structure*/
     EraseInitStruct.TypeErase     = FLASH_TYPEERASE_SECTORS;
     EraseInitStruct.VoltageRange  = FLASH_VOLTAGE_RANGE_3;
     EraseInitStruct.Sector        = FirstSector;
     EraseInitStruct.NbSectors     = NbOfSectors;
 
-    if (HAL_FLASHEx_Erase(&EraseInitStruct, &SECTORError) != HAL_OK)
+    if (HAL_FLASHEx_Erase(&EraseInitStruct, (uint32_t *)&SECTORError) != HAL_OK)
     {
         result = -RT_ERROR;
         goto __exit;

bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_l4.c

@@ -244,7 +244,7 @@ int stm32_flash_erase(long offset, size_t size)
     /* Get the 1st page to erase */
     FirstPage = GetPage(addr);
     /* Get the number of pages to erase from 1st page */
-    NbOfPages = GetPage(addr + size) - FirstPage + 1;
+    NbOfPages = GetPage(addr + size - 1) - FirstPage + 1;
     /* Get the bank */
     BankNumber = GetBank(addr);
     /* Fill EraseInit structure*/

bsp/stm32/libraries/HAL_Drivers/drv_hwtimer.c

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-10     zylx         first version
+ */
+
+#include <board.h>
+#ifdef BSP_USING_TIM
+#include "drv_config.h"
+
+//#define DRV_DEBUG
+#define LOG_TAG             "drv.hwtimer"
+#include <drv_log.h>
+
+#ifdef RT_USING_HWTIMER
+enum
+{
+#ifdef BSP_USING_TIM1
+    TIM1_INDEX,
+#endif
+#ifdef BSP_USING_TIM2
+    TIM2_INDEX,
+#endif
+#ifdef BSP_USING_TIM3
+    TIM3_INDEX,
+#endif
+#ifdef BSP_USING_TIM4
+    TIM4_INDEX,
+#endif
+#ifdef BSP_USING_TIM5
+    TIM5_INDEX,
+#endif
+#ifdef BSP_USING_TIM6
+    TIM6_INDEX,
+#endif
+#ifdef BSP_USING_TIM7
+    TIM7_INDEX,
+#endif
+#ifdef BSP_USING_TIM8
+    TIM8_INDEX,
+#endif
+#ifdef BSP_USING_TIM9
+    TIM9_INDEX,
+#endif
+#ifdef BSP_USING_TIM10
+    TIM10_INDEX,
+#endif
+#ifdef BSP_USING_TIM11
+    TIM11_INDEX,
+#endif
+#ifdef BSP_USING_TIM12
+    TIM12_INDEX,
+#endif
+#ifdef BSP_USING_TIM13
+    TIM13_INDEX,
+#endif
+#ifdef BSP_USING_TIM14
+    TIM14_INDEX,
+#endif
+#ifdef BSP_USING_TIM15
+    TIM15_INDEX,
+#endif
+#ifdef BSP_USING_TIM16
+    TIM16_INDEX,
+#endif
+#ifdef BSP_USING_TIM17
+    TIM17_INDEX,
+#endif
+};
+
+struct stm32_hwtimer
+{
+    rt_hwtimer_t time_device;
+    TIM_HandleTypeDef    tim_handle;
+    IRQn_Type tim_irqn;
+    char *name;
+};
+
+static struct stm32_hwtimer stm32_hwtimer_obj[] =
+{
+#ifdef BSP_USING_TIM1
+    TIM1_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM2
+    TIM2_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM3
+    TIM3_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM4
+    TIM4_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM5
+    TIM5_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM6
+    TIM6_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM7
+    TIM7_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM8
+    TIM8_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM9
+    TIM9_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM10
+    TIM10_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM11
+    TIM11_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM12
+    TIM12_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM13
+    TIM13_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM14
+    TIM14_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM15
+    TIM15_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM16
+    TIM16_CONFIG,
+#endif
+
+#ifdef BSP_USING_TIM17
+    TIM17_CONFIG,
+#endif
+};
+
+static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
+{
+    uint32_t prescaler_value = 0;
+    TIM_HandleTypeDef *tim = RT_NULL;
+    struct stm32_hwtimer *tim_device = RT_NULL;
+
+    RT_ASSERT(timer != RT_NULL);
+    if (state)
+    {
+        tim = (TIM_HandleTypeDef *)timer->parent.user_data;
+        tim_device = (struct stm32_hwtimer *)timer;
+
+        /* time init */
+#if defined(SOC_SERIES_STM32F4)
+        if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
+#elif defined(SOC_SERIES_STM32L4)
+        if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17)
+#elif defined(SOC_SERIES_STM32F1)
+        if (0)
+#endif
+        {
+            prescaler_value = (uint32_t)(HAL_RCC_GetPCLK2Freq() * 2 / 10000) - 1;
+        }
+        else
+        {
+            prescaler_value = (uint32_t)(HAL_RCC_GetPCLK1Freq() * 2 / 10000) - 1;
+        }
+        tim->Init.Period            = 10000 - 1;
+        tim->Init.Prescaler         = prescaler_value;
+        tim->Init.ClockDivision     = TIM_CLOCKDIVISION_DIV1;
+        if (timer->info->cntmode == HWTIMER_CNTMODE_UP)
+        {
+            tim->Init.CounterMode   = TIM_COUNTERMODE_UP;
+        }
+        else
+        {
+            tim->Init.CounterMode   = TIM_COUNTERMODE_DOWN;
+        }
+        tim->Init.RepetitionCounter = 0;
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
+        tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+#endif
+        if (HAL_TIM_Base_Init(tim) != HAL_OK)
+        {
+            LOG_E("%s init failed", tim_device->name);
+            return;
+        }
+        else
+        {
+            /* set the TIMx priority */
+            HAL_NVIC_SetPriority(tim_device->tim_irqn, 3, 0);
+
+            /* enable the TIMx global Interrupt */
+            HAL_NVIC_EnableIRQ(tim_device->tim_irqn);
+
+            /* clear update flag */
+            __HAL_TIM_CLEAR_FLAG(tim, TIM_FLAG_UPDATE);
+            /* enable update request source */
+            __HAL_TIM_URS_ENABLE(tim);
+
+            LOG_D("%s init success", tim_device->name);
+        }
+    }
+}
+
+static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
+{
+    rt_err_t result = RT_EOK;
+    TIM_HandleTypeDef *tim = RT_NULL;
+
+    RT_ASSERT(timer != RT_NULL);
+
+    tim = (TIM_HandleTypeDef *)timer->parent.user_data;
+
+    /* set tim cnt */
+    __HAL_TIM_SET_AUTORELOAD(tim, t);
+
+    if (opmode == HWTIMER_MODE_ONESHOT)
+    {
+        /* set timer to single mode */
+        tim->Instance->CR1 |= TIM_OPMODE_SINGLE;
+    }
+
+    /* start timer */
+    if (HAL_TIM_Base_Start_IT(tim) != HAL_OK)
+    {
+        LOG_E("TIM2 start failed");
+        result = -RT_ERROR;
+    }
+
+    return result;
+}
+
+static void timer_stop(rt_hwtimer_t *timer)
+{
+    TIM_HandleTypeDef *tim = RT_NULL;
+
+    RT_ASSERT(timer != RT_NULL);
+
+    tim = (TIM_HandleTypeDef *)timer->parent.user_data;
+
+    /* stop timer */
+    HAL_TIM_Base_Stop_IT(tim);
+}
+
+static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
+{
+    TIM_HandleTypeDef *tim = RT_NULL;
+    rt_err_t result = RT_EOK;
+
+    RT_ASSERT(timer != RT_NULL);
+    RT_ASSERT(arg != RT_NULL);
+
+    tim = (TIM_HandleTypeDef *)timer->parent.user_data;
+
+    switch (cmd)
+    {
+    case HWTIMER_CTRL_FREQ_SET:
+    {
+        rt_uint32_t freq;
+        rt_uint16_t val;
+
+        /* set timer frequence */
+        freq = *((rt_uint32_t *)arg);
+
+#if defined(SOC_SERIES_STM32F4)
+        if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
+#elif defined(SOC_SERIES_STM32L4)
+        if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17)
+#elif defined(SOC_SERIES_STM32F1)
+        if (0)
+#endif
+        {
+#if defined(SOC_SERIES_STM32L4)
+            val = HAL_RCC_GetPCLK2Freq() / freq;
+#else
+            val = HAL_RCC_GetPCLK2Freq() * 2 / freq;
+#endif
+        }
+        else
+        {
+            val = HAL_RCC_GetPCLK1Freq() * 2 / freq;
+        }
+        __HAL_TIM_SET_PRESCALER(tim, val - 1);
+
+        /* Update frequency value */
+        tim->Instance->EGR |= TIM_EVENTSOURCE_UPDATE;
+    }
+    break;
+    default:
+    {
+        result = -RT_ENOSYS;
+    }
+    break;
+    }
+
+    return result;
+}
+
+static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
+{
+    TIM_HandleTypeDef *tim = RT_NULL;
+
+    RT_ASSERT(timer != RT_NULL);
+
+    tim = (TIM_HandleTypeDef *)timer->parent.user_data;
+
+    return tim->Instance->CNT;
+}
+
+static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG;
+
+static const struct rt_hwtimer_ops _ops =
+{
+    .init = timer_init,
+    .start = timer_start,
+    .stop = timer_stop,
+    .count_get = timer_counter_get,
+    .control = timer_ctrl,
+};
+
+#ifdef BSP_USING_TIM2
+void TIM2_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM2_INDEX].tim_handle);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM3
+void TIM3_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM3_INDEX].tim_handle);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM4
+void TIM4_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM4_INDEX].tim_handle);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM5
+void TIM5_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM5_INDEX].tim_handle);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM11
+void TIM1_TRG_COM_TIM11_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM11_INDEX].tim_handle);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM13
+void TIM8_UP_TIM13_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM13_INDEX].tim_handle);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM14
+void TIM8_TRG_COM_TIM14_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM14_INDEX].tim_handle);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM15
+void TIM1_BRK_TIM15_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM15_INDEX].tim_handle);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM16
+void TIM1_UP_TIM16_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM16_INDEX].tim_handle);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM17
+void TIM1_TRG_COM_TIM17_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM17_INDEX].tim_handle);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
+{
+#ifdef BSP_USING_TIM2
+    if (htim->Instance == TIM2)
+    {
+        rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM2_INDEX].time_device);
+    }
+#endif
+#ifdef BSP_USING_TIM3
+    if (htim->Instance == TIM3)
+    {
+        rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM3_INDEX].time_device);
+    }
+#endif
+#ifdef BSP_USING_TIM4
+    if (htim->Instance == TIM4)
+    {
+        rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM4_INDEX].time_device);
+    }
+#endif
+#ifdef BSP_USING_TIM5
+    if (htim->Instance == TIM5)
+    {
+        rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM5_INDEX].time_device);
+    }
+#endif
+#ifdef BSP_USING_TIM11
+    if (htim->Instance == TIM11)
+    {
+        rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM11_INDEX].time_device);
+    }
+#endif
+#ifdef BSP_USING_TIM13
+    if (htim->Instance == TIM13)
+    {
+        rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM13_INDEX].time_device);
+    }
+#endif
+#ifdef BSP_USING_TIM14
+    if (htim->Instance == TIM14)
+    {
+        rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM14_INDEX].time_device);
+    }
+#endif
+#ifdef BSP_USING_TIM15
+    if (htim->Instance == TIM15)
+    {
+        rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM15_INDEX].time_device);
+    }
+#endif
+#ifdef BSP_USING_TIM16
+    if (htim->Instance == TIM16)
+    {
+        rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM16_INDEX].time_device);
+    }
+#endif
+#ifdef BSP_USING_TIM17
+    if (htim->Instance == TIM17)
+    {
+        rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM17_INDEX].time_device);
+    }
+#endif
+}
+
+static int stm32_hwtimer_init(void)
+{
+    int i = 0;
+    int result = RT_EOK;
+
+    for (i = 0; i < sizeof(stm32_hwtimer_obj) / sizeof(stm32_hwtimer_obj[0]); i++)
+    {
+        stm32_hwtimer_obj[i].time_device.info = &_info;
+        stm32_hwtimer_obj[i].time_device.ops  = &_ops;
+        if (rt_device_hwtimer_register(&stm32_hwtimer_obj[i].time_device, stm32_hwtimer_obj[i].name, &stm32_hwtimer_obj[i].tim_handle) == RT_EOK)
+        {
+            LOG_D("%s register success", stm32_hwtimer_obj[i].name);
+        }
+        else
+        {
+            LOG_E("%s register failed", stm32_hwtimer_obj[i].name);
+            result = -RT_ERROR;
+        }
+    }
+
+    return result;
+}
+INIT_BOARD_EXPORT(stm32_hwtimer_init);
+
+#endif /* RT_USING_HWTIMER */
+#endif /* BSP_USING_TIM */

bsp/stm32/libraries/HAL_Drivers/drv_pwm.c

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#include <board.h>
+#ifdef RT_USING_PWM
+#include "drv_config.h"
+
+//#define DRV_DEBUG
+#define LOG_TAG             "drv.pwm"
+#include <drv_log.h>
+
+#define MAX_PERIOD 65535
+#define MIN_PERIOD 3
+#define MIN_PULSE 2
+
+extern void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+
+enum
+{
+#ifdef BSP_USING_PWM1
+    PWM1_INDEX,
+#endif
+#ifdef BSP_USING_PWM2
+    PWM2_INDEX,
+#endif
+#ifdef BSP_USING_PWM3
+    PWM3_INDEX,
+#endif
+#ifdef BSP_USING_PWM4
+    PWM4_INDEX,
+#endif
+#ifdef BSP_USING_PWM5
+    PWM5_INDEX,
+#endif
+#ifdef BSP_USING_PWM6
+    PWM6_INDEX,
+#endif
+#ifdef BSP_USING_PWM7
+    PWM7_INDEX,
+#endif
+#ifdef BSP_USING_PWM8
+    PWM8_INDEX,
+#endif
+#ifdef BSP_USING_PWM9
+    PWM9_INDEX,
+#endif
+#ifdef BSP_USING_PWM10
+    PWM10_INDEX,
+#endif
+#ifdef BSP_USING_PWM11
+    PWM11_INDEX,
+#endif
+#ifdef BSP_USING_PWM12
+    PWM12_INDEX,
+#endif
+#ifdef BSP_USING_PWM13
+    PWM13_INDEX,
+#endif
+#ifdef BSP_USING_PWM14
+    PWM14_INDEX,
+#endif
+#ifdef BSP_USING_PWM15
+    PWM15_INDEX,
+#endif
+#ifdef BSP_USING_PWM16
+    PWM16_INDEX,
+#endif
+#ifdef BSP_USING_PWM17
+    PWM17_INDEX,
+#endif
+};
+
+struct stm32_pwm
+{
+    struct rt_device_pwm pwm_device;
+    TIM_HandleTypeDef    tim_handle;
+    rt_uint8_t channel;
+    char *name;
+};
+
+static struct stm32_pwm stm32_pwm_obj[] =
+{
+#ifdef BSP_USING_PWM1
+    PWM1_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM2
+    PWM2_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM3
+    PWM3_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM4
+    PWM4_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM5
+    PWM5_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM6
+    PWM6_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM7
+    PWM7_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM8
+    PWM8_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM9
+    PWM9_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM10
+    PWM10_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM11
+    PWM11_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM12
+    PWM12_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM13
+    PWM13_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM14
+    PWM14_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM15
+    PWM15_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM16
+    PWM16_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM17
+    PWM17_CONFIG,
+#endif
+};
+
+static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg);
+static struct rt_pwm_ops drv_ops =
+{
+    drv_pwm_control
+};
+
+static rt_err_t drv_pwm_enable(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration, rt_bool_t enable)
+{
+    /* Converts the channel number to the channel number of Hal library */
+    rt_uint32_t channel = 0x04 * (configuration->channel - 1);
+
+    if (!enable)
+    {
+        HAL_TIM_PWM_Stop(htim, channel);
+    }
+    else
+    {
+        HAL_TIM_PWM_Start(htim, channel);
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t drv_pwm_get(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
+{
+    /* Converts the channel number to the channel number of Hal library */
+    rt_uint32_t channel = 0x04 * (configuration->channel - 1);
+    rt_uint64_t tim_clock;
+
+#if defined(SOC_SERIES_STM32F4)
+    if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
+#elif defined(SOC_SERIES_STM32L4)
+    if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
+#elif defined(SOC_SERIES_STM32F1)
+    if (0)
+#endif
+    {
+        tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
+    }
+    else
+    {
+#if defined(SOC_SERIES_STM32L4)
+        tim_clock = HAL_RCC_GetPCLK1Freq();
+#else
+        tim_clock = HAL_RCC_GetPCLK1Freq() * 2;
+#endif
+    }
+    
+    if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV2)
+    {
+        tim_clock = tim_clock / 2;
+    }
+    else if (__HAL_TIM_GET_CLOCKDIVISION(htim) == TIM_CLOCKDIVISION_DIV4)
+    {
+        tim_clock = tim_clock / 4;
+    }
+
+    /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
+    tim_clock /= 1000000UL;
+    configuration->period = (__HAL_TIM_GET_AUTORELOAD(htim) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
+    configuration->pulse = (__HAL_TIM_GET_COMPARE(htim, channel) + 1) * (htim->Instance->PSC + 1) * 1000UL / tim_clock;
+
+    return RT_EOK;
+}
+
+static rt_err_t drv_pwm_set(TIM_HandleTypeDef *htim, struct rt_pwm_configuration *configuration)
+{
+    rt_uint32_t period, pulse;
+    rt_uint64_t tim_clock, psc;
+    /* Converts the channel number to the channel number of Hal library */
+    rt_uint32_t channel = 0x04 * (configuration->channel - 1);
+
+#if defined(SOC_SERIES_STM32F4)
+    if (htim->Instance == TIM9 || htim->Instance == TIM10 || htim->Instance == TIM11)
+#elif defined(SOC_SERIES_STM32L4)
+    if (htim->Instance == TIM15 || htim->Instance == TIM16 || htim->Instance == TIM17)
+#elif defined(SOC_SERIES_STM32F1)
+    if (0)
+#endif
+    {
+        tim_clock = HAL_RCC_GetPCLK2Freq() * 2;
+    }
+    else
+    {
+#if defined(SOC_SERIES_STM32L4)
+        tim_clock = HAL_RCC_GetPCLK1Freq();
+#else
+        tim_clock = HAL_RCC_GetPCLK1Freq() * 2;
+#endif
+    }
+
+    /* Convert nanosecond to frequency and duty cycle. 1s = 1 * 1000 * 1000 * 1000 ns */
+    tim_clock /= 1000000UL;
+    period = (unsigned long long)configuration->period * tim_clock / 1000ULL ;
+    psc = period / MAX_PERIOD + 1;
+    period = period / psc;
+    __HAL_TIM_SET_PRESCALER(htim, psc - 1);
+
+    if (period < MIN_PERIOD)
+    {
+        period = MIN_PERIOD;
+    }
+    __HAL_TIM_SET_AUTORELOAD(htim, period - 1);
+
+    pulse = (unsigned long long)configuration->pulse * tim_clock / psc / 1000ULL;
+    if (pulse < MIN_PULSE)
+    {
+        pulse = MIN_PULSE;
+    }
+    else if (pulse > period)
+    {
+        pulse = period;
+    }
+    __HAL_TIM_SET_COMPARE(htim, channel, pulse - 1);
+    __HAL_TIM_SET_COUNTER(htim, 0);
+
+    /* Update frequency value */
+    HAL_TIM_GenerateEvent(htim, TIM_EVENTSOURCE_UPDATE);
+
+    return RT_EOK;
+}
+
+static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
+{
+    struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
+    TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)device->parent.user_data;
+
+    switch (cmd)
+    {
+    case PWM_CMD_ENABLE:
+        return drv_pwm_enable(htim, configuration, RT_TRUE);
+    case PWM_CMD_DISABLE:
+        return drv_pwm_enable(htim, configuration, RT_FALSE);
+    case PWM_CMD_SET:
+        return drv_pwm_set(htim, configuration);
+    case PWM_CMD_GET:
+        return drv_pwm_get(htim, configuration);
+    default:
+        return RT_EINVAL;
+    }
+}
+
+static rt_err_t stm32_hw_pwm_init(struct stm32_pwm *device)
+{
+    rt_err_t result = RT_EOK;
+    TIM_HandleTypeDef *tim = RT_NULL;
+    TIM_OC_InitTypeDef oc_config = {0};
+    TIM_MasterConfigTypeDef master_config = {0};
+    TIM_ClockConfigTypeDef clock_config = {0};
+
+    RT_ASSERT(device != RT_NULL);
+
+    tim = (TIM_HandleTypeDef *)&device->tim_handle;
+
+    /* configure the timer to pwm mode */
+    tim->Init.Prescaler = 0;
+    tim->Init.CounterMode = TIM_COUNTERMODE_UP;
+    tim->Init.Period = 0;
+    tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4)
+    tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+#endif
+    if (HAL_TIM_Base_Init(tim) != HAL_OK)
+    {
+        LOG_E("%s time base init failed", device->name);
+        result = -RT_ERROR;
+        goto __exit;
+    }
+
+    clock_config.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+    if (HAL_TIM_ConfigClockSource(tim, &clock_config) != HAL_OK)
+    {
+        LOG_E("%s clock init failed", device->name);
+        result = -RT_ERROR;
+        goto __exit;
+    }
+
+    if (HAL_TIM_PWM_Init(tim) != HAL_OK)
+    {
+        LOG_E("%s pwm init failed", device->name);
+        result = -RT_ERROR;
+        goto __exit;
+    }
+
+    master_config.MasterOutputTrigger = TIM_TRGO_RESET;
+    master_config.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+    if (HAL_TIMEx_MasterConfigSynchronization(tim, &master_config) != HAL_OK)
+    {
+        LOG_E("%s master config failed", device->name);
+        result = -RT_ERROR;
+        goto __exit;
+    }
+
+    oc_config.OCMode = TIM_OCMODE_PWM1;
+    oc_config.Pulse = 0;
+    oc_config.OCPolarity = TIM_OCPOLARITY_HIGH;
+    oc_config.OCFastMode = TIM_OCFAST_DISABLE;
+
+    /* config pwm channel */
+    if (device->channel & 0x01)
+    {
+        if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_1) != HAL_OK)
+        {
+            LOG_E("%s channel1 config failed", device->name);
+            result = -RT_ERROR;
+            goto __exit;
+        }
+    }
+
+    if (device->channel & 0x02)
+    {
+        if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_2) != HAL_OK)
+        {
+            LOG_E("%s channel2 config failed", device->name);
+            result = -RT_ERROR;
+            goto __exit;
+        }
+    }
+
+    if (device->channel & 0x04)
+    {
+        if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_3) != HAL_OK)
+        {
+            LOG_E("%s channel3 config failed", device->name);
+            result = -RT_ERROR;
+            goto __exit;
+        }
+    }
+
+    if (device->channel & 0x08)
+    {
+        if (HAL_TIM_PWM_ConfigChannel(tim, &oc_config, TIM_CHANNEL_4) != HAL_OK)
+        {
+            LOG_E("%s channel4 config failed", device->name);
+            result = -RT_ERROR;
+            goto __exit;
+        }
+    }
+
+    /* pwm pin configuration */
+    HAL_TIM_MspPostInit(tim);
+
+    /* enable update request source */
+    __HAL_TIM_URS_ENABLE(tim);
+
+__exit:
+    return result;
+}
+
+static void pwm_get_channel(void)
+{
+#ifdef BSP_USING_PWM2_CH4
+    stm32_pwm_obj[PWM2_INDEX].channel |= 1 << 3;
+#endif
+#ifdef BSP_USING_PWM3_CH1
+    stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 0;
+#endif
+#ifdef BSP_USING_PWM3_CH2
+    stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 1;
+#endif
+#ifdef BSP_USING_PWM3_CH3
+    stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 2;
+#endif
+#ifdef BSP_USING_PWM3_CH4
+    stm32_pwm_obj[PWM3_INDEX].channel |= 1 << 3;
+#endif
+#ifdef BSP_USING_PWM4_CH2
+    stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 1;
+#endif
+#ifdef BSP_USING_PWM4_CH3
+    stm32_pwm_obj[PWM4_INDEX].channel |= 1 << 2;
+#endif
+#ifdef BSP_USING_PWM5_CH1
+    stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 1;
+#endif
+#ifdef BSP_USING_PWM5_CH2
+    stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 2;
+#endif
+#ifdef BSP_USING_PWM5_CH3
+    stm32_pwm_obj[PWM5_INDEX].channel |= 1 << 3;
+#endif
+}
+
+static int stm32_pwm_init(void)
+{
+    int i = 0;
+    int result = RT_EOK;
+
+    pwm_get_channel();
+
+    for (i = 0; i < sizeof(stm32_pwm_obj) / sizeof(stm32_pwm_obj[0]); i++)
+    {
+        /* pwm init */
+        if (stm32_hw_pwm_init(&stm32_pwm_obj[i]) != RT_EOK)
+        {
+            LOG_E("%s init failed", stm32_pwm_obj[i].name);
+            result = -RT_ERROR;
+            goto __exit;
+        }
+        else
+        {
+            LOG_D("%s init success", stm32_pwm_obj[i].name);
+
+            /* register pwm device */
+            if (rt_device_pwm_register(rt_calloc(1, sizeof(struct rt_device_pwm)), stm32_pwm_obj[i].name, &drv_ops, &stm32_pwm_obj[i].tim_handle) == RT_EOK)
+            {
+
+                LOG_D("%s register success", stm32_pwm_obj[i].name);
+            }
+            else
+            {
+                LOG_E("%s register failed", stm32_pwm_obj[i].name);
+                result = -RT_ERROR;
+            }
+        }
+    }
+
+__exit:
+    return result;
+}
+INIT_DEVICE_EXPORT(stm32_pwm_init);
+#endif /* RT_USING_PWM */

bsp/stm32/libraries/HAL_Drivers/drv_sdio.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef _DRV_SDIO_H
+#define _DRV_SDIO_H
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+#include <drv_common.h>
+#include "drv_dma.h"
+#include <string.h>
+#include <drivers/mmcsd_core.h>
+#include <drivers/sdio.h>
+
+#define SDIO_BUFF_SIZE       4096
+#define SDIO_MAX_FREQ        2000000
+#define SDIO_ALIGN_LEN       32
+
+#ifndef SDIO_BASE_ADDRESS
+#define SDIO_BASE_ADDRESS    (0x40012800U)
+#endif
+
+#ifndef SDIO_CLOCK_FREQ
+#define SDIO_CLOCK_FREQ      (48U * 1000 * 1000)
+#endif
+
+#ifndef SDIO_BUFF_SIZE
+#define SDIO_BUFF_SIZE       (4096)
+#endif
+
+#ifndef SDIO_ALIGN_LEN
+#define SDIO_ALIGN_LEN       (32)
+#endif
+
+#ifndef SDIO_MAX_FREQ
+#define SDIO_MAX_FREQ        (24 * 1000 * 1000)
+#endif
+
+#define HW_SDIO_IT_CCRCFAIL                    (0x01U << 0)
+#define HW_SDIO_IT_DCRCFAIL                    (0x01U << 1)
+#define HW_SDIO_IT_CTIMEOUT                    (0x01U << 2)
+#define HW_SDIO_IT_DTIMEOUT                    (0x01U << 3)
+#define HW_SDIO_IT_TXUNDERR                    (0x01U << 4)
+#define HW_SDIO_IT_RXOVERR                     (0x01U << 5)
+#define HW_SDIO_IT_CMDREND                     (0x01U << 6)
+#define HW_SDIO_IT_CMDSENT                     (0x01U << 7)
+#define HW_SDIO_IT_DATAEND                     (0x01U << 8)
+#define HW_SDIO_IT_STBITERR                    (0x01U << 9)
+#define HW_SDIO_IT_DBCKEND                     (0x01U << 10)
+#define HW_SDIO_IT_CMDACT                      (0x01U << 11)
+#define HW_SDIO_IT_TXACT                       (0x01U << 12)
+#define HW_SDIO_IT_RXACT                       (0x01U << 13)
+#define HW_SDIO_IT_TXFIFOHE                    (0x01U << 14)
+#define HW_SDIO_IT_RXFIFOHF                    (0x01U << 15)
+#define HW_SDIO_IT_TXFIFOF                     (0x01U << 16)
+#define HW_SDIO_IT_RXFIFOF                     (0x01U << 17)
+#define HW_SDIO_IT_TXFIFOE                     (0x01U << 18)
+#define HW_SDIO_IT_RXFIFOE                     (0x01U << 19)
+#define HW_SDIO_IT_TXDAVL                      (0x01U << 20)
+#define HW_SDIO_IT_RXDAVL                      (0x01U << 21)
+#define HW_SDIO_IT_SDIOIT                      (0x01U << 22)
+
+#define HW_SDIO_ERRORS \
+    (HW_SDIO_IT_CCRCFAIL | HW_SDIO_IT_CTIMEOUT | \
+     HW_SDIO_IT_DCRCFAIL | HW_SDIO_IT_DTIMEOUT | \
+     HW_SDIO_IT_RXOVERR  | HW_SDIO_IT_TXUNDERR)
+
+#define HW_SDIO_POWER_OFF                      (0x00U)
+#define HW_SDIO_POWER_UP                       (0x02U)
+#define HW_SDIO_POWER_ON                       (0x03U)
+
+#define HW_SDIO_FLOW_ENABLE                    (0x01U << 14)
+#define HW_SDIO_BUSWIDE_1B                     (0x00U << 11)
+#define HW_SDIO_BUSWIDE_4B                     (0x01U << 11)
+#define HW_SDIO_BUSWIDE_8B                     (0x02U << 11)
+#define HW_SDIO_BYPASS_ENABLE                  (0x01U << 10)
+#define HW_SDIO_IDLE_ENABLE                    (0x01U << 9)
+#define HW_SDIO_CLK_ENABLE                     (0x01U << 8)
+
+#define HW_SDIO_SUSPEND_CMD                    (0x01U << 11)
+#define HW_SDIO_CPSM_ENABLE                    (0x01U << 10)
+#define HW_SDIO_WAIT_END                       (0x01U << 9)
+#define HW_SDIO_WAIT_INT                       (0x01U << 8)
+#define HW_SDIO_RESPONSE_NO                    (0x00U << 6)
+#define HW_SDIO_RESPONSE_SHORT                 (0x01U << 6)
+#define HW_SDIO_RESPONSE_LONG                  (0x03U << 6)
+
+#define HW_SDIO_DATA_LEN_MASK                  (0x01FFFFFFU)
+
+#define HW_SDIO_IO_ENABLE                      (0x01U << 11)
+#define HW_SDIO_RWMOD_CK                       (0x01U << 10)
+#define HW_SDIO_RWSTOP_ENABLE                  (0x01U << 9)
+#define HW_SDIO_RWSTART_ENABLE                 (0x01U << 8)
+#define HW_SDIO_DBLOCKSIZE_1                   (0x00U << 4)
+#define HW_SDIO_DBLOCKSIZE_2                   (0x01U << 4)
+#define HW_SDIO_DBLOCKSIZE_4                   (0x02U << 4)
+#define HW_SDIO_DBLOCKSIZE_8                   (0x03U << 4)
+#define HW_SDIO_DBLOCKSIZE_16                  (0x04U << 4)
+#define HW_SDIO_DBLOCKSIZE_32                  (0x05U << 4)
+#define HW_SDIO_DBLOCKSIZE_64                  (0x06U << 4)
+#define HW_SDIO_DBLOCKSIZE_128                 (0x07U << 4)
+#define HW_SDIO_DBLOCKSIZE_256                 (0x08U << 4)
+#define HW_SDIO_DBLOCKSIZE_512                 (0x09U << 4)
+#define HW_SDIO_DBLOCKSIZE_1024                (0x0AU << 4)
+#define HW_SDIO_DBLOCKSIZE_2048                (0x0BU << 4)
+#define HW_SDIO_DBLOCKSIZE_4096                (0x0CU << 4)
+#define HW_SDIO_DBLOCKSIZE_8192                (0x0DU << 4)
+#define HW_SDIO_DBLOCKSIZE_16384               (0x0EU << 4)
+#define HW_SDIO_DMA_ENABLE                     (0x01U << 3)
+#define HW_SDIO_STREAM_ENABLE                  (0x01U << 2)
+#define HW_SDIO_TO_HOST                        (0x01U << 1)
+#define HW_SDIO_DPSM_ENABLE                    (0x01U << 0)
+
+#define HW_SDIO_DATATIMEOUT                    (0xF0000000U)
+
+struct stm32_sdio
+{
+    volatile rt_uint32_t power;
+    volatile rt_uint32_t clkcr;
+    volatile rt_uint32_t arg;
+    volatile rt_uint32_t cmd;
+    volatile rt_uint32_t respcmd;
+    volatile rt_uint32_t resp1;
+    volatile rt_uint32_t resp2;
+    volatile rt_uint32_t resp3;
+    volatile rt_uint32_t resp4;
+    volatile rt_uint32_t dtimer;
+    volatile rt_uint32_t dlen;
+    volatile rt_uint32_t dctrl;
+    volatile rt_uint32_t dcount;
+    volatile rt_uint32_t sta;
+    volatile rt_uint32_t icr;
+    volatile rt_uint32_t mask;
+    volatile rt_uint32_t reserved0[2];
+    volatile rt_uint32_t fifocnt;
+    volatile rt_uint32_t reserved1[13];
+    volatile rt_uint32_t fifo;
+};
+
+typedef rt_err_t (*dma_txconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size);
+typedef rt_err_t (*dma_rxconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size);
+typedef rt_uint32_t (*sdio_clk_get)(struct stm32_sdio *hw_sdio);
+
+struct stm32_sdio_des
+{
+    struct stm32_sdio *hw_sdio;
+    dma_txconfig txconfig;
+    dma_rxconfig rxconfig;
+    sdio_clk_get clk_get;
+};
+
+struct stm32_sdio_config
+{
+    SDIO_TypeDef *Instance;
+    struct dma_config dma_rx, dma_tx;
+};
+
+/* stm32 sdio dirver class */
+struct stm32_sdio_class
+{
+    struct stm32_sdio_des *des;
+    const struct stm32_sdio_config *cfg;
+    struct rt_mmcsd_host host;
+    struct
+    {
+        DMA_HandleTypeDef handle_rx;
+        DMA_HandleTypeDef handle_tx;
+    } dma;
+};
+
+#endif

bsp/stm32/libraries/STM32F1xx_HAL/SConscript

@@ -8,69 +8,80 @@ cwd = GetCurrentDir()
 # The set of source files associated with this SConscript file.
 src = Split("""
 CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c
 STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c
 STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c
 STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_crc.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_irda.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c
 STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c
 STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c
 STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_smartcard.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_usart.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_wwdg.c
 STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_adc.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_crc.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dac.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_i2c.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rcc.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rtc.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_tim.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usart.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c
 STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cec.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dac.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dac_ex.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_eth.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_hcd.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2s.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_mmc.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nand.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pccard.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c
 STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c
 """)
-#device options
+
+if GetDepend(['RT_USING_PIN']):
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c']
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c']
+    
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c']
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_usart.c']
+
+if GetDepend(['RT_USING_I2C']):
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2c.c']
+    
+if GetDepend(['RT_USING_SPI']):
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c']
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c'] 
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c']
+
+if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']):
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd.c']
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pcd_ex.c'] 
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_usb.c']
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_hcd.c']
+
+if GetDepend(['RT_USING_CAN']):
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_can.c']
+
+if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']):
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c']
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c']
+
+if GetDepend(['BSP_USING_ETH']):
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_eth.c']
+
+if GetDepend(['RT_USING_ADC']):
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c']
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c']
+
+if GetDepend(['RT_USING_RTC']):
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c']
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c']
+
+if GetDepend(['RT_USING_WDT']):
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c']
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_wwdg.c']
+
+if GetDepend(['RT_USING_SDIO']):
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_mmc.c']
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c']
+
+if GetDepend(['RT_USING_AUDIO']):
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_i2s.c']
+
+if GetDepend(['RT_USING_MTD_NOR']):
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nor.c']
+
+if GetDepend(['RT_USING_MTD_NAND']):
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nand.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c']
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c']
 
 path = [cwd + '/CMSIS/Device/ST/STM32F1xx/Include', 
-	cwd + '/STM32F1xx_HAL_Driver/Inc',
+    cwd + '/STM32F1xx_HAL_Driver/Inc',
     cwd + '/CMSIS/Include']
 
 if GetDepend(['RT_USING_RTT_CMSIS']):

bsp/stm32/libraries/STM32F4xx_HAL/SConscript

@@ -9,74 +9,92 @@ cwd = GetCurrentDir()
 src = Split('''
 CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c
 STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c
 STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cec.c
 STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c
 STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_crc.c
 STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp.c
 STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cryp_ex.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dac_ex.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dcmi_ex.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c
 STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma2d.c
 STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_fmpi2c_ex.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hash_ex.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_irda.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_ltdc_ex.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pccard.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c
 STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c
 STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c
 STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c
 STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c
 STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rng.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_smartcard.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spdifrx.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c
 STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sram.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c
-STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c
 ''')
 
+if GetDepend(['RT_USING_PIN']):
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c']
+    
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c']
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_usart.c']
+
+if GetDepend(['RT_USING_I2C']):
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c']
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c']
+
+if GetDepend(['RT_USING_SPI']):
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c']
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c']
+
+if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']):
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pccard.c']
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c'] 
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c']
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_hcd.c']
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c']
+
+if GetDepend(['RT_USING_CAN']):
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c']
+
+if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']):
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c']
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c']
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_lptim.c']
+
+if GetDepend(['BSP_USING_ETH']):
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c']
+
+if GetDepend(['RT_USING_ADC']):
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c']
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c']
+
+if GetDepend(['RT_USING_RTC']):
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c']
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c']
+
+if GetDepend(['RT_USING_WDT']):
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c']
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_wwdg.c']
+
+if GetDepend(['RT_USING_SDIO']):
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c']
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c']
+
+if GetDepend(['RT_USING_AUDIO']):
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s.c']
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2s_ex.c']
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai.c']
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sai_ex.c']
+
+if GetDepend(['RT_USING_MTD_NOR']):
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nor.c']
+
+if GetDepend(['RT_USING_MTD_NAND']):
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_nand.c']
+
+if GetDepend(['BSP_USING_SDRAM']):
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c']
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c']
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sdram.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c']
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c']
+    src += ['STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c']
+
 path = [cwd + '/STM32F4xx_HAL_Driver/Inc',
     cwd + '/CMSIS/Device/ST/STM32F4xx/Include',
     cwd + '/CMSIS/Include']

bsp/stm32/libraries/STM32L4xx_HAL/SConscript

@@ -9,103 +9,86 @@ cwd = GetCurrentDir()
 src = Split('''
 CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c
 STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c
 STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_comp.c
 STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c
 STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc.c
 STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_crc_ex.c
 STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp.c
 STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cryp_ex.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dcmi.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dfsdm_ex.c
 STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma2d.c
 STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dsi.c
 STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_exti.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_firewall.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gfxmmu.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hash_ex.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_irda.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lcd.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ltdc_ex.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nand.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nor.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_opamp_ex.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_ospi.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c
 STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c
 STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr_ex.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c
 STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc.c
 STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rcc_ex.c
 STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd_ex.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smartcard_ex.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_smbus.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c
 STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sram.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_swpmi.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tsc.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart_ex.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_wwdg.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_adc.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_comp.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_crc.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_crs.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dac.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_dma2d.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_exti.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_fmc.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_gpio.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_i2c.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lptim.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_lpuart.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_opamp.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_pwr.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rcc.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rng.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_rtc.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_spi.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_swpmi.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_tim.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usart.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c
-STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_utils.c
 ''')
 
+if GetDepend(['RT_USING_PIN']):
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c']
+    
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart.c']
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c']
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart.c']
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_usart_ex.c']
+    
+if GetDepend(['RT_USING_I2C']):
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c.c']
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c']
+
+if GetDepend(['RT_USING_SPI']):
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi.c']
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c']
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_qspi.c']
+
+if GetDepend(['RT_USING_USB_HOST']) or GetDepend(['RT_USING_USB_DEVICE']):
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_hcd.c'] 
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd.c']
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c']
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_usb.c']
+
+if GetDepend(['RT_USING_CAN']):
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_can.c']
+
+if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']):
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_lptim.c']
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim.c']
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_tim_ex.c']
+
+if GetDepend(['RT_USING_ADC']):
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc.c']
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_adc_ex.c']
+
+if GetDepend(['RT_USING_RTC']):
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc.c']
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rtc_ex.c']
+
+if GetDepend(['RT_USING_WDT']):
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_iwdg.c']
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_wwdg.c']
+
+if GetDepend(['RT_USING_SDIO']):
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd.c']
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sd_ex.c']
+
+if GetDepend(['RT_USING_AUDIO']):
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai.c']
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_sai_ex.c']
+
+if GetDepend(['RT_USING_MTD_NOR']):
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nor.c']
+
+if GetDepend(['RT_USING_MTD_NAND']):
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_nand.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c']
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c']
+    src += ['STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c']
+
 path = [cwd + '/STM32L4xx_HAL_Driver/Inc',
     cwd + '/CMSIS/Device/ST/STM32L4xx/Include',
     cwd + '/CMSIS/Include']

bsp/stm32/libraries/templates/stm32f10x/.config

@@ -62,6 +62,7 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40000
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_ARM_CORTEX_M=y
 CONFIG_ARCH_ARM_CORTEX_M3=y
@@ -180,12 +181,14 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_LOGTRACE is not set
 # CONFIG_RT_USING_RYM is not set
 # CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
 
 #
 # ARM CMSIS
 #
 # CONFIG_RT_USING_CMSIS_OS is not set
 # CONFIG_RT_USING_RTT_CMSIS is not set
+# CONFIG_RT_USING_LWP is not set
 
 #
 # RT-Thread online packages
@@ -278,6 +281,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
 # CONFIG_PKG_USING_CMSIS is not set
 # CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
 
 #
 # peripheral libraries and drivers
@@ -340,7 +344,6 @@ CONFIG_SOC_STM32F103RB=y
 #
 CONFIG_BSP_USING_GPIO=y
 CONFIG_BSP_USING_UART1=y
-# CONFIG_BSP_UART_USING_DMA_RX is not set
 # CONFIG_BSP_USING_SPI1 is not set
 # CONFIG_BSP_SPI_USING_DMA is not set
 # CONFIG_BSP_USING_I2C1 is not set

bsp/stm32/libraries/templates/stm32f10x/applications/main.c

@@ -11,14 +11,23 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 #include <board.h>
+#include "drv_gpio.h"
+/* defined the LED0 pin: PB1 */
+#define LED0_PIN    GET_PIN(B, 1)
 
 int main(void)
 {
     int count = 1;
+    /* set LED0 pin mode to output */
+    rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
+
     while (count++)
     {
-        // rt_pin_write(LED0_PIN, !rt_pin_read(LED0_PIN));
+        rt_pin_write(LED0_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
+
     return RT_EOK;
 }

bsp/stm32/libraries/templates/stm32f10x/board/Kconfig

@@ -21,10 +21,6 @@ menu "On-chip Peripheral Drivers"
         select RT_USING_SERIAL
         default y
 
-    config BSP_UART_USING_DMA_RX
-        bool "Enable UART RX DMA support"
-        default n
-
     config BSP_USING_SPI1
         bool "Enable SPI1 BUS"
         select RT_USING_SPI

bsp/stm32/libraries/templates/stm32f10x/board/board.c

@@ -51,12 +51,3 @@ void MX_GPIO_Init(void)
   __HAL_RCC_GPIOA_CLK_ENABLE();
 
 }
-
-#ifdef RT_USING_PIN
-// int board_pin_init(void)
-// {
-//     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
-//     return 0;
-// }
-// INIT_BOARD_EXPORT(board_pin_init);
-#endif /* RT_USING_PIN */

bsp/stm32/libraries/templates/stm32f10x/board/board.h

@@ -15,12 +15,6 @@
 #include <stm32f1xx.h>
 #include "drv_common.h"
 
-#ifdef BSP_USING_GPIO
-#include "drv_gpio.h"
-/* Board Pin definitions */
-// #define LED0_PIN                       GET_PIN(C,  0)
-#endif
-
 /* Internal SRAM memory size[Kbytes] <8-64>, Default: 64*/
 #define STM32_SRAM_SIZE      20
 #define STM32_SRAM_END       (0x20000000 + STM32_SRAM_SIZE * 1024)

bsp/stm32/libraries/templates/stm32f10x/rtconfig.h

@@ -38,6 +38,7 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40000
 #define ARCH_ARM
 #define ARCH_ARM_CORTEX_M
 #define ARCH_ARM_CORTEX_M3

bsp/stm32/libraries/templates/stm32f4xx/.config

@@ -62,6 +62,7 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40000
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_ARM_CORTEX_M=y
 CONFIG_ARCH_ARM_CORTEX_M4=y
@@ -180,12 +181,14 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_LOGTRACE is not set
 # CONFIG_RT_USING_RYM is not set
 # CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
 
 #
 # ARM CMSIS
 #
 # CONFIG_RT_USING_CMSIS_OS is not set
 # CONFIG_RT_USING_RTT_CMSIS is not set
+# CONFIG_RT_USING_LWP is not set
 
 #
 # RT-Thread online packages
@@ -279,6 +282,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
 # CONFIG_PKG_USING_CMSIS is not set
 # CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
 
 #
 # peripheral libraries and drivers
@@ -341,7 +345,6 @@ CONFIG_SOC_STM32F407ZG=y
 #
 CONFIG_BSP_USING_GPIO=y
 CONFIG_BSP_USING_UART1=y
-# CONFIG_BSP_UART_USING_DMA_RX is not set
 # CONFIG_BSP_USING_SPI1 is not set
 # CONFIG_BSP_SPI_USING_DMA is not set
 # CONFIG_BSP_USING_I2C1 is not set

bsp/stm32/libraries/templates/stm32f4xx/applications/main.c

@@ -11,14 +11,23 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 #include <board.h>
+#include "drv_gpio.h"
+/* defined the LED0 pin: PB1 */
+#define LED0_PIN    GET_PIN(B, 1)
 
 int main(void)
 {
     int count = 1;
+    /* set LED0 pin mode to output */
+    rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
+
     while (count++)
     {
-        // rt_pin_write(LED0_PIN, !rt_pin_read(LED0_PIN));
+        rt_pin_write(LED0_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
+
     return RT_EOK;
 }

bsp/stm32/libraries/templates/stm32f4xx/board/Kconfig

@@ -21,10 +21,6 @@ menu "On-chip Peripheral Drivers"
         select RT_USING_SERIAL
         default y
 
-    config BSP_UART_USING_DMA_RX
-        bool "Enable UART RX DMA support"
-        default n
-
     config BSP_USING_SPI1
         bool "Enable SPI1 BUS"
         select RT_USING_SPI

bsp/stm32/libraries/templates/stm32f4xx/board/board.c

@@ -56,12 +56,3 @@ void MX_GPIO_Init(void)
   __HAL_RCC_GPIOA_CLK_ENABLE();
 
 }
-
-#ifdef RT_USING_PIN
-// int board_pin_init(void)
-// {
-//     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
-//     return 0;
-// }
-// INIT_BOARD_EXPORT(board_pin_init);
-#endif /* RT_USING_PIN */

bsp/stm32/libraries/templates/stm32f4xx/board/board.h

@@ -15,12 +15,6 @@
 #include <stm32f4xx.h>
 #include "drv_common.h"
 
-#ifdef BSP_USING_GPIO
-#include "drv_gpio.h"
-/* Board Pin definitions */
-// #define LED0_PIN                       GET_PIN(C,  0)
-#endif
-
 #define STM32_SRAM_SIZE           128
 #define STM32_SRAM_END            (0x20000000 + STM32_SRAM_SIZE * 1024)
 

bsp/stm32/libraries/templates/stm32f4xx/rtconfig.h

@@ -38,6 +38,7 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40000
 #define ARCH_ARM
 #define ARCH_ARM_CORTEX_M
 #define ARCH_ARM_CORTEX_M4

bsp/stm32/libraries/templates/stm32f7xx/.config

@@ -62,9 +62,10 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40000
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_ARM_CORTEX_M=y
-CONFIG_ARCH_ARM_CORTEX_M4=y
+CONFIG_ARCH_ARM_CORTEX_M7=y
 # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
 #
@@ -110,6 +111,7 @@ CONFIG_FINSH_ARG_MAX=10
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
@@ -179,12 +181,14 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_LOGTRACE is not set
 # CONFIG_RT_USING_RYM is not set
 # CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
 
 #
 # ARM CMSIS
 #
 # CONFIG_RT_USING_CMSIS_OS is not set
 # CONFIG_RT_USING_RTT_CMSIS is not set
+# CONFIG_RT_USING_LWP is not set
 
 #
 # RT-Thread online packages
@@ -278,6 +282,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
 # CONFIG_PKG_USING_CMSIS is not set
 # CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
 
 #
 # peripheral libraries and drivers
@@ -324,12 +329,12 @@ CONFIG_RT_USING_PIN=y
 #
 # CONFIG_PKG_USING_HELLO is not set
 CONFIG_SOC_FAMILY_STM32=y
-CONFIG_SOC_SERIES_STM32F4=y
+CONFIG_SOC_SERIES_STM32F7=y
 
 #
 # Hardware Drivers Config
 #
-CONFIG_SOC_STM32F407ZG=y
+CONFIG_SOC_STM32F767IG=y
 
 #
 # Onboard Peripheral Drivers
@@ -340,7 +345,6 @@ CONFIG_SOC_STM32F407ZG=y
 #
 CONFIG_BSP_USING_GPIO=y
 CONFIG_BSP_USING_UART1=y
-# CONFIG_BSP_UART_USING_DMA_RX is not set
 # CONFIG_BSP_USING_SPI1 is not set
 # CONFIG_BSP_SPI_USING_DMA is not set
 # CONFIG_BSP_USING_I2C1 is not set

bsp/stm32/libraries/templates/stm32f7xx/board/Kconfig

@@ -21,10 +21,6 @@ menu "On-chip Peripheral Drivers"
         select RT_USING_SERIAL
         default y
 
-    config BSP_UART_USING_DMA_RX
-        bool "Enable UART RX DMA support"
-        default n
-
     config BSP_USING_SPI1
         bool "Enable SPI1 BUS"
         select RT_USING_SPI

bsp/stm32/libraries/templates/stm32f7xx/rtconfig.h

@@ -39,6 +39,9 @@
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart1"
 #define RT_VER_NUM 0x40000
+#define ARCH_ARM
+#define ARCH_ARM_CORTEX_M
+#define ARCH_ARM_CORTEX_M7
 
 /* RT-Thread Components */
 
@@ -74,6 +77,7 @@
 #define RT_USING_DEVICE_IPC
 #define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
 #define RT_USING_PIN
 
 /* Using WiFi */
@@ -105,6 +109,9 @@
 /* Utilities */
 
 
+/* ARM CMSIS */
+
+
 /* RT-Thread online packages */
 
 /* IoT - internet of things */
@@ -149,6 +156,8 @@
 
 /* example package: hello */
 
+#define SOC_FAMILY_STM32
+#define SOC_SERIES_STM32F7
 
 /* Hardware Drivers Config */
 
@@ -156,8 +165,6 @@
 
 /* Onboard Peripheral Drivers */
 
-#define BSP_USING_USB_TO_USART
-
 /* On-chip Peripheral Drivers */
 
 #define BSP_USING_GPIO

bsp/stm32/libraries/templates/stm32l4xx/.config

@@ -62,6 +62,7 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=256
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40000
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_ARM_CORTEX_M=y
 CONFIG_ARCH_ARM_CORTEX_M4=y
@@ -180,12 +181,14 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_LOGTRACE is not set
 # CONFIG_RT_USING_RYM is not set
 # CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
 
 #
 # ARM CMSIS
 #
 # CONFIG_RT_USING_CMSIS_OS is not set
 # CONFIG_RT_USING_RTT_CMSIS is not set
+# CONFIG_RT_USING_LWP is not set
 
 #
 # RT-Thread online packages
@@ -279,6 +282,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
 # CONFIG_PKG_USING_CMSIS is not set
 # CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
 
 #
 # peripheral libraries and drivers
@@ -341,7 +345,6 @@ CONFIG_SOC_STM32L475VE=y
 #
 CONFIG_BSP_USING_GPIO=y
 CONFIG_BSP_USING_UART1=y
-# CONFIG_BSP_UART_USING_DMA_RX is not set
 # CONFIG_BSP_USING_SPI1 is not set
 # CONFIG_BSP_SPI_USING_DMA is not set
 # CONFIG_BSP_USING_I2C1 is not set

bsp/stm32/libraries/templates/stm32l4xx/applications/main.c

@@ -11,14 +11,23 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 #include <board.h>
+#include "drv_gpio.h"
+/* defined the LED0 pin: PB1 */
+#define LED0_PIN    GET_PIN(B, 1)
 
 int main(void)
 {
     int count = 1;
+    /* set LED0 pin mode to output */
+    rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
+
     while (count++)
     {
-        // rt_pin_write(LED0_PIN, !rt_pin_read(LED0_PIN));
+        rt_pin_write(LED0_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
+
     return RT_EOK;
 }

bsp/stm32/libraries/templates/stm32l4xx/board/Kconfig

@@ -21,10 +21,6 @@ menu "On-chip Peripheral Drivers"
         select RT_USING_SERIAL
         default y
 
-    config BSP_UART_USING_DMA_RX
-        bool "Enable UART RX DMA support"
-        default n
-
     config BSP_USING_SPI1
         bool "Enable SPI1 BUS"
         select RT_USING_SPI

bsp/stm32/libraries/templates/stm32l4xx/board/board.c

@@ -66,12 +66,3 @@ void MX_GPIO_Init(void)
   __HAL_RCC_GPIOA_CLK_ENABLE();
 
 }
-
-#ifdef RT_USING_PIN
-// int board_pin_init(void)
-// {
-//     rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
-//     return 0;
-// }
-// INIT_BOARD_EXPORT(board_pin_init);
-#endif /* RT_USING_PIN */

bsp/stm32/libraries/templates/stm32l4xx/board/board.h

@@ -15,12 +15,6 @@
 #include <stm32l4xx.h>
 #include "drv_common.h"
 
-#ifdef BSP_USING_GPIO
-#include "drv_gpio.h"
-/* Board Pin definitions */
-// #define LED0_PIN                       GET_PIN(C,  0)
-#endif
-
 #define STM32_SRAM_SIZE         96
 #define STM32_SRAM_END          (0x20000000 + STM32_SRAM_SIZE * 1024)
 

bsp/stm32/libraries/templates/stm32l4xx/rtconfig.h

@@ -38,6 +38,7 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 256
 #define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40000
 #define ARCH_ARM
 #define ARCH_ARM_CORTEX_M
 #define ARCH_ARM_CORTEX_M4

bsp/stm32/stm32f103-atk-nano/.config

@@ -7,6 +7,7 @@
 # RT-Thread Kernel
 #
 CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_SMP is not set
 CONFIG_RT_ALIGN_SIZE=4
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
 CONFIG_RT_THREAD_PRIORITY_32=y
@@ -15,6 +16,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32
 CONFIG_RT_TICK_PER_SECOND=1000
 CONFIG_RT_USING_OVERFLOW_CHECK=y
 CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=256
 # CONFIG_RT_USING_TIMER_SOFT is not set
@@ -61,9 +63,11 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40000
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_ARM_CORTEX_M=y
 CONFIG_ARCH_ARM_CORTEX_M3=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
 #
 # RT-Thread Components
@@ -114,10 +118,12 @@ CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_CPUTIME is not set
 # CONFIG_RT_USING_I2C is not set
 CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_MTD is not set
+# CONFIG_RT_USING_PM is not set
 # CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
 # CONFIG_RT_USING_SPI is not set
@@ -175,12 +181,15 @@ CONFIG_RT_USING_PIN=y
 #
 # CONFIG_RT_USING_LOGTRACE is not set
 # CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
 
 #
 # ARM CMSIS
 #
 # CONFIG_RT_USING_CMSIS_OS is not set
 # CONFIG_RT_USING_RTT_CMSIS is not set
+# CONFIG_RT_USING_LWP is not set
 
 #
 # RT-Thread online packages
@@ -247,7 +256,6 @@ CONFIG_RT_USING_PIN=y
 #
 # CONFIG_PKG_USING_OPENMV is not set
 # CONFIG_PKG_USING_MUPDF is not set
-# CONFIG_PKG_USING_BEEPPLAYER is not set
 
 #
 # tools packages
@@ -274,6 +282,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
 # CONFIG_PKG_USING_CMSIS is not set
 # CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
 
 #
 # peripheral libraries and drivers
@@ -288,6 +297,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_BUTTON is not set
 # CONFIG_PKG_USING_MPU6XXX is not set
 # CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
 
 #
 # miscellaneous packages
@@ -303,10 +313,6 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_DSTR is not set
 # CONFIG_PKG_USING_TINYFRAME is not set
 
-#
-# sample package
-#
-
 #
 # samples: kernel and components samples
 #
@@ -314,10 +320,6 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
 # CONFIG_PKG_USING_NETWORK_SAMPLES is not set
 # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
-
-#
-# example package: hello
-#
 # CONFIG_PKG_USING_HELLO is not set
 CONFIG_SOC_FAMILY_STM32=y
 CONFIG_SOC_SERIES_STM32F1=y
@@ -330,10 +332,10 @@ CONFIG_SOC_STM32F103RB=y
 #
 # Onboard Peripheral Drivers
 #
-
-#
-# Offboard Peripheral Drivers
-#
+CONFIG_BSP_USING_USB_TO_USART=y
+# CONFIG_BSP_USING_EEPROM is not set
+# CONFIG_BSP_USING_SPI_FLASH is not set
+# CONFIG_BSP_USING_POT is not set
 
 #
 # On-chip Peripheral Drivers
@@ -343,7 +345,16 @@ CONFIG_BSP_USING_UART1=y
 # CONFIG_BSP_USING_UART2 is not set
 # CONFIG_BSP_USING_UART3 is not set
 # CONFIG_BSP_UART_USING_DMA_RX is not set
+# CONFIG_BSP_USING_TIM is not set
 # CONFIG_BSP_USING_SPI1 is not set
 # CONFIG_BSP_USING_SPI2 is not set
 # CONFIG_BSP_SPI_USING_DMA is not set
 # CONFIG_BSP_USING_I2C1 is not set
+# CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
+# CONFIG_BSP_USING_ONCHIP_RTC is not set
+# CONFIG_BSP_USING_WDT is not set
+
+#
+# Board extended module Drivers
+#

bsp/stm32/stm32f103-atk-nano/applications/main.c

@@ -11,14 +11,23 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 #include <board.h>
+#include "drv_gpio.h"
+/* defined the LED0 pin: PC0 */
+#define LED0_PIN    GET_PIN(C, 0)
 
 int main(void)
 {
     int count = 1;
+    /* set LED0 pin mode to output */
+    rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
+
     while (count++)
     {
-        rt_pin_write(LED0_PIN, !rt_pin_read(LED0_PIN));
+        rt_pin_write(LED0_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
+
     return RT_EOK;
 }

bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Inc/main.h

@@ -70,6 +70,8 @@ extern "C" {
 
 /* USER CODE END EM */
 
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+
 /* Exported functions prototypes ---------------------------------------------*/
 void Error_Handler(void);
 

bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h

@@ -78,7 +78,7 @@
 /*#define HAL_SMARTCARD_MODULE_ENABLED   */
 #define HAL_SPI_MODULE_ENABLED
 /*#define HAL_SRAM_MODULE_ENABLED   */
-/*#define HAL_TIM_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
 #define HAL_UART_MODULE_ENABLED
 /*#define HAL_USART_MODULE_ENABLED   */
 /*#define HAL_WWDG_MODULE_ENABLED   */

bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src/main.c

@@ -70,6 +70,10 @@ RTC_HandleTypeDef hrtc;
 
 SPI_HandleTypeDef hspi2;
 
+TIM_HandleTypeDef htim2;
+TIM_HandleTypeDef htim3;
+TIM_HandleTypeDef htim4;
+
 UART_HandleTypeDef huart1;
 
 /* USER CODE BEGIN PV */
@@ -85,6 +89,9 @@ static void MX_SPI2_Init(void);
 static void MX_RTC_Init(void);
 static void MX_IWDG_Init(void);
 static void MX_ADC1_Init(void);
+static void MX_TIM2_Init(void);
+static void MX_TIM3_Init(void);
+static void MX_TIM4_Init(void);
 /* USER CODE BEGIN PFP */
 /* Private function prototypes -----------------------------------------------*/
 
@@ -128,6 +135,9 @@ int main(void)
   MX_RTC_Init();
   MX_IWDG_Init();
   MX_ADC1_Init();
+  MX_TIM2_Init();
+  MX_TIM3_Init();
+  MX_TIM4_Init();
   /* USER CODE BEGIN 2 */
 
   /* USER CODE END 2 */
@@ -186,7 +196,7 @@ void SystemClock_Config(void)
   }
   PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC;
   PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
-  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV2;
+  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
   if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
   {
     Error_Handler();
@@ -334,6 +344,159 @@ static void MX_SPI2_Init(void)
 
 }
 
+/**
+  * @brief TIM2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM2_Init(void)
+{
+
+  /* USER CODE BEGIN TIM2_Init 0 */
+
+  /* USER CODE END TIM2_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM2_Init 1 */
+
+  /* USER CODE END TIM2_Init 1 */
+  htim2.Instance = TIM2;
+  htim2.Init.Prescaler = 0;
+  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim2.Init.Period = 0;
+  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM2_Init 2 */
+
+  /* USER CODE END TIM2_Init 2 */
+
+}
+
+/**
+  * @brief TIM3 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM3_Init(void)
+{
+
+  /* USER CODE BEGIN TIM3_Init 0 */
+
+  /* USER CODE END TIM3_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+  TIM_OC_InitTypeDef sConfigOC = {0};
+
+  /* USER CODE BEGIN TIM3_Init 1 */
+
+  /* USER CODE END TIM3_Init 1 */
+  htim3.Instance = TIM3;
+  htim3.Init.Prescaler = 0;
+  htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim3.Init.Period = 0;
+  htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigOC.OCMode = TIM_OCMODE_PWM1;
+  sConfigOC.Pulse = 0;
+  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
+  if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM3_Init 2 */
+
+  /* USER CODE END TIM3_Init 2 */
+  HAL_TIM_MspPostInit(&htim3);
+
+}
+
+/**
+  * @brief TIM4 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM4_Init(void)
+{
+
+  /* USER CODE BEGIN TIM4_Init 0 */
+
+  /* USER CODE END TIM4_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM4_Init 1 */
+
+  /* USER CODE END TIM4_Init 1 */
+  htim4.Instance = TIM4;
+  htim4.Init.Prescaler = 0;
+  htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim4.Init.Period = 0;
+  htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM4_Init 2 */
+
+  /* USER CODE END TIM4_Init 2 */
+
+}
+
 /**
   * @brief USART1 Initialization Function
   * @param None

bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c

@@ -78,7 +78,9 @@
 /* USER CODE BEGIN 0 */
 
 /* USER CODE END 0 */
-/**
+                        
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+                    /**
   * Initializes the Global MSP.
   */
 void HAL_MspInit(void)
@@ -287,6 +289,125 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
 
 }
 
+/**
+* @brief TIM_Base MSP Initialization
+* This function configures the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
+{
+
+  if(htim_base->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspInit 0 */
+
+  /* USER CODE END TIM2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM2_CLK_ENABLE();
+  /* USER CODE BEGIN TIM2_MspInit 1 */
+
+  /* USER CODE END TIM2_MspInit 1 */
+  }
+  else if(htim_base->Instance==TIM3)
+  {
+  /* USER CODE BEGIN TIM3_MspInit 0 */
+
+  /* USER CODE END TIM3_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM3_CLK_ENABLE();
+  /* USER CODE BEGIN TIM3_MspInit 1 */
+
+  /* USER CODE END TIM3_MspInit 1 */
+  }
+  else if(htim_base->Instance==TIM4)
+  {
+  /* USER CODE BEGIN TIM4_MspInit 0 */
+
+  /* USER CODE END TIM4_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM4_CLK_ENABLE();
+  /* USER CODE BEGIN TIM4_MspInit 1 */
+
+  /* USER CODE END TIM4_MspInit 1 */
+  }
+
+}
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(htim->Instance==TIM3)
+  {
+  /* USER CODE BEGIN TIM3_MspPostInit 0 */
+
+  /* USER CODE END TIM3_MspPostInit 0 */
+  
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    /**TIM3 GPIO Configuration    
+    PC6     ------> TIM3_CH1
+    PC7     ------> TIM3_CH2 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    __HAL_AFIO_REMAP_TIM3_ENABLE();
+
+  /* USER CODE BEGIN TIM3_MspPostInit 1 */
+
+  /* USER CODE END TIM3_MspPostInit 1 */
+  }
+
+}
+/**
+* @brief TIM_Base MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
+{
+
+  if(htim_base->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspDeInit 0 */
+
+  /* USER CODE END TIM2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM2_CLK_DISABLE();
+  /* USER CODE BEGIN TIM2_MspDeInit 1 */
+
+  /* USER CODE END TIM2_MspDeInit 1 */
+  }
+  else if(htim_base->Instance==TIM3)
+  {
+  /* USER CODE BEGIN TIM3_MspDeInit 0 */
+
+  /* USER CODE END TIM3_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM3_CLK_DISABLE();
+  /* USER CODE BEGIN TIM3_MspDeInit 1 */
+
+  /* USER CODE END TIM3_MspDeInit 1 */
+  }
+  else if(htim_base->Instance==TIM4)
+  {
+  /* USER CODE BEGIN TIM4_MspDeInit 0 */
+
+  /* USER CODE END TIM4_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM4_CLK_DISABLE();
+  /* USER CODE BEGIN TIM4_MspDeInit 1 */
+
+  /* USER CODE END TIM4_MspDeInit 1 */
+  }
+
+}
+
 /**
 * @brief UART MSP Initialization
 * This function configures the hardware resources used in this example

bsp/stm32/stm32f103-atk-nano/board/CubeMX_Config/stm32f103rbt6.ioc

@@ -10,31 +10,39 @@ KeepUserPlacement=false
 Mcu.Family=STM32F1
 Mcu.IP0=ADC1
 Mcu.IP1=IWDG
+Mcu.IP10=USART1
 Mcu.IP2=NVIC
 Mcu.IP3=RCC
 Mcu.IP4=RTC
 Mcu.IP5=SPI2
 Mcu.IP6=SYS
-Mcu.IP7=USART1
-Mcu.IPNb=8
+Mcu.IP7=TIM2
+Mcu.IP8=TIM3
+Mcu.IP9=TIM4
+Mcu.IPNb=11
 Mcu.Name=STM32F103R(8-B)Tx
 Mcu.Package=LQFP64
 Mcu.Pin0=PC14-OSC32_IN
 Mcu.Pin1=PC15-OSC32_OUT
-Mcu.Pin10=PA13
-Mcu.Pin11=PA14
-Mcu.Pin12=VP_IWDG_VS_IWDG
-Mcu.Pin13=VP_RTC_VS_RTC_Activate
-Mcu.Pin14=VP_SYS_VS_Systick
+Mcu.Pin10=PA9
+Mcu.Pin11=PA10
+Mcu.Pin12=PA13
+Mcu.Pin13=PA14
+Mcu.Pin14=VP_IWDG_VS_IWDG
+Mcu.Pin15=VP_RTC_VS_RTC_Activate
+Mcu.Pin16=VP_SYS_VS_Systick
+Mcu.Pin17=VP_TIM2_VS_ClockSourceINT
+Mcu.Pin18=VP_TIM3_VS_ClockSourceINT
+Mcu.Pin19=VP_TIM4_VS_ClockSourceINT
 Mcu.Pin2=PD0-OSC_IN
 Mcu.Pin3=PD1-OSC_OUT
 Mcu.Pin4=PB1
 Mcu.Pin5=PB13
 Mcu.Pin6=PB14
 Mcu.Pin7=PB15
-Mcu.Pin8=PA9
-Mcu.Pin9=PA10
-Mcu.PinsNb=15
+Mcu.Pin8=PC6
+Mcu.Pin9=PC7
+Mcu.PinsNb=20
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32F103RBTx
@@ -70,6 +78,10 @@ PC14-OSC32_IN.Mode=LSE-External-Oscillator
 PC14-OSC32_IN.Signal=RCC_OSC32_IN
 PC15-OSC32_OUT.Mode=LSE-External-Oscillator
 PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
+PC6.Locked=true
+PC6.Signal=S_TIM3_CH1
+PC7.Locked=true
+PC7.Signal=S_TIM3_CH2
 PCC.Checker=false
 PCC.Line=STM32F103
 PCC.MCU=STM32F103R(8-B)Tx
@@ -109,8 +121,9 @@ ProjectManager.StackSize=0x400
 ProjectManager.TargetToolchain=MDK-ARM V5
 ProjectManager.ToolChainLocation=
 ProjectManager.UnderRoot=false
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI2_Init-SPI2-false-HAL-true,5-MX_RTC_Init-RTC-false-HAL-true,6-MX_IWDG_Init-IWDG-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true
-RCC.ADCFreqValue=36000000
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_SPI2_Init-SPI2-false-HAL-true,5-MX_RTC_Init-RTC-false-HAL-true,6-MX_IWDG_Init-IWDG-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true,8-MX_TIM2_Init-TIM2-false-HAL-true,9-MX_TIM3_Init-TIM3-false-HAL-true,10-MX_TIM4_Init-TIM4-false-HAL-true
+RCC.ADCFreqValue=12000000
+RCC.ADCPresc=RCC_ADCPCLK2_DIV6
 RCC.AHBFreq_Value=72000000
 RCC.APB1CLKDivider=RCC_HCLK_DIV2
 RCC.APB1Freq_Value=36000000
@@ -120,7 +133,7 @@ RCC.APB2TimFreq_Value=72000000
 RCC.FCLKCortexFreq_Value=72000000
 RCC.FamilyName=M
 RCC.HCLKFreq_Value=72000000
-RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,RTCClockSelection,RTCFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
+RCC.IPParameters=ADCFreqValue,ADCPresc,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,PLLSourceVirtual,RTCClockSelection,RTCFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
 RCC.MCOFreq_Value=72000000
 RCC.PLLCLKFreq_Value=72000000
 RCC.PLLMCOFreq_Value=36000000
@@ -135,11 +148,18 @@ RCC.USBFreq_Value=72000000
 RCC.VCOOutput2Freq_Value=8000000
 SH.ADCx_IN9.0=ADC1_IN9,IN9
 SH.ADCx_IN9.ConfNb=1
+SH.S_TIM3_CH1.0=TIM3_CH1,PWM Generation1 CH1
+SH.S_TIM3_CH1.ConfNb=1
+SH.S_TIM3_CH2.0=TIM3_CH2,PWM Generation2 CH2
+SH.S_TIM3_CH2.ConfNb=1
 SPI2.CalculateBaudRate=18.0 MBits/s
 SPI2.Direction=SPI_DIRECTION_2LINES
 SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
 SPI2.Mode=SPI_MODE_MASTER
 SPI2.VirtualType=VM_MASTER
+TIM3.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
+TIM3.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2
+TIM3.IPParameters=Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2
 USART1.IPParameters=VirtualMode
 USART1.VirtualMode=VM_ASYNC
 VP_IWDG_VS_IWDG.Mode=IWDG_Activate
@@ -148,4 +168,10 @@ VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
 VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
 VP_SYS_VS_Systick.Mode=SysTick
 VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+VP_TIM2_VS_ClockSourceINT.Mode=Internal
+VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT
+VP_TIM3_VS_ClockSourceINT.Mode=Internal
+VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT
+VP_TIM4_VS_ClockSourceINT.Mode=Internal
+VP_TIM4_VS_ClockSourceINT.Signal=TIM4_VS_ClockSourceINT
 board=custom

bsp/stm32/stm32f103-atk-nano/board/Kconfig

@@ -54,9 +54,42 @@ menu "On-chip Peripheral Drivers"
         select RT_USING_SERIAL
         default n
 
-    config BSP_UART_USING_DMA_RX
-        bool "Enable UART RX DMA support"
+    menuconfig BSP_USING_TIM
+        bool "Enable timer"
         default n
+        select RT_USING_HWTIMER
+        if BSP_USING_TIM
+            config BSP_USING_TIM2
+                bool "Enable TIM2"
+                default n
+
+            config BSP_USING_TIM3
+                bool "Enable TIM3"
+                default n
+
+            config BSP_USING_TIM4
+                bool "Enable TIM4"
+                default n
+        endif
+
+    menuconfig BSP_USING_PWM
+        bool "Enable pwm"
+        default n
+        select RT_USING_PWM
+        if BSP_USING_PWM
+        menuconfig BSP_USING_PWM3
+            bool "Enable timer3 output pwm"
+            default n
+            if BSP_USING_PWM3
+                config BSP_USING_PWM3_CH1
+                    bool "Enable PWM3 channel1"
+                    default n
+
+                config BSP_USING_PWM3_CH2
+                    bool "Enable PWM3 channel2"
+                    default n
+            endif
+        endif
 
     config BSP_USING_SPI1
         bool "Enable SPI1 BUS"
@@ -101,7 +134,6 @@ menu "On-chip Peripheral Drivers"
             config BSP_USING_ADC2
                 bool "Enable ADC2"
                 default n
-
         endif
 
     config BSP_USING_ON_CHIP_FLASH

bsp/stm32/stm32f103-atk-nano/board/board.c

@@ -14,13 +14,17 @@ void SystemClock_Config(void)
 {
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 
   /**Initializes the CPU, AHB and APB busses clocks 
   */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE
+                              |RCC_OSCILLATORTYPE_LSE;
   RCC_OscInitStruct.HSEState = RCC_HSE_ON;
   RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
+  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+  RCC_OscInitStruct.LSIState = RCC_LSI_ON;
   RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
   RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
@@ -41,6 +45,13 @@ void SystemClock_Config(void)
   {
     Error_Handler();
   }
+  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_ADC;
+  PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
+  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+  {
+    Error_Handler();
+  }
 }
 
 void MX_GPIO_Init(void)
@@ -51,11 +62,4 @@ void MX_GPIO_Init(void)
   __HAL_RCC_GPIOA_CLK_ENABLE();
 
 }
-#ifdef RT_USING_PIN
-int board_pin_init(void)
-{
-    rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
-    return 0;
-}
-INIT_BOARD_EXPORT(board_pin_init);
-#endif /* RT_USING_PIN */
+

bsp/stm32/stm32f103-atk-nano/board/board.h

@@ -15,13 +15,6 @@
 #include <stm32f1xx.h>
 #include "drv_common.h"
 
-#ifdef BSP_USING_GPIO
-#include "drv_gpio.h"
-/* Board Pin definitions */
-#define LED0_PIN                       GET_PIN(C,  0)
-#define LED1_PIN                       GET_PIN(C,  1)
-#endif
-
 #define STM32_FLASH_START_ADRESS     ((uint32_t)0x08000000)
 #define STM32_FLASH_SIZE             (128 * 1024)
 #define STM32_FLASH_END_ADDRESS      ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))

bsp/stm32/stm32f103-atk-nano/rtconfig.h

@@ -13,6 +13,7 @@
 #define RT_TICK_PER_SECOND 1000
 #define RT_USING_OVERFLOW_CHECK
 #define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
 #define RT_IDEL_HOOK_LIST_SIZE 4
 #define IDLE_THREAD_STACK_SIZE 256
 #define RT_DEBUG
@@ -38,6 +39,7 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40000
 #define ARCH_ARM
 #define ARCH_ARM_CORTEX_M
 #define ARCH_ARM_CORTEX_M3
@@ -148,13 +150,8 @@
 /* miscellaneous packages */
 
 
-/* sample package */
-
 /* samples: kernel and components samples */
 
-
-/* example package: hello */
-
 #define SOC_FAMILY_STM32
 #define SOC_SERIES_STM32F1
 
@@ -164,11 +161,14 @@
 
 /* Onboard Peripheral Drivers */
 
-/* Offboard Peripheral Drivers */
+#define BSP_USING_USB_TO_USART
 
 /* On-chip Peripheral Drivers */
 
 #define BSP_USING_GPIO
 #define BSP_USING_UART1
 
+/* Board extended module Drivers */
+
+
 #endif

bsp/stm32/stm32f103-fire-arbitrary/.config

@@ -7,6 +7,7 @@
 # RT-Thread Kernel
 #
 CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_SMP is not set
 CONFIG_RT_ALIGN_SIZE=4
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
 CONFIG_RT_THREAD_PRIORITY_32=y
@@ -15,6 +16,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32
 CONFIG_RT_TICK_PER_SECOND=1000
 CONFIG_RT_USING_OVERFLOW_CHECK=y
 CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=256
 # CONFIG_RT_USING_TIMER_SOFT is not set
@@ -61,9 +63,11 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40000
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_ARM_CORTEX_M=y
 CONFIG_ARCH_ARM_CORTEX_M3=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
 #
 # RT-Thread Components
@@ -114,10 +118,12 @@ CONFIG_RT_SERIAL_USING_DMA=y
 # CONFIG_RT_USING_CPUTIME is not set
 # CONFIG_RT_USING_I2C is not set
 CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_MTD is not set
+# CONFIG_RT_USING_PM is not set
 # CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
 # CONFIG_RT_USING_SPI is not set
@@ -175,12 +181,15 @@ CONFIG_RT_USING_LIBC=y
 #
 # CONFIG_RT_USING_LOGTRACE is not set
 # CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
 
 #
 # ARM CMSIS
 #
 # CONFIG_RT_USING_CMSIS_OS is not set
 # CONFIG_RT_USING_RTT_CMSIS is not set
+# CONFIG_RT_USING_LWP is not set
 
 #
 # RT-Thread online packages
@@ -247,7 +256,6 @@ CONFIG_RT_USING_LIBC=y
 #
 # CONFIG_PKG_USING_OPENMV is not set
 # CONFIG_PKG_USING_MUPDF is not set
-# CONFIG_PKG_USING_BEEPPLAYER is not set
 
 #
 # tools packages
@@ -274,6 +282,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
 # CONFIG_PKG_USING_CMSIS is not set
 # CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
 
 #
 # peripheral libraries and drivers
@@ -288,6 +297,7 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_BUTTON is not set
 # CONFIG_PKG_USING_MPU6XXX is not set
 # CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
 
 #
 # miscellaneous packages
@@ -303,10 +313,6 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_DSTR is not set
 # CONFIG_PKG_USING_TINYFRAME is not set
 
-#
-# sample package
-#
-
 #
 # samples: kernel and components samples
 #
@@ -314,10 +320,6 @@ CONFIG_RT_USING_LIBC=y
 # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
 # CONFIG_PKG_USING_NETWORK_SAMPLES is not set
 # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
-
-#
-# example package: hello
-#
 # CONFIG_PKG_USING_HELLO is not set
 CONFIG_SOC_FAMILY_STM32=y
 CONFIG_SOC_SERIES_STM32F1=y
@@ -330,10 +332,13 @@ CONFIG_SOC_STM32F103ZE=y
 #
 # Onboard Peripheral Drivers
 #
-
-#
-# Offboard Peripheral Drivers
-#
+CONFIG_BSP_USING_USB_TO_USART=y
+# CONFIG_BSP_USING_RS485_OR_RS232 is not set
+# CONFIG_BSP_USING_SPI_FLASH is not set
+# CONFIG_BSP_USING_POT is not set
+# CONFIG_BSP_USING_EEPROM is not set
+# CONFIG_BSP_USING_ETH is not set
+# CONFIG_BSP_USING_SDCARD is not set
 
 #
 # On-chip Peripheral Drivers
@@ -343,8 +348,18 @@ CONFIG_BSP_USING_UART1=y
 # CONFIG_BSP_USING_UART2 is not set
 # CONFIG_BSP_USING_UART3 is not set
 # CONFIG_BSP_UART_USING_DMA_RX is not set
+# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
 # CONFIG_BSP_USING_SPI1 is not set
 # CONFIG_BSP_USING_SPI2 is not set
 # CONFIG_BSP_USING_SPI3 is not set
 # CONFIG_BSP_SPI_USING_DMA is not set
 # CONFIG_BSP_USING_I2C1 is not set
+# CONFIG_BSP_USING_TIM is not set
+# CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_ONCHIP_RTC is not set
+# CONFIG_BSP_USING_WDT is not set
+# CONFIG_BSP_USING_SDIO is not set
+
+#
+# Board extended module Drivers
+#

bsp/stm32/stm32f103-fire-arbitrary/applications/main.c

@@ -11,14 +11,23 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 #include <board.h>
+#include "drv_gpio.h"
+/* defined the LED0 pin: PF7 */
+#define LED0_PIN    GET_PIN(F, 7)
 
 int main(void)
 {
     int count = 1;
+    /* set LED0 pin mode to output */
+    rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
+
     while (count++)
     {
-        rt_pin_write(LED0_PIN, !rt_pin_read(LED0_PIN));
+        rt_pin_write(LED0_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED0_PIN, PIN_LOW);
         rt_thread_mdelay(500);
     }
+
     return RT_EOK;
 }

bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/.mxproject

 [PreviousGenFiles]
-HeaderPath=E:/workspace/BspFramework/rt-thread/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Inc
+HeaderPath=D:/BspFramework/rt-thread/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Inc
 HeaderFiles=stm32f1xx_it.h;stm32f1xx_hal_conf.h;main.h;
-SourcePath=E:/workspace/BspFramework/rt-thread/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src
+SourcePath=D:/BspFramework/rt-thread/bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src
 SourceFiles=stm32f1xx_it.c;stm32f1xx_hal_msp.c;main.c;
 
 [PreviousLibFiles]
-LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;
+LibFiles=Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_sdmmc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sd.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_adc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_iwdg.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rtc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_sdmmc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_sd.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_spi.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_tim_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_uart.h;Drivers/STM32F1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_def.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_gpio_ex.h;Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma_ex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_dma.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_cortex.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash.h;Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_flash_ex.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xe.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h;Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;
 
 [PreviousUsedKeilFiles]
-SourceFiles=..\Src\main.c;..\Src\stm32f1xx_it.c;..\Src\stm32f1xx_hal_msp.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;null;
+SourceFiles=..\Src\main.c;..\Src\stm32f1xx_it.c;..\Src\stm32f1xx_hal_msp.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_adc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_iwdg.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rtc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_sdmmc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sd.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_tim_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_uart.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_dma.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cortex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c;../Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio_ex.c;../\Src/system_stm32f1xx.c;../Drivers/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c;null;
 HeaderPath=..\Drivers\STM32F1xx_HAL_Driver\Inc;..\Drivers\STM32F1xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F1xx\Include;..\Drivers\CMSIS\Include;..\Inc;
 

bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Inc/main.h

@@ -70,6 +70,8 @@ extern "C" {
 
 /* USER CODE END EM */
 
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+
 /* Exported functions prototypes ---------------------------------------------*/
 void Error_Handler(void);
 

bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h

@@ -72,13 +72,13 @@
 /*#define HAL_PWR_MODULE_ENABLED   */
 /*#define HAL_RCC_MODULE_ENABLED   */
 #define HAL_RTC_MODULE_ENABLED
-/*#define HAL_SD_MODULE_ENABLED   */
+#define HAL_SD_MODULE_ENABLED
 /*#define HAL_MMC_MODULE_ENABLED   */
 /*#define HAL_SDRAM_MODULE_ENABLED   */
 /*#define HAL_SMARTCARD_MODULE_ENABLED   */
 #define HAL_SPI_MODULE_ENABLED
 /*#define HAL_SRAM_MODULE_ENABLED   */
-/*#define HAL_TIM_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
 #define HAL_UART_MODULE_ENABLED
 /*#define HAL_USART_MODULE_ENABLED   */
 /*#define HAL_WWDG_MODULE_ENABLED   */

bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src/main.c

@@ -68,9 +68,16 @@ IWDG_HandleTypeDef hiwdg;
 
 RTC_HandleTypeDef hrtc;
 
+SD_HandleTypeDef hsd;
+
 SPI_HandleTypeDef hspi1;
 SPI_HandleTypeDef hspi2;
 
+TIM_HandleTypeDef htim2;
+TIM_HandleTypeDef htim3;
+TIM_HandleTypeDef htim4;
+TIM_HandleTypeDef htim5;
+
 UART_HandleTypeDef huart1;
 UART_HandleTypeDef huart2;
 UART_HandleTypeDef huart3;
@@ -91,6 +98,11 @@ static void MX_USART3_UART_Init(void);
 static void MX_ADC1_Init(void);
 static void MX_RTC_Init(void);
 static void MX_IWDG_Init(void);
+static void MX_TIM2_Init(void);
+static void MX_TIM3_Init(void);
+static void MX_TIM4_Init(void);
+static void MX_TIM5_Init(void);
+static void MX_SDIO_SD_Init(void);
 /* USER CODE BEGIN PFP */
 /* Private function prototypes -----------------------------------------------*/
 
@@ -137,6 +149,11 @@ int main(void)
   MX_ADC1_Init();
   MX_RTC_Init();
   MX_IWDG_Init();
+  MX_TIM2_Init();
+  MX_TIM3_Init();
+  MX_TIM4_Init();
+  MX_TIM5_Init();
+  MX_SDIO_SD_Init();
   /* USER CODE BEGIN 2 */
 
   /* USER CODE END 2 */
@@ -305,6 +322,42 @@ static void MX_RTC_Init(void)
 
 }
 
+/**
+  * @brief SDIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SDIO_SD_Init(void)
+{
+
+  /* USER CODE BEGIN SDIO_Init 0 */
+
+  /* USER CODE END SDIO_Init 0 */
+
+  /* USER CODE BEGIN SDIO_Init 1 */
+
+  /* USER CODE END SDIO_Init 1 */
+  hsd.Instance = SDIO;
+  hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;
+  hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;
+  hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;
+  hsd.Init.BusWide = SDIO_BUS_WIDE_1B;
+  hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
+  hsd.Init.ClockDiv = 0;
+  if (HAL_SD_Init(&hsd) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN SDIO_Init 2 */
+
+  /* USER CODE END SDIO_Init 2 */
+
+}
+
 /**
   * @brief SPI1 Initialization Function
   * @param None
@@ -381,6 +434,208 @@ static void MX_SPI2_Init(void)
 
 }
 
+/**
+  * @brief TIM2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM2_Init(void)
+{
+
+  /* USER CODE BEGIN TIM2_Init 0 */
+
+  /* USER CODE END TIM2_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM2_Init 1 */
+
+  /* USER CODE END TIM2_Init 1 */
+  htim2.Instance = TIM2;
+  htim2.Init.Prescaler = 0;
+  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim2.Init.Period = 0;
+  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM2_Init 2 */
+
+  /* USER CODE END TIM2_Init 2 */
+
+}
+
+/**
+  * @brief TIM3 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM3_Init(void)
+{
+
+  /* USER CODE BEGIN TIM3_Init 0 */
+
+  /* USER CODE END TIM3_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+  TIM_OC_InitTypeDef sConfigOC = {0};
+
+  /* USER CODE BEGIN TIM3_Init 1 */
+
+  /* USER CODE END TIM3_Init 1 */
+  htim3.Instance = TIM3;
+  htim3.Init.Prescaler = 0;
+  htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim3.Init.Period = 0;
+  htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_TIM_PWM_Init(&htim3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigOC.OCMode = TIM_OCMODE_PWM1;
+  sConfigOC.Pulse = 0;
+  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
+  if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM3_Init 2 */
+
+  /* USER CODE END TIM3_Init 2 */
+  HAL_TIM_MspPostInit(&htim3);
+
+}
+
+/**
+  * @brief TIM4 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM4_Init(void)
+{
+
+  /* USER CODE BEGIN TIM4_Init 0 */
+
+  /* USER CODE END TIM4_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM4_Init 1 */
+
+  /* USER CODE END TIM4_Init 1 */
+  htim4.Instance = TIM4;
+  htim4.Init.Prescaler = 0;
+  htim4.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim4.Init.Period = 0;
+  htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM4_Init 2 */
+
+  /* USER CODE END TIM4_Init 2 */
+
+}
+
+/**
+  * @brief TIM5 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM5_Init(void)
+{
+
+  /* USER CODE BEGIN TIM5_Init 0 */
+
+  /* USER CODE END TIM5_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+
+  /* USER CODE BEGIN TIM5_Init 1 */
+
+  /* USER CODE END TIM5_Init 1 */
+  htim5.Instance = TIM5;
+  htim5.Init.Prescaler = 0;
+  htim5.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim5.Init.Period = 0;
+  htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim5) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM5_Init 2 */
+
+  /* USER CODE END TIM5_Init 2 */
+
+}
+
 /**
   * @brief USART1 Initialization Function
   * @param None
@@ -492,6 +747,7 @@ static void MX_GPIO_Init(void)
   __HAL_RCC_GPIOC_CLK_ENABLE();
   __HAL_RCC_GPIOA_CLK_ENABLE();
   __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
 
 }
 

bsp/stm32/stm32f103-fire-arbitrary/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c

@@ -78,7 +78,9 @@
 /* USER CODE BEGIN 0 */
 
 /* USER CODE END 0 */
-/**
+                        
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+                    /**
   * Initializes the Global MSP.
   */
 void HAL_MspInit(void)
@@ -214,6 +216,90 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
 
 }
 
+/**
+* @brief SD MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hsd: SD handle pointer
+* @retval None
+*/
+void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hsd->Instance==SDIO)
+  {
+  /* USER CODE BEGIN SDIO_MspInit 0 */
+
+  /* USER CODE END SDIO_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SDIO_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+    /**SDIO GPIO Configuration    
+    PC8     ------> SDIO_D0
+    PC9     ------> SDIO_D1
+    PC10     ------> SDIO_D2
+    PC11     ------> SDIO_D3
+    PC12     ------> SDIO_CK
+    PD2     ------> SDIO_CMD 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 
+                          |GPIO_PIN_12;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_2;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN SDIO_MspInit 1 */
+
+  /* USER CODE END SDIO_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief SD MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hsd: SD handle pointer
+* @retval None
+*/
+
+void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd)
+{
+
+  if(hsd->Instance==SDIO)
+  {
+  /* USER CODE BEGIN SDIO_MspDeInit 0 */
+
+  /* USER CODE END SDIO_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SDIO_CLK_DISABLE();
+  
+    /**SDIO GPIO Configuration    
+    PC8     ------> SDIO_D0
+    PC9     ------> SDIO_D1
+    PC10     ------> SDIO_D2
+    PC11     ------> SDIO_D3
+    PC12     ------> SDIO_CK
+    PD2     ------> SDIO_CMD 
+    */
+    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 
+                          |GPIO_PIN_12);
+
+    HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2);
+
+  /* USER CODE BEGIN SDIO_MspDeInit 1 */
+
+  /* USER CODE END SDIO_MspDeInit 1 */
+  }
+
+}
+
 /**
 * @brief SPI MSP Initialization
 * This function configures the hardware resources used in this example
@@ -334,6 +420,148 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
 
 }
 
+/**
+* @brief TIM_Base MSP Initialization
+* This function configures the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
+{
+
+  if(htim_base->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspInit 0 */
+
+  /* USER CODE END TIM2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM2_CLK_ENABLE();
+  /* USER CODE BEGIN TIM2_MspInit 1 */
+
+  /* USER CODE END TIM2_MspInit 1 */
+  }
+  else if(htim_base->Instance==TIM3)
+  {
+  /* USER CODE BEGIN TIM3_MspInit 0 */
+
+  /* USER CODE END TIM3_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM3_CLK_ENABLE();
+  /* USER CODE BEGIN TIM3_MspInit 1 */
+
+  /* USER CODE END TIM3_MspInit 1 */
+  }
+  else if(htim_base->Instance==TIM4)
+  {
+  /* USER CODE BEGIN TIM4_MspInit 0 */
+
+  /* USER CODE END TIM4_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM4_CLK_ENABLE();
+  /* USER CODE BEGIN TIM4_MspInit 1 */
+
+  /* USER CODE END TIM4_MspInit 1 */
+  }
+  else if(htim_base->Instance==TIM5)
+  {
+  /* USER CODE BEGIN TIM5_MspInit 0 */
+
+  /* USER CODE END TIM5_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM5_CLK_ENABLE();
+  /* USER CODE BEGIN TIM5_MspInit 1 */
+
+  /* USER CODE END TIM5_MspInit 1 */
+  }
+
+}
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(htim->Instance==TIM3)
+  {
+  /* USER CODE BEGIN TIM3_MspPostInit 0 */
+
+  /* USER CODE END TIM3_MspPostInit 0 */
+  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**TIM3 GPIO Configuration    
+    PB0     ------> TIM3_CH3
+    PB1     ------> TIM3_CH4
+    PB5     ------> TIM3_CH2 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    __HAL_AFIO_REMAP_TIM3_PARTIAL();
+
+  /* USER CODE BEGIN TIM3_MspPostInit 1 */
+
+  /* USER CODE END TIM3_MspPostInit 1 */
+  }
+
+}
+/**
+* @brief TIM_Base MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param htim_base: TIM_Base handle pointer
+* @retval None
+*/
+
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
+{
+
+  if(htim_base->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspDeInit 0 */
+
+  /* USER CODE END TIM2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM2_CLK_DISABLE();
+  /* USER CODE BEGIN TIM2_MspDeInit 1 */
+
+  /* USER CODE END TIM2_MspDeInit 1 */
+  }
+  else if(htim_base->Instance==TIM3)
+  {
+  /* USER CODE BEGIN TIM3_MspDeInit 0 */
+
+  /* USER CODE END TIM3_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM3_CLK_DISABLE();
+  /* USER CODE BEGIN TIM3_MspDeInit 1 */
+
+  /* USER CODE END TIM3_MspDeInit 1 */
+  }
+  else if(htim_base->Instance==TIM4)
+  {
+  /* USER CODE BEGIN TIM4_MspDeInit 0 */
+
+  /* USER CODE END TIM4_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM4_CLK_DISABLE();
+  /* USER CODE BEGIN TIM4_MspDeInit 1 */
+
+  /* USER CODE END TIM4_MspDeInit 1 */
+  }
+  else if(htim_base->Instance==TIM5)
+  {
+  /* USER CODE BEGIN TIM5_MspDeInit 0 */
+
+  /* USER CODE END TIM5_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM5_CLK_DISABLE();
+  /* USER CODE BEGIN TIM5_MspDeInit 1 */
+
+  /* USER CODE END TIM5_MspDeInit 1 */
+  }
+
+}
+
 /**
 * @brief UART MSP Initialization
 * This function configures the hardware resources used in this example

bsp/stm32/stm32f103-fire-arbitrary/board/SConscript

@@ -18,6 +18,9 @@ if GetDepend(['BSP_USING_ETH']):
 if GetDepend(['BSP_USING_SPI_FLASH']):
     src += Glob('ports/spi_flash_init.c')
 
+if GetDepend(['BSP_USING_SDCARD']):
+    src += Glob('ports/sdcard_port.c')
+
 path =  [cwd]
 path += [cwd + '/CubeMX_Config/Inc']
 path += [cwd + '/ports']

bsp/stm32/stm32f103-fire-arbitrary/board/board.h

@@ -15,13 +15,6 @@
 #include <stm32f1xx.h>
 #include "drv_common.h"
 
-#ifdef BSP_USING_GPIO
-#include "drv_gpio.h"
-/* Board Pin definitions */
-#define LED0_PIN                       GET_PIN(F, 7)
-#define LED1_PIN                       GET_PIN(F, 8)
-#endif
-
 /* Internal SRAM memory size[Kbytes] <8-64>, Default: 64*/
 #define STM32_SRAM_SIZE      64
 #define STM32_SRAM_END       (0x20000000 + STM32_SRAM_SIZE * 1024)

bsp/stm32/stm32f103-fire-arbitrary/rtconfig.h

@@ -13,6 +13,7 @@
 #define RT_TICK_PER_SECOND 1000
 #define RT_USING_OVERFLOW_CHECK
 #define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
 #define RT_IDEL_HOOK_LIST_SIZE 4
 #define IDLE_THREAD_STACK_SIZE 256
 #define RT_DEBUG
@@ -38,6 +39,7 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40000
 #define ARCH_ARM
 #define ARCH_ARM_CORTEX_M
 #define ARCH_ARM_CORTEX_M3
@@ -149,13 +151,8 @@
 /* miscellaneous packages */
 
 
-/* sample package */
-
 /* samples: kernel and components samples */
 
-
-/* example package: hello */
-
 #define SOC_FAMILY_STM32
 #define SOC_SERIES_STM32F1
 
@@ -165,11 +162,14 @@
 
 /* Onboard Peripheral Drivers */
 
-/* Offboard Peripheral Drivers */
+#define BSP_USING_USB_TO_USART
 
 /* On-chip Peripheral Drivers */
 
 #define BSP_USING_GPIO
 #define BSP_USING_UART1
 
+/* Board extended module Drivers */
+
+
 #endif

bsp/stm32/stm32f407-atk-explorer/board/CubeMX_Config/.mxproject

@@ -5,9 +5,9 @@ SourcePath=E:/workspace/BspFramework/rt-thread/bsp/stm32/stm32f407-atk-explorer/
 SourceFiles=stm32f4xx_it.c;stm32f4xx_hal_msp.c;main.c;
 
 [PreviousLibFiles]
-LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;
+LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_eth.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_iwdg.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_sdmmc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_sd.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/arm_common_tables.h;Drivers/CMSIS/Include/arm_const_structs.h;Drivers/CMSIS/Include/arm_math.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armcc_V6.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cmFunc.h;Drivers/CMSIS/Include/core_cmInstr.h;Drivers/CMSIS/Include/core_cmSimd.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;
 
 [PreviousUsedKeilFiles]
-SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null;
+SourceFiles=..\Src\main.c;..\Src\stm32f4xx_it.c;..\Src\stm32f4xx_hal_msp.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_eth.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_iwdg.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_sdmmc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;../\Src/system_stm32f4xx.c;../Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;null;
 HeaderPath=..\Drivers\STM32F4xx_HAL_Driver\Inc;..\Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32F4xx\Include;..\Drivers\CMSIS\Include;..\Inc;