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提交 f615c1e9 编写于 作者: G Grissiom
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Revert "Merge pull request #241 from bright-pan/master" 

This reverts commit 5aeedc4f, reversing
changes made to 3d80e414.

This merge breaks every uart driver in all BSPs. @bright-pan , is there
any way to get this done without breaking existing code?
上级 54b693b3
隐藏空白更改
内联 并排
Showing with 178 addition and 493 deletion
bsp/stm32f10x/drivers/board.h
浏览文件 @ f615c1e9
......@@ -41,8 +41,6 @@
#define RT_USING_UART1
#define RT_USING_UART2
#define RT_USING_UART3
//#define RT_USING_UART4
//#define RT_USING_UART5
#endif /* __BOARD_H__ */
......
bsp/stm32f10x/drivers/usart.c
浏览文件 @ f615c1e9
......@@ -21,90 +21,25 @@
#include <rtdevice.h>
/* USART1 */
#define UART1_TX_PIN GPIO_Pin_9
#define UART1_TX_GPIO GPIOA
#define UART1_RX_PIN GPIO_Pin_10
#define UART1_RX_GPIO GPIOA
#define UART1_CTS_PIN ((uint16_t)0x0000)// cts is disable
#define UART1_CTS_GPIO ((GPIO_TypeDef *)0x00000000)
#define UART1_RTS_PIN ((uint16_t)0x0000)// rts is disable
#define UART1_RTS_GPIO ((GPIO_TypeDef *)0x00000000)
#define UART1_REMAP (((uint32_t)0x00000000))// remap is disable
#define UART1_GPIO_TX GPIO_Pin_9
#define UART1_GPIO_RX GPIO_Pin_10
#define UART1_GPIO GPIOA
/* USART2 */
#define UART2_TX_PIN GPIO_Pin_2
#define UART2_TX_GPIO GPIOA
#define UART2_RX_PIN GPIO_Pin_3
#define UART2_RX_GPIO GPIOA
#define UART2_CTS_PIN ((uint16_t)0x0000)// cts is disable
#define UART2_CTS_GPIO ((GPIO_TypeDef *)0x00000000)
#define UART2_RTS_PIN ((uint16_t)0x0000)// rts is disable
#define UART2_RTS_GPIO ((GPIO_TypeDef *)0x00000000)
#define UART2_REMAP (((uint32_t)0x00000000))// remap is disable
/* USART3_REMAP[1:0] = 11 */
#define UART3_TX_PIN GPIO_Pin_8
#define UART3_TX_GPIO GPIOD
#define UART3_RX_PIN GPIO_Pin_9
#define UART3_RX_GPIO GPIOD
#define UART3_CTS_PIN ((uint16_t)0x0000)// cts is disable
#define UART3_CTS_GPIO ((GPIO_TypeDef *)0x00000000)
#define UART3_RTS_PIN ((uint16_t)0x0000)// rts is disable
#define UART3_RTS_GPIO ((GPIO_TypeDef *)0x00000000)
#define UART3_REMAP GPIO_FullRemap_USART3
/* USART4 */
#define UART4_TX_PIN GPIO_Pin_10
#define UART4_TX_GPIO GPIOC
#define UART4_RX_PIN GPIO_Pin_11
#define UART4_RX_GPIO GPIOC
#define UART4_CTS_PIN ((uint16_t)0x0000)// cts is disable
#define UART4_CTS_GPIO ((GPIO_TypeDef *)0x00000000)
#define UART4_RTS_PIN ((uint16_t)0x0000)// rts is disable
#define UART4_RTS_GPIO ((GPIO_TypeDef *)0x00000000)
#define UART4_REMAP (((uint32_t)0x00000000))// remap is disable
#define UART2_GPIO_TX GPIO_Pin_2
#define UART2_GPIO_RX GPIO_Pin_3
#define UART2_GPIO GPIOA
/* USART5 */
#define UART5_TX_PIN GPIO_Pin_12
#define UART5_TX_GPIO GPIOC
#define UART5_RX_PIN GPIO_Pin_2
#define UART5_RX_GPIO GPIOD
#define UART5_CTS_PIN ((uint16_t)0x0000)// cts is disable
#define UART5_CTS_GPIO ((GPIO_TypeDef *)0x00000000)
#define UART5_RTS_PIN ((uint16_t)0x0000)// rts is disable
#define UART5_RTS_GPIO ((GPIO_TypeDef *)0x00000000)
#define UART4_REMAP (((uint32_t)0x00000000))// remap is disable
/* USART3_REMAP[1:0] = 00 */
#define UART3_GPIO_TX GPIO_Pin_10
#define UART3_GPIO_RX GPIO_Pin_11
#define UART3_GPIO GPIOB
/* STM32 uart driver */
struct stm32_uart
{
USART_TypeDef* uart_device;
IRQn_Type irq;
uint16_t uart_tx_pin;
GPIO_TypeDef *uart_tx_gpio;
uint16_t uart_rx_pin;
GPIO_TypeDef *uart_rx_gpio;
uint16_t uart_cts_pin;
GPIO_TypeDef *uart_cts_gpio;
uint16_t uart_rts_pin;
GPIO_TypeDef *uart_rts_gpio;
uint32_t uart_remap;
};
static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
......@@ -116,7 +51,7 @@ static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_c
RT_ASSERT(cfg != RT_NULL);
uart = (struct stm32_uart *)serial->parent.user_data;
USART_StructInit(&USART_InitStructure);
USART_InitStructure.USART_BaudRate = cfg->baud_rate;
if (cfg->data_bits == DATA_BITS_8)
......@@ -127,18 +62,8 @@ static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_c
else if (cfg->stop_bits == STOP_BITS_2)
USART_InitStructure.USART_StopBits = USART_StopBits_2;
if (cfg->parity == PARITY_NONE)
USART_InitStructure.USART_Parity = USART_Parity_No;
else if (cfg->parity == PARITY_EVEN)
USART_InitStructure.USART_Parity = USART_Parity_Even;
else if (cfg->parity == PARITY_ODD)
USART_InitStructure.USART_Parity = USART_Parity_Odd;
if (cfg->hw_control == HW_CONTROL_NONE)
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
else if (cfg->hw_control == HW_CONTROL_RTS_CTS)
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_RTS_CTS;
USART_InitStructure.USART_Parity = USART_Parity_No;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_Init(uart->uart_device, &USART_InitStructure);
......@@ -210,327 +135,180 @@ static const struct rt_uart_ops stm32_uart_ops =
stm32_getc,
};
__STATIC_INLINE void serial_device_isr(struct rt_serial_device *serial)
{
volatile int ch = 0;
struct stm32_uart *uart = serial->parent.user_data;
/* process uart error */
if(uart->uart_device->SR & (USART_FLAG_ORE | USART_FLAG_NE | USART_FLAG_FE | USART_FLAG_PE))
{
ch = uart->uart_device->DR; // invalid read
while (uart->uart_device->SR & USART_FLAG_RXNE)
{
ch = uart->uart_device->DR; // invalid read
}
}
/* process usart receive */
if (uart->uart_device->SR & USART_FLAG_RXNE)
{
rt_hw_serial_isr(serial);//auto clear interrupt flag
}
/* process usart send */
if (uart->uart_device->SR & USART_IT_TC)
{
/* clear interrupt */
uart->uart_device->SR = ~((uint16_t)0x01 << (uint16_t)(USART_IT_TC >> 0x08));
}
}
#if defined(RT_USING_UART1)
/* UART1 device driver structure */
struct serial_ringbuffer uart1_int_rx;
#define UART1_POOL_SIZE 64
rt_uint8_t uart1_pool[UART1_POOL_SIZE];
struct stm32_uart uart1 =
{
USART1,
USART1_IRQn,
UART1_TX_PIN,
UART1_TX_GPIO,
UART1_RX_PIN,
UART1_RX_GPIO,
UART1_CTS_PIN,
UART1_CTS_GPIO,
UART1_RTS_PIN,
UART1_RTS_GPIO,
UART1_REMAP,
};
struct rt_serial_device serial1;
void USART1_IRQHandler(void)
{
struct stm32_uart* uart;
uart = &uart1;
/* enter interrupt */
rt_interrupt_enter();
if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
{
rt_hw_serial_isr(&serial1);
/* clear interrupt */
USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
}
if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
{
/* clear interrupt */
USART_ClearITPendingBit(uart->uart_device, USART_IT_TC);
}
serial_device_isr(&serial1);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* RT_USING_UART1 */
#if defined(RT_USING_UART2)
/* UART2 device driver structure */
/* UART1 device driver structure */
struct serial_ringbuffer uart2_int_rx;
#define UART2_POOL_SIZE 64
rt_uint8_t uart2_pool[UART2_POOL_SIZE];
struct stm32_uart uart2 =
{
USART2,
USART2_IRQn,
UART2_TX_PIN,
UART2_TX_GPIO,
UART2_RX_PIN,
UART2_RX_GPIO,
UART2_CTS_PIN,
UART2_CTS_GPIO,
UART2_RTS_PIN,
UART2_RTS_GPIO,
UART2_REMAP,
};
struct rt_serial_device serial2;
void USART2_IRQHandler(void)
{
struct stm32_uart* uart;
uart = &uart2;
/* enter interrupt */
rt_interrupt_enter();
if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
{
rt_hw_serial_isr(&serial2);
/* clear interrupt */
USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
}
if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
{
/* clear interrupt */
USART_ClearITPendingBit(uart->uart_device, USART_IT_TC);
}
serial_device_isr(&serial2);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* RT_USING_UART2 */
#if defined(RT_USING_UART3)
/* UART3 device driver structure */
/* UART1 device driver structure */
struct serial_ringbuffer uart3_int_rx;
#define UART3_POOL_SIZE 64
rt_uint8_t uart3_pool[UART3_POOL_SIZE];
struct stm32_uart uart3 =
{
USART3,
USART3_IRQn,
UART3_TX_PIN,
UART3_TX_GPIO,
UART3_RX_PIN,
UART3_RX_GPIO,
UART3_CTS_PIN,
UART3_CTS_GPIO,
UART3_RTS_PIN,
UART3_RTS_GPIO,
UART3_REMAP,
};
struct rt_serial_device serial3;
void USART3_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
serial_device_isr(&serial3);
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* RT_USING_UART3 */
#if defined(RT_USING_UART4)
/* UART4 device driver structure */
struct serial_ringbuffer uart4_int_rx;
#define UART4_POOL_SIZE 64
rt_uint8_t uart4_pool[UART4_POOL_SIZE];
struct stm32_uart uart4 =
{
UART4,
UART4_IRQn,
UART4_TX_PIN,
UART4_TX_GPIO,
UART4_RX_PIN,
UART4_RX_GPIO,
UART4_CTS_PIN,
UART4_CTS_GPIO,
UART4_RTS_PIN,
UART4_RTS_GPIO,
struct stm32_uart* uart;
UART4_REMAP,
};
struct rt_serial_device serial4;
uart = &uart3;
void UART4_IRQHandler(void)
{
/* enter interrupt */
rt_interrupt_enter();
serial_device_isr(&serial4);
if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
{
rt_hw_serial_isr(&serial3);
/* clear interrupt */
USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
}
if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
{
/* clear interrupt */
USART_ClearITPendingBit(uart->uart_device, USART_IT_TC);
}
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* RT_USING_UART4 */
#if defined(RT_USING_UART5)
/* UART5 device driver structure */
struct serial_ringbuffer uart5_int_rx;
#define UART5_POOL_SIZE 64
rt_uint8_t uart5_pool[UART5_POOL_SIZE];
struct stm32_uart uart5 =
{
UART5,
UART5_IRQn,
UART5_TX_PIN,
UART5_TX_GPIO,
UART5_RX_PIN,
UART5_RX_GPIO,
UART5_CTS_PIN,
UART5_CTS_GPIO,
UART5_RTS_PIN,
UART5_RTS_GPIO,
UART5_REMAP,
};
struct rt_serial_device serial5;
#endif /* RT_USING_UART3 */
void UART5_IRQHandler(void)
static void RCC_Configuration(void)
{
/* enter interrupt */
rt_interrupt_enter();
#ifdef RT_USING_UART1
/* Enable UART GPIO clocks */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
/* Enable UART clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
#endif /* RT_USING_UART1 */
serial_device_isr(&serial5);
#ifdef RT_USING_UART2
/* Enable UART GPIO clocks */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
/* Enable UART clock */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
#endif /* RT_USING_UART2 */
/* leave interrupt */
rt_interrupt_leave();
}
#endif /* RT_USING_UART5 */
#define GPIO_RCC_ENABLE(x) \
do{ \
if (IS_GPIO_ALL_PERIPH(x)) \
{ \
if ((x) == GPIOA) \
{ \
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); \
} \
if ((x) == GPIOB) \
{ \
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); \
} \
if ((x) == GPIOC) \
{ \
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE); \
} \
if ((x) == GPIOD) \
{ \
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE); \
} \
if ((x) == GPIOE) \
{ \
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE, ENABLE); \
} \
if ((x) == GPIOF) \
{ \
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOF, ENABLE); \
} \
if ((x) == GPIOG) \
{ \
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOG, ENABLE); \
} \
} \
}while(0)
#define UART_RCC_ENABLE(x) \
do{ \
if (IS_USART_ALL_PERIPH(x)) \
{ \
if ((x) == USART1) \
{ \
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); \
} \
if ((x) == USART2) \
{ \
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); \
} \
if ((x) == USART3) \
{ \
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); \
} \
if ((x) == UART4) \
{ \
RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE); \
} \
if ((x) == UART5) \
{ \
RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE); \
} \
} \
}while(0)
static void RCC_Configuration(struct stm32_uart* uart)
{
#ifdef RT_USING_UART3
/* Enable UART GPIO clocks */
GPIO_RCC_ENABLE(uart->uart_tx_gpio);
GPIO_RCC_ENABLE(uart->uart_rx_gpio);
GPIO_RCC_ENABLE(uart->uart_cts_gpio);
GPIO_RCC_ENABLE(uart->uart_rts_gpio);
/* Enable UART GPIO AF clocks */
if (IS_GPIO_REMAP(uart->uart_remap))
{
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
GPIO_PinRemapConfig(uart->uart_remap, ENABLE);
}
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
/* Enable UART clock */
UART_RCC_ENABLE(uart->uart_device);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
#endif /* RT_USING_UART3 */
}
static void GPIO_Configuration(struct stm32_uart* uart)
static void GPIO_Configuration(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
#ifdef RT_USING_UART1
/* Configure USART Rx/tx PIN */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitStructure.GPIO_Pin = uart->uart_rx_pin;
GPIO_Init(uart->uart_rx_gpio, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = UART1_GPIO_RX;
GPIO_Init(UART1_GPIO, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Pin = uart->uart_tx_pin;
GPIO_Init(uart->uart_tx_gpio, &GPIO_InitStructure);
/* Configure USART RTS/CTS PIN */
if (IS_GPIO_ALL_PERIPH(uart->uart_cts_gpio) &&
IS_GPIO_ALL_PERIPH(uart->uart_rts_gpio) &&
IS_GPIO_PIN(uart->uart_cts_pin) &&
IS_GPIO_PIN(uart->uart_rts_pin))
{
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitStructure.GPIO_Pin = uart->uart_cts_pin;
GPIO_Init(uart->uart_cts_gpio, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = UART1_GPIO_TX;
GPIO_Init(UART1_GPIO, &GPIO_InitStructure);
#endif /* RT_USING_UART1 */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Pin = uart->uart_rts_pin;
GPIO_Init(uart->uart_rts_gpio, &GPIO_InitStructure);
}
#ifdef RT_USING_UART2
/* Configure USART Rx/tx PIN */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitStructure.GPIO_Pin = UART2_GPIO_RX;
GPIO_Init(UART1_GPIO, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Pin = UART2_GPIO_TX;
GPIO_Init(UART2_GPIO, &GPIO_InitStructure);
#endif /* RT_USING_UART2 */
#ifdef RT_USING_UART3
/* Configure USART Rx/tx PIN */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitStructure.GPIO_Pin = UART3_GPIO_RX;
GPIO_Init(UART3_GPIO, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Pin = UART3_GPIO_TX;
GPIO_Init(UART3_GPIO, &GPIO_InitStructure);
#endif /* RT_USING_UART3 */
}
static void NVIC_Configuration(struct stm32_uart* uart)
{
NVIC_InitTypeDef NVIC_InitStructure;
/* Enable the USART Interrupt */
/* Enable the USART1 Interrupt */
NVIC_InitStructure.NVIC_IRQChannel = uart->irq;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
......@@ -541,161 +319,57 @@ static void NVIC_Configuration(struct stm32_uart* uart)
void rt_hw_usart_init(void)
{
struct stm32_uart* uart;
struct rt_serial_device *serial;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
RCC_Configuration();
GPIO_Configuration();
#ifdef RT_USING_UART1
uart = &uart1;
serial = &serial1;
uart1_int_rx.pool = uart1_pool;
uart1_int_rx.size = UART1_POOL_SIZE;
config.baud_rate = BAUD_RATE_115200;
serial->ops = &stm32_uart_ops;
serial->int_rx = &uart1_int_rx;
serial->config = config;
RCC_Configuration(uart);
GPIO_Configuration(uart);
NVIC_Configuration(uart);
serial1.ops = &stm32_uart_ops;
serial1.int_rx = &uart1_int_rx;
serial1.config = config;
NVIC_Configuration(&uart1);
/* register UART1 device */
rt_hw_serial_register(serial, "uart1",
rt_hw_serial_register(&serial1, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
uart);
#endif /* RT_USING_UART1 */
#ifdef RT_USING_UART2
uart = &uart2;
serial = &serial2;
uart2_int_rx.pool = uart2_pool;
uart2_int_rx.size = UART2_POOL_SIZE;
config.baud_rate = BAUD_RATE_115200;
serial2.ops = &stm32_uart_ops;
serial2.int_rx = &uart2_int_rx;
serial2.config = config;
serial->ops = &stm32_uart_ops;
serial->int_rx = &uart2_int_rx;
serial->config = config;
RCC_Configuration(uart);
GPIO_Configuration(uart);
NVIC_Configuration(uart);
NVIC_Configuration(&uart2);
/* register UART2 device */
rt_hw_serial_register(serial, "uart2",
/* register UART1 device */
rt_hw_serial_register(&serial2, "uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
#endif /* RT_USING_UART2 */
#ifdef RT_USING_UART3
uart = &uart3;
serial = &serial3;
uart3_int_rx.pool = uart3_pool;
uart3_int_rx.size = UART3_POOL_SIZE;
config.baud_rate = BAUD_RATE_115200;
serial->ops = &stm32_uart_ops;
serial->int_rx = &uart3_int_rx;
serial->config = config;
RCC_Configuration(uart);
GPIO_Configuration(uart);
NVIC_Configuration(uart);
/* register UART3 device */
rt_hw_serial_register(serial, "uart3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
#endif /* RT_USING_UART3 */
serial3.ops = &stm32_uart_ops;
serial3.int_rx = &uart3_int_rx;
serial3.config = config;
#ifdef RT_USING_UART4
uart = &uart4;
serial = &serial4;
uart4_int_rx.pool = uart4_pool;
uart4_int_rx.size = UART4_POOL_SIZE;
NVIC_Configuration(&uart3);
config.baud_rate = BAUD_RATE_115200;
serial->ops = &stm32_uart_ops;
serial->int_rx = &uart4_int_rx;
serial->config = config;
RCC_Configuration(uart);
GPIO_Configuration(uart);
NVIC_Configuration(uart);
/* register UART4 device */
rt_hw_serial_register(serial, "uart4",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
#endif /* RT_USING_UART4 */
#ifdef RT_USING_UART5
uart = &uart5;
serial = &serial5;
uart5_int_rx.pool = uart5_pool;
uart5_int_rx.size = UART5_POOL_SIZE;
config.baud_rate = BAUD_RATE_115200;
serial->ops = &stm32_uart_ops;
serial->int_rx = &uart5_int_rx;
serial->config = config;
RCC_Configuration(uart);
GPIO_Configuration(uart);
NVIC_Configuration(uart);
/* register UART5 device */
rt_hw_serial_register(serial, "uart5",
/* register UART1 device */
rt_hw_serial_register(&serial3, "uart3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
uart);
#endif /* RT_USING_UART5 */
}
/* uart device test */
#ifdef RT_USING_FINSH
#include <finsh.h>
#if (defined(RT_USING_UART1) || defined(RT_USING_UART2) || defined(RT_USING_UART3) || defined(RT_USING_UART4) || defined(RT_USING_UART5))
void uart_rw(const char *name, rt_int8_t cmd, const char *str)
{
rt_device_t uart;
uart = rt_device_find(name);
if (uart != RT_NULL)
{
if (uart->open_flag == RT_DEVICE_OFLAG_CLOSE)
{
rt_device_open(uart, RT_DEVICE_OFLAG_RDWR);
}
if (cmd == 0)
{
rt_int8_t temp[20];
memset(temp, '\0', 20);
rt_device_read(uart,0,(void *)temp,20);
rt_kprintf("%s", temp);
}
else
{
rt_kprintf("%s, %d", str, strlen(str));
rt_device_write(uart,0,str,strlen(str));
}
//rt_device_close(uart);
}
else
{
rt_kprintf("device %s is not exist!\n", name);
}
#endif /* RT_USING_UART3 */
}
FINSH_FUNCTION_EXPORT(uart_rw, set uart[name 0 xxx] for read.)
#endif
#endif
components/drivers/include/drivers/serial.h
浏览文件 @ f615c1e9
......@@ -29,7 +29,6 @@
#define __SERIAL_H__
#include <rtthread.h>
#include <rtdevice.h>
#define BAUD_RATE_4800 4800
#define BAUD_RATE_9600 9600
......@@ -56,11 +55,6 @@
#define NRZ_NORMAL 0 /* Non Return to Zero : normal mode */
#define NRZ_INVERTED 1 /* Non Return to Zero : inverted mode */
#define HW_CONTROL_NONE 0
#define HW_CONTROL_RTS 1
#define HW_CONTROL_CTS 2
#define HW_CONTROL_RTS_CTS 3
#ifndef RT_SERIAL_RB_BUFSZ
#define RT_SERIAL_RB_BUFSZ 64
#endif
......@@ -81,23 +75,21 @@
#define RT_SERIAL_TX_DATAQUEUE_LWM 30
/* Default config for serial_configure structure */
#define RT_SERIAL_CONFIG_DEFAULT \
{ \
BAUD_RATE_115200, /* 115200 bits/s */ \
DATA_BITS_8, /* 8 databits */ \
STOP_BITS_1, /* 1 stopbit */ \
PARITY_NONE, /* No parity */ \
BIT_ORDER_LSB, /* LSB first sent */ \
NRZ_NORMAL, /* Normal mode */ \
HW_CONTROL_NONE, /* Hardware control */\
0 \
#define RT_SERIAL_CONFIG_DEFAULT \
{ \
BAUD_RATE_115200, /* 115200 bits/s */ \
DATA_BITS_8, /* 8 databits */ \
STOP_BITS_1, /* 1 stopbit */ \
PARITY_NONE, /* No parity */ \
BIT_ORDER_LSB, /* LSB first sent */ \
NRZ_NORMAL, /* Normal mode */ \
0 \
}
struct serial_ringbuffer
{
struct rt_ringbuffer rb;
rt_uint8_t *pool;
rt_uint16_t size;
rt_uint8_t buffer[RT_SERIAL_RB_BUFSZ];
rt_uint16_t put_index, get_index;
};
struct serial_configure
......@@ -108,8 +100,7 @@ struct serial_configure
rt_uint32_t parity :2;
rt_uint32_t bit_order :1;
rt_uint32_t invert :1;
rt_uint32_t hw_control :2;
rt_uint32_t reserved :18;
rt_uint32_t reserved :20;
};
struct rt_serial_device
......
components/drivers/serial/serial.c
浏览文件 @ f615c1e9
......@@ -25,9 +25,6 @@
* 2012-11-23 bernard fix compiler warning.
* 2013-02-20 bernard use RT_SERIAL_RB_BUFSZ to define
* the size of ring buffer.
* 2014-02-26 bright use DeviceDriver ringbuffer.
* add hardware flow support.
* use new struct serial_ringbuffer.
*/
#include <rthw.h>
......@@ -36,7 +33,9 @@
rt_inline void serial_ringbuffer_init(struct serial_ringbuffer *rbuffer)
{
rt_ringbuffer_init(&rbuffer->rb, rbuffer->pool, rbuffer->size);
rt_memset(rbuffer->buffer, 0, sizeof(rbuffer->buffer));
rbuffer->put_index = 0;
rbuffer->get_index = 0;
}
rt_inline void serial_ringbuffer_putc(struct serial_ringbuffer *rbuffer,
......@@ -46,8 +45,17 @@ rt_inline void serial_ringbuffer_putc(struct serial_ringbuffer *rbuffer,
/* disable interrupt */
level = rt_hw_interrupt_disable();
rt_ringbuffer_putchar(&rbuffer->rb, ch);
// enable interrupt
rbuffer->buffer[rbuffer->put_index] = ch;
rbuffer->put_index = (rbuffer->put_index + 1) & (RT_SERIAL_RB_BUFSZ - 1);
/* if the next position is read index, discard this 'read char' */
if (rbuffer->put_index == rbuffer->get_index)
{
rbuffer->get_index = (rbuffer->get_index + 1) & (RT_SERIAL_RB_BUFSZ - 1);
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
}
......@@ -55,11 +63,25 @@ rt_inline int serial_ringbuffer_putchar(struct serial_ringbuffer *rbuffer,
char ch)
{
rt_base_t level;
//rt_uint16_t next_index;
rt_uint16_t next_index;
/* disable interrupt */
level = rt_hw_interrupt_disable();
rt_ringbuffer_putchar(&rbuffer->rb, ch);
next_index = (rbuffer->put_index + 1) & (RT_SERIAL_RB_BUFSZ - 1);
if (next_index != rbuffer->get_index)
{
rbuffer->buffer[rbuffer->put_index] = ch;
rbuffer->put_index = next_index;
}
else
{
/* enable interrupt */
rt_hw_interrupt_enable(level);
return -1;
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
......@@ -68,14 +90,17 @@ rt_inline int serial_ringbuffer_putchar(struct serial_ringbuffer *rbuffer,
rt_inline int serial_ringbuffer_getc(struct serial_ringbuffer *rbuffer)
{
int ch = 0;
int ch;
rt_base_t level;
ch = -1;
/* disable interrupt */
level = rt_hw_interrupt_disable();
/* get char */
if (!rt_ringbuffer_getchar(&rbuffer->rb, (rt_uint8_t *)&ch))
ch = -1;
if (rbuffer->get_index != rbuffer->put_index)
{
ch = rbuffer->buffer[rbuffer->get_index];
rbuffer->get_index = (rbuffer->get_index + 1) & (RT_SERIAL_RB_BUFSZ - 1);
}
/* enable interrupt */
rt_hw_interrupt_enable(level);
......@@ -88,10 +113,7 @@ rt_inline rt_uint32_t serial_ringbuffer_size(struct serial_ringbuffer *rbuffer)
rt_base_t level;
level = rt_hw_interrupt_disable();
size = rt_ringbuffer_space_len(&rbuffer->rb);
/*
size = (rbuffer->put_index - rbuffer->get_index) & (RT_SERIAL_RB_BUFSZ - 1);
*/
rt_hw_interrupt_enable(level);
return size;
......
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