diff --git a/bsp/nuc140/CMSIS/CM0/NUC1xx.h b/bsp/nuc140/CMSIS/CM0/NUC1xx.h new file mode 100644 index 0000000000000000000000000000000000000000..1cbb6747b14b4a7e5f43b10ca548e3757df410a1 --- /dev/null +++ b/bsp/nuc140/CMSIS/CM0/NUC1xx.h @@ -0,0 +1,2029 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* */ +/* Copyright (c) Nuvoton Technology Corp. All rights reserved. */ +/* */ +/*---------------------------------------------------------------------------------------------------------*/ + +#ifndef __NUC1xx_H__ +#define __NUC1xx_H__ + + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/****** ARMIKMCU Swift specific Interrupt Numbers ************************************************/ + BOD_IRQn = 0, + WDT_IRQn = 1, + EINT0_IRQn = 2, + EINT1_IRQn = 3, + GPAB_IRQn = 4, + GPCDE_IRQn = 5, + PWMA_IRQn = 6, + PWMB_IRQn = 7, + TMR0_IRQn = 8, + TMR1_IRQn = 9, + TMR2_IRQn = 10, + TMR3_IRQn = 11, + UART0_IRQn = 12, + UART1_IRQn = 13, + SPI0_IRQn = 14, + SPI1_IRQn = 15, + SPI2_IRQn = 16, + SPI3_IRQn = 17, + I2C0_IRQn = 18, + I2C1_IRQn = 19, + CAN0_IRQn = 20, + CAN1_IRQn = 21, + SD_IRQn = 22, + USBD_IRQn = 23, + PS2_IRQn = 24, + ACMP_IRQn = 25, + PDMA_IRQn = 26, + I2S_IRQn = 27, + PWRWU_IRQn = 28, + ADC_IRQn = 29, + DAC_IRQn = 30, + RTC_IRQn = 31 + + /*!< maximum of 32 Interrupts are possible */ +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M0 Processor and Core Peripherals */ +#define __MPU_PRESENT 0 /*!< armikcmu does not provide a MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< armikcmu Supports 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + + +#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ +#include "system_NUC1xx.h" /* NUC1xx System */ +// #include "System\SysInfra.h" + + +/** + * Initialize the system clock + * + * @param none + * @return none + * + * @brief Setup the microcontroller system + * Initialize the PLL and update the SystemFrequency variable + */ +extern void SystemInit (void); + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/*--------------------- General Purpose Input and Ouptut ---------------------*/ +typedef struct +{ + __IO uint32_t PMD0:2; + __IO uint32_t PMD1:2; + __IO uint32_t PMD2:2; + __IO uint32_t PMD3:2; + __IO uint32_t PMD4:2; + __IO uint32_t PMD5:2; + __IO uint32_t PMD6:2; + __IO uint32_t PMD7:2; + __IO uint32_t PMD8:2; + __IO uint32_t PMD9:2; + __IO uint32_t PMD10:2; + __IO uint32_t PMD11:2; + __IO uint32_t PMD12:2; + __IO uint32_t PMD13:2; + __IO uint32_t PMD14:2; + __IO uint32_t PMD15:2; +} GPIO_PMD_T; + +typedef __IO uint32_t GPIO_SCH_T; + +typedef __IO uint32_t GPIO_DOUT_T; + +typedef __IO uint32_t GPIO_DMASK_T; + +typedef __IO uint32_t GPIO_PIN_T; + +typedef __IO uint32_t GPIO_DBEN_T; + +typedef __IO uint32_t GPIO_IMD_T; + +typedef __IO uint32_t GPIO_IEN_T; + +typedef __IO uint32_t GPIO_ISRC_T; + +typedef struct +{ + __IO uint32_t DBCLKSEL:4; + __IO uint32_t DBCLKSRC:1; + __IO uint32_t ICLK_ON:1; + __I uint32_t RESERVE:26; +} GPIO_DBNCECON_T; + +typedef struct +{ + GPIO_PMD_T PMD; + GPIO_SCH_T SCH; + GPIO_DOUT_T DOUT; + GPIO_DMASK_T DMASK; + GPIO_PIN_T PIN; + GPIO_DBEN_T DBEN; + GPIO_IMD_T IMD; + GPIO_IEN_T IEN; + GPIO_ISRC_T ISRC; + +} GPIO_T; + + +/*------------------------- UART Interface Controller ------------------------*/ + +typedef __IO uint32_t UART_DATA_T; + + +typedef struct +{ + __IO uint32_t RDA_IEN:1; + __IO uint32_t THRE_IEN:1; + __IO uint32_t RLS_IEN:1; + __IO uint32_t MS_IEN:1; + __IO uint32_t RTO_IEN:1; + __IO uint32_t BUF_ERR_IEN:1; + __IO uint32_t WAKE_IEN:1; + __I uint32_t RESERVE0:4; + __IO uint32_t TOC_EN:1; /* Time-out counter enable */ + __IO uint32_t AUTO_RTS_EN:1; + __IO uint32_t AUTO_CTS_EN:1; + __IO uint32_t DMA_TX_EN:1; + __IO uint32_t DMA_RX_EN:1; + __I uint32_t RESERVE1:15; + __IO uint32_t nDEBUGACK_EN:1; +} UART_IER_T; + +typedef struct +{ + __I uint32_t RESERVE0:1; + __IO uint32_t RFR:1; + __IO uint32_t TFR:1; + __I uint32_t RESERVE1:1; + __IO uint32_t RFITL:4; /* Rx FIFO Interrupt Trigger Level */ + __I uint32_t RESERVE2:8; + __IO uint32_t RTS_TRIG_LEVEL:4; + __I uint32_t RESERVE3:12; +} UART_FCR_T; + +typedef struct +{ + __IO uint32_t WLS:2; /* Word length select */ + __IO uint32_t NSB:1; /* Number of STOP bit */ + __IO uint32_t PBE:1; /* Parity bit enable */ + __IO uint32_t EPE:1; /* Even parity enable */ + __IO uint32_t SPE:1; /* Stick parity enable*/ + __IO uint32_t BCB:1; /* Break control bit */ + __I uint32_t RESERVE:25; +} UART_LCR_T; + +typedef struct +{ + __I uint32_t RESERVE0:1; + __IO uint32_t RTS_INV:1; + __I uint32_t RESERVE1:2; + __IO uint32_t LBME:1; + __I uint32_t RESERVE2:4; + __IO uint32_t RTS_ACT_LEVEL:1; + __I uint32_t RESERVE3:3; + __I uint32_t RTS:1; /* RTS status */ + __I uint32_t RESERVE4:18; +} UART_MCR_T; + +typedef struct +{ + __IO uint32_t DCTS:1; + __I uint32_t RESERVE0:3; + __I uint32_t CTS:1; /* CTS status */ + __I uint32_t RESERVE1:3; + __IO uint32_t CTS_ACT_LEVEL:1; + __I uint32_t RESERVE2:23; +} UART_MSR_T; + +typedef struct +{ + __IO uint32_t RX_OVERFLOW:1; + __I uint32_t RESERVE0:3; + __IO uint32_t PEI:1; + __IO uint32_t FEI:1; + __IO uint32_t BII:1; + __I uint32_t RESERVE1:1; + __I uint32_t RX_POINTER:6; + __I uint32_t RX_EMPTY:1; + __I uint32_t RX_FULL:1; + __I uint32_t TX_POINTER:6; + __I uint32_t TX_EMPTY:1; + __I uint32_t TX_FULL:1; + __IO uint32_t TX_OVERFLOW:1; + __I uint32_t RESERVE2:3; + __I uint32_t TE:1; /* Transmitter empty flag */ + __I uint32_t RESERVE3:3; +} UART_FSR_T; + +typedef struct +{ + __IO uint32_t RDA_IF:1; + __IO uint32_t THRE_IF:1; + __IO uint32_t RLS_IF:1; + __IO uint32_t MODEM_IF:1; + __IO uint32_t TOUT_IF:1; + __IO uint32_t BUF_ERR_IF:1; + __IO uint32_t WAKE_IF:1; + __IO uint32_t SW_TX:1; + __IO uint32_t RDA_INT:1; + __IO uint32_t THRE_INT:1; + __IO uint32_t RLS_INT:1; + __IO uint32_t MODEM_INT:1; + __IO uint32_t TOUT_INT:1; + __IO uint32_t BUF_ERR_INT:1; + __IO uint32_t WAKE_INT:1; + __IO uint32_t SW_RX:1; + __I uint32_t RESERVE0:2; + __IO uint32_t HW_RLS_IF:1; + __IO uint32_t HW_MODEM_IF:1; + __IO uint32_t HW_TOUT_IF:1; + __IO uint32_t HW_BUF_ERR_IF:1; + __IO uint32_t HW_WAKE_IF:1; + __IO uint32_t EDMA_TX:1; + __I uint32_t RESERVE1:2; + __IO uint32_t HW_RLS_INT:1; + __IO uint32_t HW_MODEM_INT:1; + __IO uint32_t HW_TOUT_INT:1; + __IO uint32_t HW_BUF_ERR_INT:1; + __IO uint32_t HW_WAKE_INT:1; + __IO uint32_t EDMA_RX:1; +} UART_ISR_T; + +typedef __IO uint32_t UART_TOR_T; + +typedef struct +{ + __IO uint32_t DIV:16; + __I uint32_t RESERVE0:8; + __IO uint32_t DIVX:4; + __IO uint32_t DIVX1:1; + __IO uint32_t DIVX_EN:1; + __I uint32_t RESERVE1:2; +} UART_BAUD_T; + +typedef struct +{ + __IO uint32_t IrDA_EN:1; + __I uint32_t RESERVE0:2; + __IO uint32_t RX_EN:1; + __IO uint32_t TX_EN:1; + __IO uint32_t TX_INV_EN:1; + __IO uint32_t RX_INV_EN:1; + __I uint32_t RESERVE1:25; +} UART_IRCR_T; + +typedef struct +{ + __IO uint32_t LINBCNT:4; + __I uint32_t RESERVE0:2; + __IO uint32_t LINRX_EN:1; + __IO uint32_t LINTX_EN:1; + __I uint32_t RESERVE1:24; +} UART_LINCON_T; + + + +typedef struct +{ + __IO uint32_t LIN_EN:2; + __IO uint32_t IrDA_EN:2; + __I uint32_t RESERVE0:32; + +} UART_FUNSEL_T; + + +typedef struct +{ + UART_DATA_T DATA; + UART_IER_T IER; + UART_FCR_T FCR; + UART_LCR_T LCR; + UART_MCR_T MCR; + UART_MSR_T MSR; + UART_FSR_T FSR; + UART_ISR_T ISR; + UART_TOR_T TOR; + UART_BAUD_T BAUD; + UART_IRCR_T IRCR; + UART_LINCON_T LINCON; + UART_FUNSEL_T FUNSEL; +} UART_T; + +/*----------------------------- Timer Controller -----------------------------*/ +typedef struct +{ + __IO uint32_t PRESCALE:8; + __I uint32_t RESERVE0:8; + __IO uint32_t TDR_EN:1; + __I uint32_t RESERVE1:8; + __IO uint32_t CACT:1; + __IO uint32_t CRST:1; + __IO uint32_t MODE:2; + __IO uint32_t IE:1; + __IO uint32_t CEN:1; + __IO uint32_t nDBGACK_EN:1; +} TIMER_TCSR_T; + +typedef __IO uint32_t TIMER_TICR_T; + +typedef __IO uint32_t TIMER_TDR_T; + +typedef struct +{ + __IO uint32_t TIF:1; + __I uint32_t RESERVE:31; +} TIMER_TISR_T; + +typedef struct +{ + TIMER_TCSR_T TCSR; + TIMER_TICR_T TICR; + TIMER_TISR_T TISR; + TIMER_TDR_T TDR; + } TIMER_T; + + +/*----------------------------- WDT Controller -----------------------------*/ +typedef struct +{ + __IO uint32_t WTR:1; + __IO uint32_t WTRE:1; + __IO uint32_t WTRF:1; + __IO uint32_t WTIF:1; + __I uint32_t RESERVE:2; + __IO uint32_t WTIE:1; + __IO uint32_t WTE:1; + __IO uint32_t WTIS:3; + __I uint32_t RESERVE1:21; +} WDT_WTCR_T; + +typedef struct +{ + WDT_WTCR_T WTCR; + + } WDT_T; + +/*------------------------- SPI Interface Controller -------------------------*/ +typedef struct +{ + __IO uint32_t GO_BUSY:1; + __IO uint32_t RX_NEG:1; + __IO uint32_t TX_NEG:1; + __IO uint32_t TX_BIT_LEN:5; + __IO uint32_t TX_NUM:2; + __IO uint32_t LSB:1; + __IO uint32_t CLKP:1; + __IO uint32_t SLEEP:4; + __IO uint32_t IF:1; + __IO uint32_t IE:1; + __IO uint32_t SLAVE:1; + __IO uint32_t BYTE_SLEEP:1; + __IO uint32_t BYTE_ENDIAN:1; + __IO uint32_t FOURB:1; + __IO uint32_t TWOB:1; + __IO uint32_t VARCLK_EN:1; + __I uint32_t RESERVE:8; +} SPI_CNTRL_T; + +typedef struct +{ + __IO uint32_t DIVIDER:16; + __IO uint32_t DIVIDER2:16; +} SPI_DIVIDER_T; + +typedef struct +{ + __IO uint32_t SSR:2; + __IO uint32_t SS_LVL:1; + __IO uint32_t ASS:1; + __IO uint32_t SS_LTRIG:1; + __IO uint32_t LTRIG_FLAG:1; + __I uint32_t RESERVE:26; +} SPI_SSR_T; + + +typedef __I uint32_t SPI_RX_T; +typedef __O uint32_t SPI_TX_T; + +typedef struct +{ + __IO uint32_t JS:1; + __I uint32_t RESERVE0:3; + __IO uint32_t JS_RW:1; + __IO uint32_t CS_ACT:1; + __IO uint32_t DATA_RDY:1; + __IO uint32_t CS_DEACT:1; + __IO uint32_t READYB:1; + __I uint32_t RESERVE1:23; +} SPI_JS_T; + +typedef __IO uint32_t SPI_VARCLK_T; + +typedef struct +{ + __IO uint32_t TX_DMA_GO:1; + __IO uint32_t RX_DMA_GO:1; + __I uint32_t RESERVE:30; +} SPI_DMA_T; + +typedef struct +{ + SPI_CNTRL_T CNTRL; + SPI_DIVIDER_T DIVIDER; + SPI_SSR_T SSR; + uint32_t RESERVE0; + SPI_RX_T RX[2]; + uint32_t RESERVE1; + uint32_t RESERVE2; + SPI_TX_T TX[2]; + uint32_t RESERVE3; + uint32_t RESERVE4; + SPI_JS_T JS; + SPI_VARCLK_T VARCLK; + SPI_DMA_T DMA; +} SPI_T; + +/*------------------------------ I2C Controller ------------------------------*/ +typedef struct +{ + __I uint32_t RESERVE0:2; + __IO uint32_t AA:1; + __IO uint32_t SI:1; + __IO uint32_t STO:1; + __IO uint32_t STA:1; + __IO uint32_t ENSI:1; + __IO uint32_t EI:1; + __I uint32_t RESERVE1:24; +} I2C_CON_T; + +typedef struct +{ + __IO uint32_t GC:1; + __IO uint32_t ADDR:7; + __I uint32_t RESERVE:24; +} I2C_ADDR_T; + +typedef __IO uint32_t I2C_DATA_T; + +typedef __I uint32_t I2C_STATUS_T; + +typedef __IO uint32_t I2C_CLK_T; + +typedef struct +{ + __IO uint32_t TIF:1; + __IO uint32_t DIV4:1; + __IO uint32_t ENTI:1; + __I uint32_t RESERVE:29; +} I2C_TOC_T; + +typedef struct +{ + __I uint32_t RESERVE0:1; + __IO uint32_t ADM:7; + __I uint32_t RESERVE1:24; +} I2C_ADRM_T; + +typedef struct +{ + I2C_CON_T CON; + I2C_ADDR_T ADDR0; + I2C_DATA_T DATA; + I2C_STATUS_T STATUS; + I2C_CLK_T CLK; + I2C_TOC_T TOC; + I2C_ADDR_T ADDR1; + I2C_ADDR_T ADDR2; + I2C_ADDR_T ADDR3; + I2C_ADRM_T ADRM0; + I2C_ADRM_T ADRM1; + I2C_ADRM_T ADRM2; + I2C_ADRM_T ADRM3; +} I2C_T; + + +/*----------------------------- RTC Controller -------------------------------*/ + +typedef __IO uint32_t RTC_INIR_T; + +typedef struct +{ + __IO uint32_t AER:16; + __I uint32_t ENF:1; + __I uint32_t RESERVE1:15; +} RTC_AER_T; + +typedef struct +{ + __IO uint32_t FRACTION:6; + __I uint32_t RESERVE0:2; + __IO uint32_t INTEGER:4; + __I uint32_t RESERVE1:20; +} RTC_FCR_T; + +typedef struct +{ + __IO uint32_t SEC1:4; + __IO uint32_t SEC10:3; + __I uint32_t RESERVE0:1; + __IO uint32_t MIN1:4; + __IO uint32_t MIN10:3; + __I uint32_t RESERVE1:1; + __IO uint32_t HR1:4; + __IO uint32_t HR10:2; + __I uint32_t RESERVE2:10; +} RTC_TLR_T; + +typedef struct +{ + __IO uint32_t DAY1:4; + __IO uint32_t DAY10:2; + __I uint32_t RESERVE0:2; + __IO uint32_t MON1:4; + __IO uint32_t MON10:1; + __I uint32_t RESERVE1:3; + __IO uint32_t YEAR1:4; + __IO uint32_t YEAR10:4; + __I uint32_t RESERVE2:8; +} RTC_CLR_T; + +typedef struct +{ + __IO uint32_t HR24:1; + __I uint32_t RESERVE:31; +} RTC_TSSR_T; + +typedef struct +{ + __IO uint32_t DWR:3; + __I uint32_t RESERVE:29; +} RTC_DWR_T; + +typedef RTC_TLR_T RTC_TAR_T; +typedef RTC_CLR_T RTC_CAR_T; + +typedef struct +{ + __IO uint32_t LIR:1; + __I uint32_t RESERVE:31; +} RTC_LIR_T; + +typedef struct +{ + __IO uint32_t AIER:1; + __IO uint32_t TIER:1; + __I uint32_t RESERVE:30; +} RTC_RIER_T; + + +//typedef __IO uint32_t RTC_RIIR_T; + +typedef struct +{ + __IO uint32_t AI:1; + __IO uint32_t TI:1; + __I uint32_t RESERVE:30; +} RTC_RIIR_T; + +typedef struct +{ + __IO uint32_t TTR:3; + __I uint32_t RESERVE:30; +} RTC_TTR_T; + +typedef struct +{ + __IO uint32_t PTOUT:16; + __I uint32_t RESERVE0:7; + __IO uint32_t PWROFF:1; + __I uint32_t RESERVE1:8; +} RTC_PWRCON_T; + +typedef struct +{ + RTC_INIR_T INIR; + RTC_AER_T AER; + RTC_FCR_T FCR; + RTC_TLR_T TLR; + RTC_CLR_T CLR; + RTC_TSSR_T TSSR; + RTC_DWR_T DWR; + RTC_TAR_T TAR; + RTC_CAR_T CAR; + RTC_LIR_T LIR; + RTC_RIER_T RIER; + RTC_RIIR_T RIIR; + RTC_TTR_T TTR; + RTC_PWRCON_T PWRCON; +} RTC_T; + + +/*----------------------------- ADC Controller -------------------------------*/ +typedef struct +{ + __IO uint32_t RSLT:16; + __IO uint32_t OVERRUN:1; + __IO uint32_t VALID:1; + __I uint32_t RESERVE1:14; +} ADC_ADDR_T; + +typedef struct +{ + __IO uint32_t ADEN:1; + __IO uint32_t ADIE:1; + __IO uint32_t ADMD:2; + __IO uint32_t TRGS:2; + __IO uint32_t TRGCOND:2; + __IO uint32_t TRGEN:1; + __IO uint32_t PTEN:1; + __IO uint32_t DIFF:1; + __IO uint32_t ADST:1; + __I uint32_t RESERVE0:4; + __IO uint32_t ADCLKDIV:7; + __I uint32_t RESERVE1:9; +} ADC_ADCR_T; + + + +typedef struct +{ + __IO uint32_t CHEN:8; + __IO uint32_t PRESEL:2; + __I uint32_t RESERVE:22; +} ADC_ADCHER_T; + + +typedef struct +{ + __IO uint32_t CMPEN:1; + __IO uint32_t CMPIE:1; + __IO uint32_t CMPCOND:1; + __IO uint32_t CMPCH:3; + __I uint32_t RESERVE0:2; + __IO uint32_t CMPMATCNT:4; + __I uint32_t RESERVE1:4; + __IO uint32_t CMPD:12; + __I uint32_t RESERVE2:4; +} ADC_ADCMPR_T; + +typedef struct +{ + __IO uint32_t ADF:1; + __IO uint32_t CMPF0:1; + __IO uint32_t CMPF1:1; + __IO uint32_t BUSY:1; + __IO uint32_t CHANNEL:3; + __I uint32_t RESERVE0:1; + __IO uint32_t VALID:8; + __IO uint32_t OVERRUN:8; + __I uint32_t RESERVE1:8; +} ADC_ADSR_T; + +typedef struct +{ + __IO uint32_t CALEN:1; + __IO uint32_t CALDONE:1; + __I uint32_t RESERVE:30; +} ADC_ADCALR_T; + +typedef struct +{ + ADC_ADDR_T ADDR[8]; + ADC_ADCR_T ADCR; + ADC_ADCHER_T ADCHER; + ADC_ADCMPR_T ADCMPR[2]; + ADC_ADSR_T ADSR; + ADC_ADCALR_T ADCALR; + +} ADC_T; + +/*---------------------- Analog Comparator Controller -------------------------*/ +typedef struct +{ + __IO uint32_t CMPEN:1; + __IO uint32_t CMPIE:1; + __IO uint32_t CMP_HYSEN:1; + __IO uint32_t CP:1; + __IO uint32_t CN:1; + __IO uint32_t COE:1; + __I uint32_t RESERVE:26; +} ACMP_CMPCR_T; + +typedef struct +{ + __IO uint32_t CMPF1:1; + __IO uint32_t CMPF2:1; + __IO uint32_t CO1:1; + __IO uint32_t CO2:1; + __I uint32_t RESERVE:28; +} ACMP_CMPSR_T; + +typedef struct +{ + ACMP_CMPCR_T CMPCR[2]; + ACMP_CMPSR_T CMPSR; +} ACMP_T; + +/*---------------------------- Clock Controller ------------------------------*/ +typedef struct +{ + __IO uint32_t XTL12M_EN:1; + __IO uint32_t XTL32K_EN:1; + __IO uint32_t OSC22M_EN:1; + __IO uint32_t OSC10K_EN:1; + __IO uint32_t WU_DLY:1; + __IO uint32_t WINT_EN:1; + __IO uint32_t PD_WU_STS:1; + __IO uint32_t PWR_DOWN:1; + __IO uint32_t PD_WAIT_CPU:1; + __I uint32_t RESERVE:23; +} SYSCLK_PWRCON_T; + +typedef struct +{ + __IO uint32_t CPU_EN:1; + __IO uint32_t PDMA_EN:1; + __IO uint32_t ISP_EN:1; + __I uint32_t RESERVE:29; +} SYSCLK_AHBCLK_T; + +typedef struct +{ + __IO uint32_t WDG_EN:1; + __IO uint32_t RTC_EN:1; + __IO uint32_t TMR0_EN:1; + __IO uint32_t TMR1_EN:1; + __IO uint32_t TMR2_EN:1; + __IO uint32_t TMR3_EN:1; + __I uint32_t RESERVE0:2; + __IO uint32_t I2C0_EN:1; + __IO uint32_t I2C1_EN:1; + __I uint32_t RESERVE1:2; + __IO uint32_t SPI0_EN:1; + __IO uint32_t SPI1_EN:1; + __IO uint32_t SPI2_EN:1; + __IO uint32_t SPI3_EN:1; + __IO uint32_t UART0_EN:1; + __IO uint32_t UART1_EN:1; + __I uint32_t RESERVE2:2; + __IO uint32_t PWM01_EN:1; + __IO uint32_t PWM23_EN:1; + __I uint32_t RESERVE3:2; + __IO uint32_t CAN0_EN:1; + __IO uint32_t CAN1_EN:1; + __I uint32_t RESERVE4:1; + __IO uint32_t USBD_EN:1; + __IO uint32_t ADC_EN:1; + __I uint32_t RESERVE5:1; + __IO uint32_t ACMP_EN:1; + __IO uint32_t PS2_EN:1; +} SYSCLK_APBCLK_T; + +typedef struct +{ + __IO uint32_t HCLK_S:3; + __IO uint32_t STCLK_S:3; + __I uint32_t RESERVE:26; +} SYSCLK_CLKSEL0_T; + + +typedef struct +{ + __IO uint32_t WDG_S:2; + __IO uint32_t ADC_S:2; + __I uint32_t RESERVE1:4; + __IO uint32_t TMR0_S:3; + __I uint32_t RESERVE2:1; + __IO uint32_t TMR1_S:3; + __I uint32_t RESERVE3:1; + __IO uint32_t TMR2_S:3; + __I uint32_t RESERVE4:1; + __IO uint32_t TMR3_S:3; + __I uint32_t RESERVE5:1; + __IO uint32_t UART_S:2; + __IO uint32_t CAN_S:2; + __IO uint32_t PWM10_S:2; + __IO uint32_t PWM32_S:2; +} SYSCLK_CLKSEL1_T; + +typedef struct +{ + __IO uint32_t HCLK_N:4; + __IO uint32_t USB_N:4; + __IO uint32_t UART_N:4; + __IO uint32_t CAN_N:4; + __IO uint32_t ADC_N:8; + __I uint32_t RESERVE:8; +} SYSCLK_CLKDIV_T; + +typedef struct +{ + __IO uint32_t FB_DV:9; + __IO uint32_t IN_DV:5; + __IO uint32_t OUT_DV:2; + __IO uint32_t PD:1; + __IO uint32_t BP:1; + __IO uint32_t OE:1; + __IO uint32_t PLL_SRC:1; + __I uint32_t RESERVE:12; +} SYSCLK_PLLCON_T; + +typedef struct +{ + __IO uint32_t TEST_SEL:8; + __I uint32_t RESERVE:24; +} SYSCLK_TREG_T; + +typedef struct +{ + SYSCLK_PWRCON_T PWRCON; + SYSCLK_AHBCLK_T AHBCLK; + SYSCLK_APBCLK_T APBCLK; + uint32_t RESERVED0; + SYSCLK_CLKSEL0_T CLKSEL0; + SYSCLK_CLKSEL1_T CLKSEL1; + SYSCLK_CLKDIV_T CLKDIV; + uint32_t RESERVED1; + SYSCLK_PLLCON_T PLLCON; + +} SYSCLK_T; + +/*---------------------------- Global Controller -----------------------------*/ +typedef __I uint32_t GCR_PDID_T; + +typedef struct +{ + __IO uint32_t RSTS_POR:1; + __IO uint32_t RSTS_PAD:1; + __IO uint32_t RSTS_WDG:1; + __IO uint32_t RSTS_LVR:1; + __IO uint32_t RSTS_BOD:1; + __IO uint32_t RSTS_MCU:1; + __IO uint32_t RSTS_PMU:1; + __I uint32_t RESERVE:25; +} GCR_RSTSRC_T; + + +typedef struct +{ + __IO uint32_t CHIP_RST:1; + __IO uint32_t CPU_RST:1; + __IO uint32_t PDMA_RST:1; + __I uint32_t RESERVE:29; +} GCR_IPRSTC1_T; + +typedef struct +{ + __I uint32_t RESERVE0:1; + __IO uint32_t GPIO_RST:1; + __IO uint32_t TMR0_RST:1; + __IO uint32_t TMR1_RST:1; + __IO uint32_t TMR2_RST:1; + __IO uint32_t TMR3_RST:1; + __I uint32_t RESERVE1:2; + __IO uint32_t I2C0_RST:1; + __IO uint32_t I2C1_RST:1; + __I uint32_t RESERVE2:2; + __IO uint32_t SPI0_RST:1; + __IO uint32_t SPI1_RST:1; + __IO uint32_t SPI2_RST:1; + __IO uint32_t SPI3_RST:1; + __IO uint32_t UART0_RST:1; + __IO uint32_t UART1_RST:1; + __I uint32_t RESERVE3:2; + __IO uint32_t PWM_RST:1; + __I uint32_t RESERVE4:1; + __IO uint32_t ACMP_RST:1; + __IO uint32_t PS2_RST:1; + __IO uint32_t CAN0_RST:1; + __IO uint32_t CAN1_RST:1; + __I uint32_t RESERVE5:1; + __IO uint32_t USBD_RST:1; + __IO uint32_t ADC_RST:1; + __I uint32_t RESERVE6:3; +} GCR_IPRSTC2_T; + +typedef __IO uint32_t GCR_MISCR_T; + + +typedef struct +{ + __IO uint32_t BOD_EN:1; + __IO uint32_t BOD_VL:2; + __IO uint32_t BOD_RSTEN:1; + __IO uint32_t BOD_BYP_EN:1; + __IO uint32_t BOD_LPM:1; + __IO uint32_t BOD_OUT:1; + __IO uint32_t LVR_EN:1; + __IO uint32_t VTEMP_EN:1; + __IO uint32_t LDO_BYP:1; + __I uint32_t RESERVE1:22; +} GCR_BODCR_T; + +typedef __IO uint32_t GCR_PORCR_T; + + +typedef struct +{ + __IO uint32_t ADC0:1; + __IO uint32_t ADC1:1; + __IO uint32_t ADC2:1; + __IO uint32_t ADC3:1; + __IO uint32_t ADC4:1; + __IO uint32_t ADC5:1; + __IO uint32_t ADC6:1; + __IO uint32_t ADC7:1; + __IO uint32_t I2C0_SDA:1; + __IO uint32_t I2C0_SCL:1; + __IO uint32_t I2C1_SDA:1; + __IO uint32_t I2C1_SCL:1; + __IO uint32_t PWM0:1; + __IO uint32_t PWM1:1; + __IO uint32_t PWM2:1; + __IO uint32_t PWM3:1; + __IO uint32_t SCHMITT:16; +} GCR_GPAMFP_T; + +typedef struct +{ + __IO uint32_t UART0_RX:1; + __IO uint32_t UART0_TX:1; + __IO uint32_t UART0_nRTS:1; + __IO uint32_t UART0_nCTS:1; + __IO uint32_t UART1_RX:1; + __IO uint32_t UART1_TX:1; + __IO uint32_t UART1_nRTS:1; + __IO uint32_t UART1_nCTS:1; + __IO uint32_t TM0:1; + __IO uint32_t TM1:1; + __IO uint32_t TM2:1; + __IO uint32_t TM3:1; + __IO uint32_t CPO0:1; + __IO uint32_t CPO1:1; + __IO uint32_t INT0:1; + __IO uint32_t INT1:1; + __IO uint32_t SCHMITT:16; +} GCR_GPBMFP_T; + +typedef struct +{ + __IO uint32_t SPI0_SS0:1; + __IO uint32_t SPI0_CLK:1; + __IO uint32_t SPI0_MISO0:1; + __IO uint32_t SPI0_MOSI0:1; + __IO uint32_t SPI0_MISO1:1; + __IO uint32_t SPI0_MOSI1:1; + __IO uint32_t CPP0:1; + __IO uint32_t CPN0:1; + __IO uint32_t SPI1_SS0:1; + __IO uint32_t SPI1_CLK:1; + __IO uint32_t SPI1_MISO0:1; + __IO uint32_t SPI1_MOSI0:1; + __IO uint32_t SPI1_MISO1:1; + __IO uint32_t SPI1_MOSI1:1; + __IO uint32_t CPP1:1; + __IO uint32_t CPN1:1; + __IO uint32_t SCHMITT:16; +} GCR_GPCMFP_T; + +typedef struct +{ + __IO uint32_t SPI2_SS0:1; + __IO uint32_t SPI2_CLK:1; + __IO uint32_t SPI2_MISO0:1; + __IO uint32_t SPI2_MOSI0:1; + __IO uint32_t SPI2_MISO1:1; + __IO uint32_t SPI2_MOSI1:1; + __IO uint32_t CAN0_RX:1; + __IO uint32_t CAN0_TX:1; + __IO uint32_t SPI3_SS0:1; + __IO uint32_t SPI3_CLK:1; + __IO uint32_t SPI3_MISO0:1; + __IO uint32_t SPI3_MOSI0:1; + __IO uint32_t SPI3_MISO1:1; + __IO uint32_t SPI3_MOSI1:1; + __IO uint32_t CAN1_RX:1; + __IO uint32_t CAN1_TX:1; + __IO uint32_t SCHMITT:16; +} GCR_GPDMFP_T; + + +typedef struct +{ + __I uint32_t RESERVE:16; + __IO uint32_t SCHMITT:16; +} GCR_GPEMFP_T; + +typedef struct +{ + __IO uint32_t SPI0_SS1:1; /* GPB10 */ + __IO uint32_t SPI1_SS1:1; /* GPB9 */ + __IO uint32_t SPI2_SS1:1; /* GPA7 */ + __IO uint32_t SPI3_SS1:1; /* GPB14 */ + __I uint32_t RESERVE:28; + +} GCR_USPIMFP_T; + +typedef __IO uint32_t GCR_REGLOCK_T; +typedef __IO uint32_t GCR_RCADJ_T; + + +typedef struct +{ + __IO uint32_t INTSRC:3; + __I uint32_t RESERVE:29; +} GCR_INTSRC_T; + +typedef struct +{ + __IO uint32_t NMISEL:5; + __I uint32_t RESERVE0:2; + __IO uint32_t INT_TEST:1; + __I uint32_t RESERVE1:24; +} GCR_NMISEL_T; + + +typedef __IO uint32_t GCR_MCUIRQ_T; + +typedef struct +{ + GCR_PDID_T PDID; + GCR_RSTSRC_T RSTSRC; + GCR_IPRSTC1_T IPRSTC1; + GCR_IPRSTC2_T IPRSTC2; + uint32_t RESERVE0; + GCR_MISCR_T MISCR; + GCR_BODCR_T BODCR; + GCR_PORCR_T PORCR; + uint32_t RESERVE1[4]; + GCR_GPAMFP_T GPAMFP; + GCR_GPBMFP_T GPBMFP; + GCR_GPCMFP_T GPCMFP; + GCR_GPDMFP_T GPDMFP; + GCR_GPEMFP_T GPEMFP; + uint32_t RESERVE2[3]; + GCR_USPIMFP_T USPIMFP; + uint32_t RESERVE3[43]; + GCR_REGLOCK_T REGLOCK; + uint32_t RESERVE4[3]; + GCR_RCADJ_T RCADJ; +} GCR_T; + + + +typedef struct +{ + GCR_INTSRC_T INTSRC; + GCR_NMISEL_T NMISEL; + GCR_MCUIRQ_T MCUIRQ; +} GCR_INT_T; + +/*-------------------------- FLASH Memory Controller -------------------------*/ +typedef struct +{ + __IO uint32_t ISPEN:1; + __IO uint32_t BS:1; + __I uint32_t RESERVE0:3; + __IO uint32_t LDUEN:1; + __IO uint32_t ISPFF:1; + __IO uint32_t SWRST:1; + __IO uint32_t PT:3; + __I uint32_t RESERVE1:1; + __IO uint32_t ET:3; + __I uint32_t RESERVE2:17; + +} FMC_ISPCON_T; + +typedef __IO uint32_t FMC_ISPADR_T; +typedef __IO uint32_t FMC_ISPDAT_T; + +typedef struct +{ + __IO uint32_t FCTRL:4; + __IO uint32_t FCEN:1; + __IO uint32_t FOEN:1; + __I uint32_t RESERVE:26; +} FMC_ISPCMD_T; + +typedef struct +{ + __IO uint32_t ISPGO:1; + __I uint32_t RESERVE:31; +} FMC_ISPTRG_T; + +typedef __I uint32_t FMC_DFBADR_T; + +typedef struct +{ + __IO uint32_t FPSEN:1; + __IO uint32_t FATS:3; + __I uint32_t RESERVE:28; +} FMC_FATCON_T; + +typedef struct +{ + FMC_ISPCON_T ISPCON; + FMC_ISPADR_T ISPADR; + FMC_ISPDAT_T ISPDAT; + FMC_ISPCMD_T ISPCMD; + FMC_ISPTRG_T ISPTRG; + FMC_DFBADR_T DFBADR; + FMC_FATCON_T FATCON; +} FMC_T; + + +/*------------------------ PS2 Device Interface Controller -------------------*/ +typedef struct +{ + __IO uint32_t PS2EN:1; + __IO uint32_t TXINTEN:1; + __IO uint32_t RXINTEN:1; + __IO uint32_t TXFIFO_DEPTH:4; + __IO uint32_t ACK:1; + __IO uint32_t CLRFIFO:1; + __IO uint32_t OVERRIDE:1; + __IO uint32_t FPS2CLK:1; + __IO uint32_t FPS2DAT:1; + __I uint32_t RESERVE:20; +} PS2_CON_T; + +typedef __IO uint32_t PS2_DATA_T; + +typedef struct +{ + __IO uint32_t PS2CLK:1; + __IO uint32_t PS2DATA:1; + __IO uint32_t FRAMERR:1; + __IO uint32_t RXPARTY:1; + __IO uint32_t RXBUSY:1; + __IO uint32_t TXBUSY:1; + __IO uint32_t RXOVF:1; + __IO uint32_t TXEMPTY:1; + __IO uint32_t BYTEIDX:4; + __I uint32_t RESERVE:20; +} PS2_STATUS_T; + +typedef __IO uint32_t PS2_INTID_T; + +typedef struct +{ + PS2_CON_T PS2CON; + PS2_DATA_T TXDATA[4]; + PS2_DATA_T RXDATA; + PS2_STATUS_T STATUS; + PS2_INTID_T INTID; +} PS2_T; + +/*---------------------------- CAN Bus Controller ----------------------------*/ +typedef struct +{ + __IO uint32_t RSTM:1; + __IO uint32_t LOM:1; + __I uint32_t RESERVE:30; + +} CAN_OPMODE_T; + +typedef struct +{ + __IO uint32_t TR:1; + __IO uint32_t ABRT:1; + __I uint32_t RESERVE2:3; + __IO uint32_t OVERFLOAD_EN:1; + __IO uint32_t WAKEUP_EN:1; + __IO uint32_t CAN_EN:1; + __I uint32_t RESERVE:24; +} CAN_CMD_T; + +typedef struct +{ + __I uint32_t RESERVE0:3; + __IO uint32_t TCS:1; + __IO uint32_t RS:1; + __IO uint32_t TS:1; + __IO uint32_t BS:1; + __IO uint32_t BS2:1; + __IO uint32_t EAS:1; + __IO uint32_t EPS:1; + __I uint32_t RESERVE1:22; +} CAN_BSR_T; + +typedef struct +{ + __IO uint32_t RI:1; + __IO uint32_t TI:1; + __I uint32_t RESERVE0:2; + __IO uint32_t WUI:1; + __I uint32_t RESERVE1:1; + __IO uint32_t ALI:1; + __IO uint32_t BEI:1; + __I uint32_t RESERVE2:24; +} CAN_INTR_T; + +typedef struct +{ + __IO uint32_t RIE:1; + __IO uint32_t TIE:1; + __I uint32_t RESERVE0:2; + __IO uint32_t WUIE:1; + __I uint32_t RESERVE1:1; + __IO uint32_t ALIE:1; + __IO uint32_t BEIE:1; + __I uint32_t RESERVE2:24; +} CAN_INTEN_T; + +typedef struct +{ + __IO uint32_t BRP:4; + __IO uint32_t SJW:2; + __IO uint32_t TSEG1:5; + __IO uint32_t TSEG2:4; + __IO uint32_t SAMP:1; + __I uint32_t RESERVE2:16; +} CAN_BTIMR_T; + +typedef struct +{ + __IO uint32_t BIT_ERR:4; + __IO uint32_t ACK_ERR:2; + __IO uint32_t CRC_ERR:5; + __IO uint32_t FORM_ERR:4; + __IO uint32_t STUFF_ERR:1; + __I uint32_t RESERVE:16; +} CAN_ERRCR_T; + +typedef struct +{ + __IO uint32_t RECNT:8; + __I uint32_t RESERVE:24; +} CAN_RECNTR_T; + +typedef struct +{ + __IO uint32_t TECNT:8; + __I uint32_t RESERVE:24; +} CAN_TECNTR_T; + +typedef struct +{ + __IO uint32_t TXDLC:6; + __IO uint32_t TXRTR:1; + __IO uint32_t TXFF:1; + __I uint32_t RESERVE:24; +} CAN_TXFINFO_T; + +typedef struct +{ + __I uint32_t RESERVE:3; + __IO uint32_t TXID:29; +} CAN_TXID_T; + +typedef __IO uint32_t CAN_TXDATA_T; + +typedef struct +{ + __IO uint32_t RXDLC:4; + __I uint32_t RESERVE0:2; + __IO uint32_t RXRTR:1; + __IO uint32_t RXIDE:1; + __I uint32_t RESERVE1:24; +} CAN_RXFINFO_T; + +typedef struct +{ + __I uint32_t RESERVE:3; + __IO uint32_t RXID:29; +} CAN_RXID_T; + +typedef __IO uint32_t CAN_RXDATA_T; + +typedef struct +{ + __I uint32_t RESERVE:3; + __IO uint32_t ACR:29; +} CAN_ACR_T; + +typedef struct +{ + __I uint32_t RESERVE:3; + __IO uint32_t AMR:29; +} CAN_AMR_T; + + +typedef struct +{ + __I uint32_t RESERVE:32; +} CAN_RESERVE_T; + +typedef struct +{ + CAN_OPMODE_T OPMODE; + CAN_CMD_T CMD; + CAN_BSR_T BSR; + CAN_INTR_T INTR; + + CAN_INTEN_T INTEN; + CAN_BTIMR_T BTIMR; + CAN_RESERVE_T PROTECT[2]; + + CAN_ERRCR_T ERRCR; + CAN_RESERVE_T PROTECT1; + CAN_RECNTR_T RECNTR; + CAN_TECNTR_T TECNTR; + + CAN_TXFINFO_T TXFINFO; + CAN_TXID_T TXID; + CAN_TXDATA_T TXDATA[2]; + + CAN_RXFINFO_T RXFINFO; + CAN_RXID_T RXID; + CAN_RXDATA_T RX_DATA[2]; + CAN_ACR_T ACR; + CAN_AMR_T AMR; +} CAN_T; + + +/*--------------------------- USB Device Controller --------------------------*/ +typedef struct +{ + __IO uint32_t BUS:1; + __IO uint32_t USB:1; + __IO uint32_t FLD:1; + __IO uint32_t WAKEUP:1; + __I uint32_t RESERVE0:4; + __IO uint32_t WAKEUP_EN:1; + __I uint32_t RESERVE1:6; + __IO uint32_t INNAK_EN:1; + __I uint32_t RESERVE2:16; +} USBD_IEF_T; + +typedef struct +{ + __IO uint32_t BUS:1; + __IO uint32_t USB:1; + __IO uint32_t FLD:1; + __IO uint32_t WAKEUP:1; + __I uint32_t RESERVE0:12; + __IO uint32_t EPTF:6; + __I uint32_t RESERVE1:9; + __IO uint32_t SETUP:1; +} USBD_EVF_T; + +typedef struct +{ + __IO uint32_t FADDR:7; + __I uint32_t RESERVE:25; +} USBD_FADDR_T; + +typedef struct +{ + __I uint32_t RESERVE0:7; + __IO uint32_t OVERRUN:1; + __IO uint32_t STS0:3; + __IO uint32_t STS1:3; + __IO uint32_t STS2:3; + __IO uint32_t STS3:3; + __IO uint32_t STS4:3; + __IO uint32_t STS5:3; + __I uint32_t RESERVE1:6; +} USBD_STS_T; + + + +typedef struct +{ + __IO uint32_t USBRST:1; + __IO uint32_t SUSPEND:1; + __IO uint32_t RESUME:1; + __IO uint32_t TIMEOUT:1; + __IO uint32_t PHY_EN:1; + __IO uint32_t RWAKEUP:1; + __I uint32_t RESERVE0:1; + __IO uint32_t USB_EN:1; + __IO uint32_t DPPU_EN:1; + __IO uint32_t PDB:1; + __I uint32_t RESERVE1:22; +} USBD_ATTR_T; + + + +typedef struct +{ + __IO uint32_t FLODET:1; + __I uint32_t RESERVE:31; +} USBD_FLODET_T; + +typedef struct +{ + __I uint32_t RESERVE0:3; + __IO uint32_t BUFSEG:6; + __I uint32_t RESERVE:23; +} USBD_BUFSEG_T; + +typedef struct +{ + __IO uint32_t MXPLD:9; + __I uint32_t RESERVE:23; +} USBD_MXPLD_T; + +typedef struct +{ + __IO uint32_t EPT:4; + __IO uint32_t ISOCH:1; + __IO uint32_t STATE:2; + __IO uint32_t DSQ:1; + __I uint32_t RESERVE0:1; + __IO uint32_t STALL_CTL:1; + __I uint32_t RESERVE1:22; +} USBD_CFG_T; + +typedef struct +{ + __IO uint32_t CFGP:1; + __IO uint32_t STALL:1; + __I uint32_t RESERVE:30; +} USBD_CFGP_T; + +typedef struct +{ + __IO uint32_t DRVSE0:1; + __I uint32_t RESERVE:31; +} USBD_DRVSE0_T; + +typedef struct +{ + __IO uint32_t BISTEN:1; + __IO uint32_t FINISH:1; + __IO uint32_t BISTFAIL:1; + __I uint32_t RESERVE:29; +} USBD_BIST_T; + +typedef struct +{ + __IO uint32_t PDMA_RW:1; + __IO uint32_t PDMA_EN:1; + __I uint32_t RESERVE:30; +} USBD_PDMA_T; + + +typedef struct +{ + USBD_BUFSEG_T BUFSEG; + USBD_MXPLD_T MXPLD; + USBD_CFG_T CFG; + USBD_CFGP_T CFGP; +} USBD_EP_T; + +typedef struct +{ + USBD_IEF_T IEF; + USBD_EVF_T EVF; + USBD_FADDR_T FADDR; + USBD_STS_T STS; + USBD_ATTR_T ATTR; + USBD_FLODET_T FLODET; + USBD_BUFSEG_T BUFSEG; + uint32_t RESERVE0; + USBD_EP_T EP[6]; + uint32_t RESERVE1[4]; + USBD_DRVSE0_T DRVSE0; + uint32_t RESERVE2[3]; + USBD_BIST_T BIST; + USBD_PDMA_T PDMA; +} USBD_T; + + +/*------------------------------ PDMA Controller -----------------------------*/ +typedef struct +{ + __IO uint32_t PDMACEN:1; + __IO uint32_t SW_RST:1; + __IO uint32_t MODE_SEL:2; + __IO uint32_t SAD_SEL:2; + __IO uint32_t DAD_SEL:2; + __I uint32_t RESERVE0:4; + __IO uint32_t WAR_BCR_SEL:4; + __I uint32_t RESERVE1:3; + __IO uint32_t APB_TWS:2; + __I uint32_t RESERVE2:2; + __IO uint32_t TRIG_EN:1; + __I uint32_t RESERVE3:8; +} PDMA_CSR_T; + +typedef __IO uint32_t PDMA_SAR_T; +typedef __IO uint32_t PDMA_DAR_T; + +typedef __IO uint32_t PDMA_BCR_T; + +typedef __IO uint32_t PDMA_CSAR_T; +typedef __IO uint32_t PDMA_CDAR_T; + +typedef struct +{ + __IO uint32_t CBCR:24; + __I uint32_t RESERVE:8; +} PDMA_CBCR_T; + +typedef struct +{ + __IO uint32_t TABORT_IE:1; + __IO uint32_t BLKD_IE:1; + __IO uint32_t WAR_IE:1; + __I uint32_t RESERVE:29; +} PDMA_IER_T; + +//typedef __IO uint32_t PDMA_ISR_T; + +typedef struct +{ + __IO uint32_t TABORT_IF:1; + __IO uint32_t BLKD_IF:1; + __I uint32_t RESERVE:6; + __IO uint32_t WAR_IF:4; + __I uint32_t RESERVE1:3; + __IO uint32_t BUSY:1; + __I uint32_t RESERVE2:15; + __IO uint32_t INTR:1; +} PDMA_ISR_T; + +typedef __IO uint32_t PDMA_SBUF_T; + +typedef struct +{ + __IO uint32_t PDMA_RST:1; + __I uint32_t RESERVE0:7; + __IO uint32_t HCLK0_EN:1; + __IO uint32_t HCLK1_EN:1; + __IO uint32_t HCLK2_EN:1; + __IO uint32_t HCLK3_EN:1; + __IO uint32_t HCLK4_EN:1; + __IO uint32_t HCLK5_EN:1; + __IO uint32_t HCLK6_EN:1; + __IO uint32_t HCLK7_EN:1; + __IO uint32_t HCLK8_EN:1; + __IO uint32_t HCLK9_EN:1; + __IO uint32_t HCLK10_EN:1; + __IO uint32_t HCLK11_EN:1; + __I uint32_t RESERVE1:12; +} PDMA_GCRCSR_T; + +typedef struct +{ + __IO uint32_t UART0_RXSEL:4; + __IO uint32_t UART0_TXSEL:4; + __IO uint32_t UART1_RXSEL:4; + __IO uint32_t UART1_TXSEL:4; + __IO uint32_t USBD_RXSEL:4; + __IO uint32_t USBD_TXSEL:4; + __IO uint32_t ADC_RXSEL:4; + __IO uint32_t ADC_TXSEL:4; +} PDMA_PDSSR1_T; + + +typedef struct +{ + __IO uint32_t SPI0_RXSEL:4; + __IO uint32_t SPI0_TXSEL:4; + __IO uint32_t SPI1_RXSEL:4; + __IO uint32_t SPI1_TXSEL:4; + __IO uint32_t SPI2_RXSEL:4; + __IO uint32_t SPI2_TXSEL:4; + __IO uint32_t SPI3_RXSEL:4; + __IO uint32_t SPI3_TXSEL:4; +} PDMA_PDSSR0_T; + +typedef __IO uint32_t PDMA_GCRISR_T; + +typedef struct +{ + PDMA_GCRCSR_T GCRCSR; + PDMA_PDSSR0_T PDSSR0; + PDMA_PDSSR1_T PDSSR1; + PDMA_GCRISR_T GCRISR; +} PDMA_GCR_T; + +typedef struct +{ + PDMA_CSR_T CSR; + PDMA_SAR_T SAR; + PDMA_DAR_T DAR; + PDMA_BCR_T BCR; + uint32_t POINT; + PDMA_CSAR_T CSAR; + PDMA_CDAR_T CDAR; + PDMA_CBCR_T CBCR; + PDMA_IER_T IER; + PDMA_ISR_T ISR; + PDMA_SBUF_T SBUF[4]; +} PDMA_T; + +/*----------------------------- PWM Controller -------------------------------*/ +typedef struct +{ + __IO uint32_t CP0:8; + __IO uint32_t CP1:8; + __IO uint32_t DZI0:8; + __IO uint32_t DZI1:8; +} PWM_PPR_T; + +typedef struct +{ + __IO uint32_t CSR0:3; + __I uint32_t RESERVE0:1; + __IO uint32_t CSR1:3; + __I uint32_t RESERVE1:1; + __IO uint32_t CSR2:3; + __I uint32_t RESERVE2:1; + __IO uint32_t CSR3:3; + __I uint32_t RESERVE:17; +} PWM_CSR_T; + +typedef struct +{ + __IO uint32_t CH0EN:1; + __I uint32_t RESERVE0:1; + __IO uint32_t CH0INV:1; + __IO uint32_t CH0MOD:1; + __IO uint32_t DZEN0:1; + __IO uint32_t DZEN1:1; + __I uint32_t RESERVE1:2; + __IO uint32_t CH1EN:1; + __I uint32_t RESERVE2:1; + __IO uint32_t CH1INV:1; + __IO uint32_t CH1MOD:1; + __I uint32_t RESERVE3:4; + __IO uint32_t CH2EN:1; + __I uint32_t RESERVE4:1; + __IO uint32_t CH2INV:1; + __IO uint32_t CH2MOD:1; + __I uint32_t RESERVE5:4; + __IO uint32_t CH3EN:1; + __I uint32_t RESERVE6:1; + __IO uint32_t CH3INV:1; + __IO uint32_t CH3MOD:1; + __I uint32_t RESERVE7:4; +} PWM_PCR_T; + +typedef __IO uint32_t PWM_CNR_T; + +typedef __IO uint32_t PWM_CMR_T; + +typedef __IO uint32_t PWM_PDR_T; + +typedef struct +{ + __IO uint32_t PWMIE0:1; + __IO uint32_t PWMIE1:1; + __IO uint32_t PWMIE2:1; + __IO uint32_t PWMIE3:1; + __I uint32_t RESERVE:28; +} PWM_PIER_T; + + +typedef struct +{ + __IO uint32_t PWMIF0:1; + __IO uint32_t PWMIF1:1; + __IO uint32_t PWMIF2:1; + __IO uint32_t PWMIF3:1; + __I uint32_t RESERVE:28; +} PWM_PIIR_T; + + +typedef struct +{ + __IO uint32_t INV0:1; + __IO uint32_t CRL_IE0:1; + __IO uint32_t CFL_IE0:1; + __IO uint32_t CAPCH0EN:1; + __IO uint32_t CAPIF0:1; + __I uint32_t RESERVE0:1; + __IO uint32_t CRLRI0:1; + __IO uint32_t CFLRI0:1; + __I uint32_t RESERVE1:8; + __IO uint32_t INV1:1; + __IO uint32_t CRL_IE1:1; + __IO uint32_t CFL_IE1:1; + __IO uint32_t CAPCH1EN:1; + __IO uint32_t CAPIF1:1; + __I uint32_t RESERVE2:1; + __IO uint32_t CRLRI1:1; + __IO uint32_t CFLRI1:1; + __I uint32_t RESERVE3:8; +} PWM_CCR0_T; + + +typedef struct +{ + __IO uint32_t INV2:1; + __IO uint32_t CRL_IE2:1; + __IO uint32_t CFL_IE2:1; + __IO uint32_t CAPCH2EN:1; + __IO uint32_t CAPIF2:1; + __I uint32_t RESERVE0:1; + __IO uint32_t CRLRI2:1; + __IO uint32_t CFLRI2:1; + __I uint32_t RESERVE1:8; + __IO uint32_t INV3:1; + __IO uint32_t CRL_IE3:1; + __IO uint32_t CFL_IE3:1; + __IO uint32_t CAPCH3EN:1; + __IO uint32_t CAPIF3:1; + __I uint32_t RESERVE2:1; + __IO uint32_t CRLRI3:1; + __IO uint32_t CFLRI3:1; + __I uint32_t RESERVE3:8; +} PWM_CCR1_T; + + +typedef __IO uint32_t PWM_CRLR_T; + +typedef __IO uint32_t PWM_CFLR_T; + +typedef __IO uint32_t PWM_CAPENR_T; + +typedef struct +{ + __IO uint32_t PWM0:1; + __IO uint32_t PWM1:1; + __IO uint32_t PWM2:1; + __IO uint32_t PWM3:1; + __I uint32_t RESERVE:28; +} PWM_POE_T; + + +typedef struct +{ + PWM_PPR_T PPR; + PWM_CSR_T CSR; + PWM_PCR_T PCR; + PWM_CNR_T CNR0; + PWM_CMR_T CMR0; + PWM_PDR_T PDR0; + PWM_CNR_T CNR1; + PWM_CMR_T CMR1; + PWM_PDR_T PDR1; + PWM_CNR_T CNR2; + PWM_CMR_T CMR2; + PWM_PDR_T PDR2; + PWM_CNR_T CNR3; + PWM_CMR_T CMR3; + PWM_PDR_T PDR3; + __I uint32_t RESERVE0; + PWM_PIER_T PIER; + PWM_PIIR_T PIIR; + __I uint32_t RESERVE1[2]; + PWM_CCR0_T CCR0; + PWM_CCR1_T CCR1; + PWM_CRLR_T CRLR0; + PWM_CFLR_T CFLR0; + PWM_CRLR_T CRLR1; + PWM_CFLR_T CFLR1; + PWM_CRLR_T CRLR2; + PWM_CFLR_T CFLR2; + PWM_CRLR_T CRLR3; + PWM_CFLR_T CFLR3; + PWM_CAPENR_T CAPENR; + PWM_POE_T POE; + + +} PWM_T; + + + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Peripheral and SRAM base address */ +#define FLASH_BASE (( uint32_t)0x00000000) +#define SRAM_BASE (( uint32_t)0x20000000) +#define AHB_BASE (( uint32_t)0x50000000) +#define APB1_BASE (( uint32_t)0x40000000) +#define APB2_BASE (( uint32_t)0x40100000) + +/* Peripheral memory map */ +#define GPIO_BASE (AHB_BASE + 0x4000) + +#define GPIOA_BASE (GPIO_BASE ) +#define GPIOB_BASE (GPIO_BASE + 0x0040) +#define GPIOC_BASE (GPIO_BASE + 0x0080) +#define GPIOD_BASE (GPIO_BASE + 0x00C0) +#define GPIOE_BASE (GPIO_BASE + 0x0100) +#define GPIO_DBNCECON_BASE (GPIO_BASE + 0x0180) + +#define UART0_BASE (APB1_BASE + 0x50000) +#define UART1_BASE (APB2_BASE + 0x50000) + +#define TIMER0_BASE (APB1_BASE + 0x10000) +#define TIMER1_BASE (APB1_BASE + 0x10020) +#define TIMER2_BASE (APB2_BASE + 0x10000) +#define TIMER3_BASE (APB2_BASE + 0x10020) + +#define WDT_BASE (APB1_BASE + 0x4000) + +#define SPI0_BASE (APB1_BASE + 0x30000) +#define SPI1_BASE (APB1_BASE + 0x34000) +#define SPI2_BASE (APB2_BASE + 0x30000) +#define SPI3_BASE (APB2_BASE + 0x34000) + +#define I2C0_BASE (APB1_BASE + 0x20000) +#define I2C1_BASE (APB2_BASE + 0x20000) + +#define RTC_BASE (APB1_BASE + 0x08000) + +#define ADC_BASE (APB1_BASE + 0xE0000) +#define ADC_ADSR (ADC_BASE + 0x30) + +#define ACMP_BASE (APB1_BASE + 0xD0000) + +#define SYSCLK_BASE (AHB_BASE + 0x00200) + +#define GCR_BASE (AHB_BASE + 0x00000) + +#define INT_BASE (AHB_BASE + 0x00300) + +#define FMC_BASE (AHB_BASE + 0x0C000) + +#define PS2_BASE (APB2_BASE + 0x00000) + +#define CAN0_BASE (APB2_BASE + 0x80000) +#define CAN1_BASE (APB2_BASE + 0x84000) + +#define USBD_BASE (APB1_BASE + 0x60000) + +#define PDMA0_BASE (AHB_BASE + 0x08000) +#define PDMA1_BASE (AHB_BASE + 0x08100) +#define PDMA2_BASE (AHB_BASE + 0x08200) +#define PDMA3_BASE (AHB_BASE + 0x08300) +#define PDMA4_BASE (AHB_BASE + 0x08400) +#define PDMA5_BASE (AHB_BASE + 0x08500) +#define PDMA6_BASE (AHB_BASE + 0x08600) +#define PDMA7_BASE (AHB_BASE + 0x08700) +#define PDMA8_BASE (AHB_BASE + 0x08800) +#define PDMA9_BASE (AHB_BASE + 0x08900) +#define PDMA10_BASE (AHB_BASE + 0x08A00) +#define PDMA11_BASE (AHB_BASE + 0x08B00) +#define PDMA_GCR_BASE (AHB_BASE + 0x08F00) + +#define PWM_BASE (APB1_BASE + 0x40000) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define GPIOA ((GPIO_T *) GPIOA_BASE) +#define GPIOB ((GPIO_T *) GPIOB_BASE) +#define GPIOC ((GPIO_T *) GPIOC_BASE) +#define GPIOD ((GPIO_T *) GPIOD_BASE) +#define GPIOE ((GPIO_T *) GPIOE_BASE) +#define GPIO_DBNCECON ((GPIO_DBNCECON_T *) GPIO_DBNCECON_BASE) + +#define UART0 ((UART_T *) UART0_BASE) +#define UART1 ((UART_T *) UART1_BASE) + +#define TIMER0 ((TIMER_T *) TIMER0_BASE) +#define TIMER1 ((TIMER_T *) TIMER1_BASE) +#define TIMER2 ((TIMER_T *) TIMER2_BASE) +#define TIMER3 ((TIMER_T *) TIMER3_BASE) + +#define WDT ((WDT_T *) WDT_BASE) + +#define SPI0 ((SPI_T *) SPI0_BASE) +#define SPI1 ((SPI_T *) SPI1_BASE) +#define SPI2 ((SPI_T *) SPI2_BASE) +#define SPI3 ((SPI_T *) SPI3_BASE) + +#define I2C0 ((I2C_T *) I2C0_BASE) +#define I2C1 ((I2C_T *) I2C1_BASE) + +#define RTC ((RTC_T *) RTC_BASE) + +#define ADC ((ADC_T *) ADC_BASE) + +#define ACMP ((ACMP_T *) ACMP_BASE) + +#define SYSCLK ((SYSCLK_T *) SYSCLK_BASE) + +#define SYS ((GCR_T *) GCR_BASE) + +#define SYSINT ((GCR_INT_T *) INT_BASE) + +#define FMC ((FMC_T *) FMC_BASE) + +#define PS2 ((PS2_T *) PS2_BASE) + +#define CAN0 ((CAN_T *) CAN0_BASE) +#define CAN1 ((CAN_T *) CAN1_BASE) + +#define USBD ((USBD_T *) USBD_BASE) + +#define PDMA0 ((PDMA_T *) PDMA0_BASE) +#define PDMA1 ((PDMA_T *) PDMA1_BASE) +#define PDMA2 ((PDMA_T *) PDMA2_BASE) +#define PDMA3 ((PDMA_T *) PDMA3_BASE) +#define PDMA4 ((PDMA_T *) PDMA4_BASE) +#define PDMA5 ((PDMA_T *) PDMA5_BASE) +#define PDMA6 ((PDMA_T *) PDMA6_BASE) +#define PDMA7 ((PDMA_T *) PDMA7_BASE) +#define PDMA8 ((PDMA_T *) PDMA8_BASE) +#define PDMA9 ((PDMA_T *) PDMA9_BASE) +#define PDMA10 ((PDMA_T *) PDMA10_BASE) +#define PDMA11 ((PDMA_T *) PDMA11_BASE) +#define PDMA_GCR ((PDMA_GCR_T *) PDMA_GCR_BASE) + +#define PWM ((PWM_T *) PWM_BASE) + +#define UNLOCKREG(x) *((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x59;*((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x16;*((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x88 +#define LOCKREG(x) *((__IO uint32_t *)(GCR_BASE + 0x100)) = 0x00; + +#define REGCOPY(dest, src) *((uint32_t *)&(dest)) = *((uint32_t *)&(src)) +#define CLEAR(dest) *((uint32_t *)&(dest)) = 0 + +//============================================================================= +typedef volatile unsigned char vu8; +typedef volatile unsigned long vu32; +typedef volatile unsigned short vu16; +#define M8(adr) (*((vu8 *) (adr))) +#define M16(adr) (*((vu16 *) (adr))) +#define M32(adr) (*((vu32 *) (adr))) + +#define outpw(port,value) *((volatile unsigned int *)(port))=value +#define inpw(port) (*((volatile unsigned int *)(port))) +#define outpb(port,value) *((volatile unsigned char *)(port))=value +#define inpb(port) (*((volatile unsigned char *)(port))) +#define outps(port,value) *((volatile unsigned short *)(port))=value +#define inps(port) (*((volatile unsigned short *)(port))) + +#define E_SUCCESS 0 +#define NULL 0 + +#define TRUE 1 +#define FALSE 0 + +#define ENABLE 1 +#define DISABLE 0 + +// Define one bit mask +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#endif + diff --git a/bsp/nuc140/CMSIS/CM0/core_cm0.c b/bsp/nuc140/CMSIS/CM0/core_cm0.c new file mode 100644 index 0000000000000000000000000000000000000000..047a5d788551d7730a77f7000ee48af4ecd51bdc --- /dev/null +++ b/bsp/nuc140/CMSIS/CM0/core_cm0.c @@ -0,0 +1,470 @@ +/****************************************************************************** + * @file: core_cm0.c + * @purpose: CMSIS Cortex-M0 Core Peripheral Access Layer Source File + * @version: V1.10 + * @date: 24. Feb. 2009 + *---------------------------------------------------------------------------- + * + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * ARM Limited (ARM) is supplying this software for use with Cortex-Mx + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + + +#include + + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for armcc */ + #define __INLINE __inline /*!< inline keyword for armcc */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for iarcc */ + #define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */ + #define __nop __no_operation /*!< no operation intrinsic in iarcc */ + +#elif defined ( __GNUC__ ) + #define __ASM asm /*!< asm keyword for gcc */ + #define __INLINE inline /*!< inline keyword for gcc */ +#endif + + + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ + +/** + * @brief Return the Process Stack Pointer + * + * @param none + * @return uint32_t ProcessStackPointer + * + * Return the actual process stack pointer + */ +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} + +/** + * @brief Set the Process Stack Pointer + * + * @param uint32_t Process Stack Pointer + * @return none + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} + +/** + * @brief Return the Main Stack Pointer + * + * @param none + * @return uint32_t Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} + +/** + * @brief Set the Main Stack Pointer + * + * @param uint32_t Main Stack Pointer + * @return none + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param uint16_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in unsigned short value + */ +__ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param int16_t value to reverse + * @return int32_t reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +__ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__ARMCC_VERSION < 400000) + + +/** + * @brief Return the Priority Mask value + * + * @param none + * @return uint32_t PriMask + * + * Return the state of the priority mask bit from the priority mask + * register + */ +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} + +/** + * @brief Set the Priority Mask value + * + * @param uint32_t PriMask + * @return none + * + * Set the priority mask bit in the priority mask register + */ +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} + + +/** + * @brief Return the Control Register value + * + * @param none + * @return uint32_t Control value + * + * Return the content of the control register + */ +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} + +/** + * @brief Set the Control Register value + * + * @param uint32_t Control value + * @return none + * + * Set the control register + */ +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} + +#endif /* __ARMCC_VERSION */ + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +#pragma diag_suppress=Pe940 + +/** + * @brief Return the Process Stack Pointer + * + * @param none + * @return uint32_t ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param uint32_t Process Stack Pointer + * @return none + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Return the Main Stack Pointer + * + * @param none + * @return uint32_t Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); + __ASM("bx lr"); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param uint32_t Main Stack Pointer + * @return none + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); + __ASM("bx lr"); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param uint16_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + __ASM("rev16 r0, r0"); + __ASM("bx lr"); +} + + +#pragma diag_default=Pe940 + + + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ + +/** + * @brief Return the Process Stack Pointer + * + * @param none + * @return uint32_t ProcessStackPointer + * + * Return the actual process stack pointer + */ +uint32_t __get_PSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param uint32_t Process Stack Pointer + * @return none + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @param none + * @return uint32_t Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +uint32_t __get_MSP(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param uint32_t Main Stack Pointer + * @return none + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) ); +} + + +/** + * @brief Return the Priority Mask value + * + * @param none + * @return uint32_t PriMask + * + * Return the state of the priority mask bit from the priority mask + * register + */ +uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Priority Mask value + * + * @param uint32_t PriMask + * @return none + * + * Set the priority mask bit in the priority mask register + */ +void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +/** + * @brief Reverse byte order in integer value + * + * @param uint32_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in integer value + */ +uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in unsigned short value + * + * @param uint16_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in unsigned short value + */ +uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param int32_t value to reverse + * @return int32_t reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** + * @brief Return the Control Register value + * + * @param none + * @return uint32_t Control value + * + * Return the content of the control register + */ +uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param uint32_t Control value + * @return none + * + * Set the control register + */ +void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + +#endif + + + + + + + + + + + + + + + + + diff --git a/bsp/nuc140/CMSIS/CM0/core_cm0.h b/bsp/nuc140/CMSIS/CM0/core_cm0.h new file mode 100644 index 0000000000000000000000000000000000000000..34e4a6097c6034c22e43dba3a41f089037cc53e6 --- /dev/null +++ b/bsp/nuc140/CMSIS/CM0/core_cm0.h @@ -0,0 +1,801 @@ +/****************************************************************************** + * @file: core_cm0.h + * @purpose: CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version: V1.10 + * @date: 24. Feb. 2009 + *---------------------------------------------------------------------------- + * + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * ARM Limited (ARM) is supplying this software for use with Cortex-Mx + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + + + +#ifndef __CM0_CORE_H__ +#define __CM0_CORE_H__ + + +#define __CM0_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex core */ + + + +#include /* Include standard types */ + +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 /*!< standard definition for NVIC Priority Bits */ +#endif + + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#define __I volatile const /*!< defines 'read only' permissions */ +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ + + +/* System Reset */ +#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */ +#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */ +#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */ +#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */ + + + + +/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Interrupt Priority Register */ +} NVIC_Type; + + +/* memory mapping struct for System Control Block */ +typedef struct +{ + __I uint32_t CPUID; /*!< CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Interrupt Control State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< System Control Register */ + __IO uint32_t CCR; /*!< Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< System Handler Control and State Register */ + uint32_t RESERVED2[2]; + __IO uint32_t DFSR; /*!< Debug Fault Status Register */ +} SCB_Type; + + +/* memory mapping struct for SysTick */ +typedef struct +{ + __IO uint32_t CTRL; /*!< SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< SysTick Current Value Register */ + __I uint32_t CALIB; /*!< SysTick Calibration Register */ +} SysTick_Type; + + + +/* Core Debug Register */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + #define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ + +#elif defined ( __GNUC__ ) + #define __ASM asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#endif + + +/* ################### Compiler specific Intrinsics ########################### */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#define __enable_fault_irq __enable_fiq +#define __disable_fault_irq __disable_fiq + +#define __NOP __nop +#define __WFI __wfi +#define __WFE __wfe +#define __SEV __sev +#define __ISB() __isb(0) +#define __DSB() __dsb(0) +#define __DMB() __dmb(0) +#define __REV __rev + + + /* intrinsic void __enable_irq(); */ + /* intrinsic void __disable_irq(); */ + + +/** + * @brief Return the Process Stack Pointer + * + * @param none + * @return uint32_t ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param uint32_t Process Stack Pointer + * @return none + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @param none + * @return uint32_t Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param uint32_t Main Stack Pointer + * @return none + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param uint16_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/* + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param int16_t value to reverse + * @return int32_t reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + + +#if (__ARMCC_VERSION < 400000) + +/** + * @brief Return the Priority Mask value + * + * @param none + * @return uint32_t PriMask + * + * Return the state of the priority mask bit from the priority mask + * register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param uint32_t PriMask + * @return none + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Control Register value + * + * @param none + * @return uint32_t Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param uint32_t Control value + * @return none + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +#else /* (__ARMCC_VERSION >= 400000) */ + + +/** + * @brief Return the Priority Mask value + * + * @param none + * @return uint32_t PriMask + * + * Return the state of the priority mask bit from the priority mask + * register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + +/** + * @brief Set the Priority Mask value + * + * @param uint32_t PriMask + * @return none + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + +/** + * @brief Return the Control Register value + * + * @param none + * @return uint32_t Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + +/** + * @brief Set the Control Register value + * + * @param uint32_t Control value + * @return none + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + +#endif /* __ARMCC_VERSION */ + + + +#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ +#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ + +static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } + +static __INLINE void __WFI() { __ASM ("wfi"); } +static __INLINE void __WFE() { __ASM ("wfe"); } +static __INLINE void __SEV() { __ASM ("sev"); } + +//static __INLINE void __ISB(arg) { __ASM ("isb"); } +//static __INLINE void __DSB(arg) { __ASM ("dsb"); } +//static __INLINE void __DMB(arg) { __ASM ("dmb"); } + +/** + * @brief Return the Process Stack Pointer + * + * @param none + * @return uint32_t ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param uint32_t Process Stack Pointer + * @return none + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @param none + * @return uint32_t Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param uint32_t Main Stack Pointer + * @return none + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param uint16_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + + + +/* intrinsic void __set_PRIMASK(); */ +/* intrinsic void __get_PRIMASK(); */ +/* intrinsic uint32_t __REV(uint32_t value); */ +/* intrinsic uint32_t __REVSH(uint32_t value); */ + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +static __INLINE void __NOP() { __ASM volatile ("nop"); } +static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } +static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } + +static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } +static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } + +static __INLINE void __WFI() { __ASM volatile ("wfi"); } +static __INLINE void __WFE() { __ASM volatile ("wfe"); } +static __INLINE void __SEV() { __ASM volatile ("sev"); } +static __INLINE void __ISB(arg) { __ASM volatile ("isb"); } +static __INLINE void __DSB(arg) { __ASM volatile ("dsb"); } +static __INLINE void __DMB(arg) { __ASM volatile ("dmb"); } + + +/** + * @brief Return the Process Stack Pointer + * + * @param none + * @return uint32_t ProcessStackPointer + * + * Return the actual process stack pointer + */ +extern uint32_t __get_PSP(void); + +/** + * @brief Set the Process Stack Pointer + * + * @param uint32_t Process Stack Pointer + * @return none + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +extern void __set_PSP(uint32_t topOfProcStack); + +/** + * @brief Return the Main Stack Pointer + * + * @param none + * @return uint32_t Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +extern uint32_t __get_MSP(void); + +/** + * @brief Set the Main Stack Pointer + * + * @param uint32_t Main Stack Pointer + * @return none + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +extern void __set_MSP(uint32_t topOfMainStack); + +/** + * @brief Return the Priority Mask value + * + * @param none + * @return uint32_t PriMask + * + * Return the state of the priority mask bit from the priority mask + * register + */ +extern uint32_t __get_PRIMASK(void); + +/** + * @brief Set the Priority Mask value + * + * @param uint32_t PriMask + * @return none + * + * Set the priority mask bit in the priority mask register + */ +extern void __set_PRIMASK(uint32_t priMask); + +/** + * @brief Return the Control Register value + * + * @param none + * @return uint32_t Control value + * + * Return the content of the control register + */ +extern uint32_t __get_CONTROL(void); + +/** + * @brief Set the Control Register value + * + * @param uint32_t Control value + * @return none + * + * Set the control register + */ +extern void __set_CONTROL(uint32_t control); + +/** + * @brief Reverse byte order in integer value + * + * @param uint32_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in integer value + */ +extern uint32_t __REV(uint32_t value); + +/** + * @brief Reverse byte order in unsigned short value + * + * @param uint16_t value to reverse + * @return uint32_t reversed value + * + * Reverse byte order in unsigned short value + */ +extern uint32_t __REV16(uint16_t value); + +/* + * Reverse byte order in signed short value with sign extension to integer + * + * @param int16_t value to reverse + * @return int32_t reversed value + * + * @brief Reverse byte order in signed short value with sign extension to integer + */ +extern int32_t __REVSH(int16_t value); + + +#endif + + + +/* ########################## NVIC functions #################################### */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ + +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param uint32_t priority_grouping is priority grouping field + * @return + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t priority_grouping) +{ + uint32_t reg_value=0; + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */ + reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (priority_grouping << 8))); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn_Type IRQn specifies the interrupt number + * @return none + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn_Type IRQn is the positive number of the external interrupt + * @return none + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn_Type IRQn is the number of the device specifc interrupt + * @return IRQn_Type Number of pending interrupt or zero + * + * Read the pending register in NVIC and return the number of the + * specified interrupt if its status is pending, otherwise it returns + * zero. The interrupt number cannot be a negative value. + */ +static __INLINE IRQn_Type NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((IRQn_Type) (NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))); /* Return Interrupt bit or 'zero' */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn_Type IRQn is the Number of the interrupt + * @return none + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn_Type IRQn is the Number of the interrupt + * @return none + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn_Type IRQn is the Number of the interrupt + * @param priority is the priority for the interrupt + * @return none + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. \n + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, int32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn_Type IRQn is the Number of the interrupt + * @return priority is the priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)((NVIC->IP[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/* SysTick constants */ +#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */ +#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */ +#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */ +#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */ + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param uint32_t ticks is the number of ticks between two interrupts + * @return none + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = (0x00); /* Load the SysTick Counter Value */ + SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<AIRCR = (NVIC_AIRCR_VECTKEY | (1< Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + ; maximum of 32 External Interrupts are possible + DCD BOD_IRQHandler + DCD WDT_IRQHandler + DCD EINT0_IRQHandler + DCD EINT1_IRQHandler + DCD GPAB_IRQHandler + DCD GPCDE_IRQHandler + DCD PWMA_IRQHandler + DCD PWMB_IRQHandler + DCD TMR0_IRQHandler + DCD TMR1_IRQHandler + DCD TMR2_IRQHandler + DCD TMR3_IRQHandler + DCD UART0_IRQHandler + DCD UART1_IRQHandler + DCD SPI0_IRQHandler + DCD SPI1_IRQHandler + DCD SPI2_IRQHandler + DCD SPI3_IRQHandler + DCD I2C0_IRQHandler + DCD I2C1_IRQHandler + DCD CAN0_IRQHandler + DCD CAN1_IRQHandler + DCD Default_Handler + DCD USBD_IRQHandler + DCD PS2_IRQHandler + DCD ACMP_IRQHandler + DCD PDMA_IRQHandler + DCD Default_Handler + DCD PWRWU_IRQHandler + DCD ADC_IRQHandler + DCD Default_Handler + DCD RTC_IRQHandler + + + + + + + + AREA |.text|, CODE, READONLY + + + +; Reset Handler + + ENTRY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT BOD_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT EINT0_IRQHandler [WEAK] + EXPORT EINT1_IRQHandler [WEAK] + EXPORT GPAB_IRQHandler [WEAK] + EXPORT GPCDE_IRQHandler [WEAK] + EXPORT PWMA_IRQHandler [WEAK] + EXPORT PWMB_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT CAN1_IRQHandler [WEAK] + EXPORT USBD_IRQHandler [WEAK] + EXPORT PS2_IRQHandler [WEAK] + EXPORT ACMP_IRQHandler [WEAK] + EXPORT PDMA_IRQHandler [WEAK] + EXPORT PWRWU_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + +BOD_IRQHandler +WDT_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +GPAB_IRQHandler +GPCDE_IRQHandler +PWMA_IRQHandler +PWMB_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +CAN0_IRQHandler +CAN1_IRQHandler +USBD_IRQHandler +PS2_IRQHandler +ACMP_IRQHandler +PDMA_IRQHandler +PWRWU_IRQHandler +ADC_IRQHandler +RTC_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/bsp/nuc140/CMSIS/CM0/system_NUC1xx.c b/bsp/nuc140/CMSIS/CM0/system_NUC1xx.c new file mode 100644 index 0000000000000000000000000000000000000000..ae90b986cf8ec7fc504cbba3b6731daff691ae0d --- /dev/null +++ b/bsp/nuc140/CMSIS/CM0/system_NUC1xx.c @@ -0,0 +1,37 @@ +/*---------------------------------------------------------------------------------------------------------*/ +/* */ +/* Copyright(c) 2009 Nuvoton Technology Corp. All rights reserved. */ +/* */ +/*---------------------------------------------------------------------------------------------------------*/ +#include +#include "NUC1xx.h" + +/*---------------------------------------------------------------------------- + Define SYSCLK + *----------------------------------------------------------------------------*/ +#define __HSI (50000000UL) + +/*---------------------------------------------------------------------------- + Clock Definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemFrequency = __HSI; /*!< System Clock Frequency (Core Clock) */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Function: SystemInit */ +/* */ +/* Parameters: */ +/* None */ +/* */ +/* Returns: */ +/* None */ +/* */ +/* Description: */ +/* The necessary initializaiton of systerm. */ +/* */ +/*---------------------------------------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +} + diff --git a/bsp/nuc140/CMSIS/CM0/system_NUC1xx.h b/bsp/nuc140/CMSIS/CM0/system_NUC1xx.h new file mode 100644 index 0000000000000000000000000000000000000000..24064881df862f351937343869a1a2568db99b20 --- /dev/null +++ b/bsp/nuc140/CMSIS/CM0/system_NUC1xx.h @@ -0,0 +1,39 @@ +/****************************************************************************** + * @file: system_armikmcu.h + * @purpose: CMSIS ARM Cortex-M0 Device Peripheral Access Layer Header File + * @version: V0.01 + * @date: 17. Feb. 2009 + *---------------------------------------------------------------------------- + * + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * ARM Limited (ARM) is supplying this software for use with Cortex-Mx + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __SYSTEM_ARMCM0_H +#define __SYSTEM_ARMCM0_H + +extern uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system + * Initialise GPIO directions and values + */ +extern void SystemInit (void); +#endif diff --git a/bsp/nuc140/CMSIS/Documentation/CMSIS_Core.htm b/bsp/nuc140/CMSIS/Documentation/CMSIS_Core.htm new file mode 100644 index 0000000000000000000000000000000000000000..9993573adcde3191ab18aacae4f1c0a5ddf9ea55 --- /dev/null +++ b/bsp/nuc140/CMSIS/Documentation/CMSIS_Core.htm @@ -0,0 +1,1204 @@ + + + + CMSIS: Cortex Microcontroller Software Interface Standard + + + +

Cortex Microcontroller Software Interface Standard

+ +

This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).

+

Version: 1.10 - 24. Feb. 2009

+ +

Information in this file, the accompany manuals, and software is
+ Copyright © ARM Ltd.
All rights reserved. +

+ +
+ +

Revision History

+
    +
  • Version 1.00: initial release.
    • +
  • Version 1.01: added __LDREXx, __STREXx, and __CLREX.
    • +
  • Version 1.02: added Cortex-M0.
    • +
  • Version 1.10: second review.
    • +
+ +
+ +

Contents

+ +
    +
  1. About
    2. +
  2. Coding Rules and Conventions
    3. +
  3. CMSIS Files
    4. +
  4. Core Peripheral Access Layer
    5. +
  5. CMSIS Example
    6. +
+ +

About

+ +

+ The Cortex Microcontroller Software Interface Standard (CMSIS) answers the challenges + that are faced when software components are deployed to physical microcontroller devices based on a + Cortex-M0 / Cortex-M1 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M + processor cores (the term Cortex-Mx is used to indicate that). The CMSIS is defined in close co-operation + with various silicon and software vendors and provides a common approach to interface to peripherals, + real-time operating systems, and middleware components. +

+ +

ARM provides as part of the CMSIS the following software layers that are +available for various compiler implementations:

+
    +
  • Core Peripheral Access Layer: contains name definitions, + address definitions and helper functions to + access core registers and peripherals. It defines also an device + independent interface for RTOS Kernels that includes debug channel + definitions.
    • +
  • Middleware Access Layer: provides common methods to + access peripherals for the software industry. The Middleware Access Layer + is adapted by the Silicon Vendor for the device specific peripherals used + by middleware components. The middleware access layer is currently in + development and not yet part of this documentation
    • +
+ +

These software layers are expanded by Silicon partners with:

+
    +
  • Device Peripheral Access Layer: provides definitions + for all device peripherals
    • +
  • Access Functions for Peripherals (optional): provides + additional helper functions for peripherals
    • +
+ +

CMSIS defines for a Cortex-Mx Microcontroller System:

+
    +
  • A common way to access peripheral registers + and a common way to define exception vectors.
    • +
  • The register names of the Core + Peripherals and the names of the Core + Exception Vectors.
    • +
  • An device independent interface for RTOS Kernels including a debug + channel.
    • +
  • Interfaces for middleware components (TCP/IP + Stack, Flash File System).
    • +
+ +

+ By using CMSIS compliant software components, the user can easier re-use template code. + CMSIS is intended to enable the combination of software components from multiple middleware vendors. +

+ +

Coding Rules and Conventions

+ +

+ The following section describes the coding rules and conventions used in the CMSIS + implementation. It contains also information about data types and version number information. +

+ +

Essentials

+
    +
  • The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations, + there are disable and enable sequences for PC-LINT inserted.
    • +
  • ANSI standard data types defined in the ANSI C header file + <stdint.h> are used.
    • +
  • #define constants that include expressions must be enclosed by + parenthesis.
    • +
  • Variables and parameters have a complete data type.
    • +
  • All functions in the Core Peripheral Access Layer are + re-entrant.
    • +
  • The Core Peripheral Access Layer has no blocking code + (which means that wait/query loops are done at other software layers such as + the Middleware Access Layer).
    • +
  • For each exception/interrupt there is definition for: +
      +
    • an exception/interrupt handler with the postfix _Handler + (for exceptions) or _IRQHandler (for interrupts).
      • +
    • a default exception/interrupt handler (weak definition) that contains an endless loop.
      • +
    • a #define of the interrupt number with the postfix _IRQn.
      • +
    • +
+ +

Recommendations

+ +

The CMSIS recommends the following conventions for identifiers.

+
    +
  • CAPITAL names to identify Core Registers, Peripheral Registers, and CPU Instructions.
    • +
  • CamelCase names to identify peripherals access functions and interrupts.
    • +
  • PERIPHERAL_ prefix to identify functions that belong to specify peripherals.
    • +
  • Doxygen comments for all functions are included as described under Function Comments below.
    • +
+ +Comments + +
    +
  • Comments use the ANSI C90 style (/* comment */) or C++ style + (// comment). It is assumed that the programming tools support today + consistently the C++ comment style.
    • +
  • Function Comments provide for each function the following information: +
      +
    • one-line brief function overview.
      • +
    • detailed parameter explanation.
      • +
    • detailed information about return values.
      • +
    • detailed description of the actual function.
      • +
    +

    Doxygen Example:

    + 
    +/** 
+ * @brief  Enable Interrupt in NVIC Interrupt Controller
+ * @param  IRQn  interrupt number that specifies the interrupt
+ * @return none.
+ * Enable the specified interrupt in the NVIC Interrupt Controller.
+ * Other settings of the interrupt such as priority are not affected.
+ */
    +
    • +
+ +

Data Types and IO Type Qualifiers

+ +

+ The Cortex-Mx HAL uses the standard types from the standard ANSI C header file + <stdint.h>. IO Type Qualifiers are used to specify the access + to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of + debug information of peripheral registers. +

+ + + + + + + + + + + + + + + + + + + + + + + + +
IO Type Qualifier#defineDescription
__Ivolatile constRead access only
__OvolatileWrite access only
__IOvolatileRead and write access
+ +

CMSIS Version Number

+

+ File core_cm3.h contains the version number of the CMSIS with the following define: +

+ +
+#define __CM3_CMSIS_VERSION_MAIN  (0x00)      /* [31:16] main version       */
+#define __CM3_CMSIS_VERSION_SUB   (0x03)      /* [15:0]  sub version        */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)
+ +

+ File core_cm0.h contains the version number of the CMSIS with the following define: +

+ +
+#define __CM0_CMSIS_VERSION_MAIN  (0x00)      /* [31:16] main version       */
+#define __CM0_CMSIS_VERSION_SUB   (0x00)      /* [15:0]  sub version        */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)
+ + +

CMSIS Cortex Core

+

+ File core_cm3.h contains the type of the CMSIS Cortex-Mx with the following define: +

+ +
+#define __CORTEX_M                (0x03)
+ +

+ File core_cm0.h contains the type of the CMSIS Cortex-Mx with the following define: +

+ +
+#define __CORTEX_M                (0x00)
+ + +

CMSIS Files

+

+ This section describes the Files provided in context with the CMSIS to access the Cortex-Mx + hardware and peripherals. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FileProviderDescription
device.hDevice specific (provided by silicon partner)Defines the peripherals for the actual device. The file may use + several other include files to define the peripherals of the actual device.
core_cm0.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the core peripherals for the Cortex-M0 CPU and core peripherals.
core_cm3.hARM (for RealView ARMCC, IAR, and GNU GCC)Defines the core peripherals for the Cortex-M3 CPU and core peripherals.
core_cm0.cARM (for RealView ARMCC, IAR, and GNU GCC)Provides helper functions that access core registers.
core_cm0.cARM (for RealView ARMCC, IAR, and GNU GCC)Provides helper functions that access core registers.
startup_deviceARM (adapted by compiler partner / silicon partner)Provides the Cortex-Mx startup code and the complete (device specific) Interrupt Vector Table
system_deviceARM (adapted by silicon partner)Provides a device specific configuration file for the device. It configures the device initializes + typically the oscillator (PLL) that is part of the microcontroller device
+ +

device.h

+ +

+ The file device.h is provided by the silicon vendor and is the + central include file that the application programmer is using in + the C source code. This file contains: +

+
    +
  • +

    Interrupt Number Definition: provides interrupt numbers + (IRQn) for all core and device specific exceptions and interrupts.

    +
    • +
  • +

    Configuration for core_cm0.h / core_cm3.h: reflects the + actual configuration of the Cortex-Mx processor that is part of the actual + device. As such the file core_cm0.h / core_cm3.h is included that + implements access to processor registers and core peripherals.

    +
    • +
  • +

    Device Peripheral Access Layer: provides definitions + for all device peripherals. It contains all data structures and the address + mapping for the device specific peripherals.

    +
    • +
  • Access Functions for Peripherals (optional): provides + additional helper functions for peripherals that are useful for programming + of these peripherals. Access Functions may be provided as inline functions + or can be extern references to a device specific library provided by the + silicon vendor.
    • +
+ + +

Interrupt Number Definition

+ +

To access the device specific interrupts the device.h file defines IRQn +numbers for the complete device using a enum typedef as shown below:

+
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
+  NonMaskableInt_IRQn             = -14,      /*!< 2 Non Maskable Interrupt                              */
+  MemoryManagement_IRQn           = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt               */
+  BusFault_IRQn                   = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                       */
+  UsageFault_IRQn                 = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                     */
+  SVCall_IRQn                     = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                        */
+  DebugMonitor_IRQn               = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt                  */
+  PendSV_IRQn                     = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                        */
+  SysTick_IRQn                    = -1,       /*!< 15 Cortex-M3 System Tick Interrupt                    */
+/******  STM32 specific Interrupt Numbers ****************************************************************/
+  WWDG_STM_IRQn                   = 0,        /*!< Window WatchDog Interrupt                             */
+  PVD_STM_IRQn                    = 1,        /*!< PVD through EXTI Line detection Interrupt             */
+  :
+  :
+  } IRQn_Type;
+ + +

Configuration for core_cm0.h / core_cm3.h

+

+ The Cortex-Mx core configuration options which are defined for each device implementation. Some + configuration options are reflected in the CMSIS layer using the #define settings described below. +

+

+ To access core peripherals file device.h includes file core_cm0.h / core_cm3.h. + Several features in core_cm0.h / core_cm3.h are configured by the following defines that must be + defined before #include <core_cm0.h> / #include <core_cm3.h> + preprocessor command. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#defineFileValueDescription
__NVIC_PRIO_BITScore_cm0.h(2)Number of priority bits implemented in the NVIC (device specific)
__NVIC_PRIO_BITScore_cm3.h(2 ... 8)Number of priority bits implemented in the NVIC (device specific)
__MPU_PRESENTcore_cm0.h, core_cm3.h(0, 1)Defines if an MPU is present or not
__Vendor_SysTickConfigcore_cm0.h, core_cm3.h(1)When this define is setup to 1, the SysTickConfig function + in core_cm3.h is excluded. In this case the device.h + file must contain a vendor specific implementation of this function.
+ + +

Device Peripheral Access Layer

+

+ Each peripheral uses a PERIPHERAL_ prefix to identify peripheral registers + and functions that access this specific peripheral. If more than one peripheral of the same + type exists, identifiers have a postfix (digit or letter). For example: +

+
    +
  • UART_Type: defines the generic register layout for all UART channels in a device.
    • +
  • UART1: is a pointer to a register structure that refers to a specific UART. + For example UART1->DR is the data register of UART1.
    • +
  • UART_SendChar(UART1, c): is a generic function that works with all UART's in the device. + To communicate the UART that it accesses the first parameter is a pointer to the actual + UART register structure.
    • +
  • UART1_SendChar(c): is an UART1 specific implementation (in this case the send function).
    • +
+ +
Minimal Requiements
+

+ To access the peripheral registers and related function in a device the files device.h + and core_cm0.h / core_cm3.h defines as a minimum: +

+
    +
  • The Register Layout Typedef for each peripheral that defines all register names. + Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of + the peripheral registers. For example: + 
    +typedef struct {
+  __IO uint32_t CTRL;      /* SysTick Control and Status Register */
+  __IO uint32_t LOAD;      /* SysTick Reload Value Register       */
+  __IO uint32_t VAL;       /* SysTick Current Value Register      */
+  __I  uint32_t CALIB;     /* SysTick Calibration Register        */
+  } SysTick_Type;
    +
    • + +
  • Base Address for each peripheral (in case of multiple peripherals + that use the same register layout typedef multiple base addresses are defined). For example: + 
    +#define SysTick_BASE (SCS_BASE + 0x0010)            /* SysTick Base Address */
    +
    • + +
  • Access Definition for each peripheral (in case of multiple peripherals that use + the same register layout typedef multiple access definitions exist, i.e. UART0, + UART1). For Example: + 
    +#define SysTick ((SysTick_Type *) SysTick_BASE)     /* SysTick access definition */
    +
    • +
+ +

+ These definitions allow to access the peripheral registers from user code with simple assignments like: +

+
SysTick->CTRL = 0;
+ +
Optional Features
+

In addition the device.h file may define:

+
    +
  • #define constants that simplify access to the peripheral registers. + These constant define bit-positions or other specific patterns are that + required for the programming of the peripheral registers. The identifiers + used start with the name of the PERIPERHAL_. It is + recommended to use CAPITAL letters for such #define constants.
    • +
  • Functions that perform more complex functions with the peripheral (i.e. + status query before a sending register is accessed). Again these function + start with the name of the PERIPHERAL_.
    • +
+ +

core_cm0.h and core_cm0.c

+

+ File core_cm0.h describes the data structures for the Cortex-M0 core peripherals and does + the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers + and core peripherals with efficient functions (defined as static inline). +

+

+ File core_cm0.c defines several helper functions that access processor registers. +

+

Together these files implement the Core Peripheral Access Layer for a Cortex-M0.

+ +

core_cm3.h and core_cm3.c

+

+ File core_cm3.h describes the data structures for the Cortex-M3 core peripherals and does + the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers + and core peripherals with efficient functions (defined as static inline). +

+

+ File core_cm3.c defines several helper functions that access processor registers. +

+

Together these files implement the Core Peripheral Access Layer for a Cortex-M3.

+ +

startup_device

+

+ A template file for startup_device is provided by ARM for each supported + compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific + interrupt handlers. Each interrupt handler is defined as weak function + to an dummy handler. Therefore the interrupt handler can be directly used in application software + without any requirements to adapt the startup_device file. +

+

+ The following exception names are fixed and define the start of the vector table for a Cortex-M0: +

+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+ +

+ The following exception names are fixed and define the start of the vector table for a Cortex-M3: +

+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+ +

+ In the following examples for device specific interrupts are shown: +

+
+; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window Watchdog
+                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+                DCD     TAMPER_IRQHandler         ; Tamper
+ +

+ Device specific interrupts must have a dummy function that can be overwritten in user code. + Below is an example for this dummy function. +

+
+Default_Handler PROC
+                EXPORT WWDG_IRQHandler   [WEAK]
+                EXPORT PVD_IRQHandler    [WEAK]
+                EXPORT TAMPER_IRQHandler [WEAK]
+                :
+                :
+                WWDG_IRQHandler
+                PVD_IRQHandler
+                TAMPER_IRQHandler
+                :
+                :
+                B .
+                ENDP
+ +

+ The user application may simply define an interrupt handler function by using the handler name + as shown below. +

+
+void WWDG_IRQHandler(void)
+{
+  :
+  :
+}
+ + +

system_device.c

+

+ A template file for system_device.c is provided by ARM but adapted by + the silicon vendor to match their actual device. As a minimum requirement + this file must provide a device specific system configuration function and a global variable + that contains the system frequency. It configures the device and initializes typically the + oscillator (PLL) that is part of the microcontroller device. +

+

+ The file system_device.c must provide + as a minimum requirement the SystemInit function as shown below. +

+ + + + + + + + + + + + +
Function DefinitionDescription
void SystemInit (void)Setup the microcontroller system. Typically this function configures the + oscillator (PLL) that is part of the microcontroller device. For systems + with variable clock speed it also updates the variable SystemFrequency.
+ +

+ Also part of the file system_device.c + is the variable SystemFrequency which contains the current CPU clock speed shown below. +

+ + + + + + + + + + + + +
Variable DefinitionDescription
uint32_t SystemFrequencyContains the system frequency (which is the system clock frequency supplied + to the SysTick timer and the processor core clock). This variable can be + used by the user application after the call to the function SystemInit() + to setup the SysTick timer or configure other parameters. It may also be + used by debugger to query the frequency of the debug timer or configure + the trace clock speed.

+ This variable may also be defined in the const space. + The compiler must be configured to avoid the removal of this variable in + case that the application program is not using it. It is important for + debug systems that the variable is physically present in memory so that + it can be examined to configure the debugger.
+ +

Note

+
    +

  • The above definitions are the minimum requirements for the file + system_device.c. This + file may export more functions or variables that provide a more flexible + configuration of the microcontroller system.

    +
    • +
+ + +

Core Peripheral Access Layer

+ +

Cortex-Mx Core Register Access

+

+ The following functions are defined in core_cm0.h / core_cm3.h + and provide access to Cortex-Mx core registers. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Function DefinitionCoreCore RegisterDescription
void __enable_irq (void)M0, M3PRIMASK = 0Global Interrupt enable (using the instruction CPSIE + i)
void __disable_irq (void)M0, M3PRIMASK = 1Global Interrupt disable (using the instruction + CPSID i)
void __set_PRIMASK (uint32_t value)M0, M3PRIMASK = valueAssign value to Priority Mask Register (using the instruction + MSR)
uint32_t __get_PRIMASK (void)M0, M3return PRIMASKReturn Priority Mask Register (using the instruction + MRS)
void __enable_fault_irq (void)M3FAULTMASK = 0Global Fault exception and Interrupt enable (using the + instruction CPSIE + f)
void __disable_fault_irq (void)M3FAULTMASK = 1Global Fault exception and Interrupt disable (using the + instruction CPSID f)
void __set_FAULTMASK (uint32_t value)M3FAULTMASK = valueAssign value to Fault Mask Register (using the instruction + MSR)
uint32_t __get_FAULTMASK (void)M3return FAULTMASKReturn Fault Mask Register (using the instruction MRS)
void __set_BASEPRI (uint32_t value)M3BASEPRI = valueSet Base Priority (using the instruction MSR)
uiuint32_t __get_BASEPRI (void)M3return BASEPRIReturn Base Priority (using the instruction MRS)
void __set_CONTROL (uint32_t value)M0, M3CONTROL = valueSet CONTROL register value (using the instruction MSR)
uint32_t __get_CONTROL (void)M0, M3return CONTROLReturn Control Register Value (using the instruction + MRS)
void __set_PSP (uint32_t TopOfProcStack)M0, M3PSP = TopOfProcStackSet Process Stack Pointer value (using the instruction + MSR)
uint32_t __get_PSP (void)M0, M3return PSPReturn Process Stack Pointer (using the instruction MRS)
void __set_MSP (uint32_t TopOfMainStack)M0, M3MSP = TopOfMainStackSet Main Stack Pointer (using the instruction MSR)
uint32_t __get_MSP (void)M0, M3return MSPReturn Main Stack Pointer (using the instruction MRS)
+ +

Cortex-Mx Instruction Access

+

+ The following functions are defined in core_cm0.h / core_cm3.hand + generate specific Cortex-Mx instructions. The functions are implemented in the file + core_cm0.c / core_cm3.c. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameCoreGenerated CPU InstructionDescription
void __WFI (void)M0, M3WFIWait for Interrupt
void __WFE (void)M0, M3WFEWait for Event
void __SEV (void)M0, M3SEVSet Event
void __ISB (void)M0, M3ISBInstruction Synchronization Barrier
void __DSB (void)M0, M3DSBData Synchronization Barrier
void __DMB (void)M0, M3DMBData Memory Barrier
uint32_t __REV (uint32_t value)M0, M3REVReverse byte order in integer value.
uint32_t __REV16 (uint16_t value)M0, M3REV16Reverse byte order in unsigned short value.
sint32_t __REVSH (sint16_t value)M0, M3REVSHReverse byte order in signed short value with sign extension to integer.
uint32_t __RBIT (uint32_t value)M3RBITReverse bit order of value
uint8_t __LDREXB (uint8_t *addr)M3LDREXBLoad exclusive byte
uint16_t __LDREXH (uint16_t *addr)M3LDREXHLoad exclusive half-word
uint32_t __LDREXW (uint32_t *addr)M3LDREXWLoad exclusive word
uint32_t __STREXB (uint8_t value, uint8_t *addr)M3STREXBStore exclusive byte
uint32_t __STREXB (uint16_t value, uint16_t *addr)M3STREXHStore exclusive half-word
uint32_t __STREXB (uint32_t value, uint32_t *addr)M3STREXWStore exclusive word
void __CLREX (void)M3CLREXRemove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW
+ + +

NVIC Access Functions

+

+ The CMSIS provides access to the NVIC via the register interface structure and several helper + functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to + identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative + IRQn values are used for processor core exceptions. +

+

+ For the IRQn values of core exceptions the file device.h provides + the following enum names. +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Core Exception enum ValueCoreIRQnDescription
NonMaskableInt_IRQnM0, M3-14Cortex-Mx Non Maskable Interrupt
MemoryManagement_IRQnM3-12Cortex-Mx Memory Management Interrupt
BusFault_IRQnM3-11Cortex-Mx Bus Fault Interrupt
UsageFault_IRQnM3-10Cortex-Mx Usage Fault Interrupt
SVCall_IRQnM0, M3-5Cortex-Mx SV Call Interrupt
DebugMonitor_IRQnM3-4Cortex-Mx Debug Monitor Interrupt
PendSV_IRQnM0, M3-2Cortex-Mx Pend SV Interrupt
SysTick_IRQnM0, M3-1Cortex-Mx System Tick Interrupt
+ +

The following functions simplify the setup of the NVIC. +The functions are defined as static inline.

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameCoreParameterDescription
void NVIC_SetPriorityGrouping(uint32_t priority_grouping)M0, M3Priority Grouping ValueSet the Priority Grouping (Groups . Subgroups)
void NVIC_EnableIRQ(IRQn_Type IRQn)M0, M3IRQ NumberEnable IRQn
void NVIC_DisableIRQ(IRQn_Type IRQn)M0, M3IRQ NumberDisable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)M0, M3IRQ NumberReturn true (IRQ-Number) if IRQn is pending
void NVIC_SetPendingIRQ (IRQn_Type IRQn)M0, M3IRQ NumberSet IRQn Pending
void NVIC_ClearPendingIRQ (IRQn_Type IRQn)M0, M3IRQ NumberClear IRQn Pending Status
uint32_t NVIC_GetActive (IRQn_Type IRQn)M3IRQ NumberReturn the IRQn of the active interrupt
void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)M0, M3IRQ Number, PrioritySet Priority for IRQn
+ (not threadsafe for Cortex-M0)
uint32_t NVIC_GetPriority (IRQn_Type IRQn)M0, M3IRQ NumberGet Priority for IRQn
void NVIC_SystemReset (void)M0, M3(void)Resets the System
+

Note

+
    +

  • The processor exceptions have negative enum values. Device specific interrupts + have positive enum values and start with 0. The values are defined in + device.h file.

    +
    • +
+ + +

SysTick Configuration Function

+ +

The following function is used to configure the SysTick timer and start the +SysTick interrupt.

+ + + + + + + + + + + + + + +
NameParameterDescription
uint32_t SysTickConfig + (uint32_t ticks)ticks is SysTick counter reload valueSetup the SysTick timer and enable the SysTick interrupt. After this + call the SysTick timer creates interrupts with the specified time + interval.
+
+ Return: 0 when successful, 1 on failure.
+
+ + +

Cortex-M3 ITM Debug Access

+ +

The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that +provides together with the Serial Viewer Output trace capabilities for the +microcontroller system. The ITM has 32 communication channels; two ITM +communication channels are used by CMSIS to output the following information:

+
    +
  • ITM Channel 0: implements the ITM_putchar function + which can be used for printf-style output via the debug interface.
    • +
  • ITM Channel 31: is reserved for the RTOS kernel and can be used for + kernel awareness debugging.
    • +
+

Note

+
    +

  • The ITM channel 31 is selected for the RTOS kernel since some kernels + may use the Privileged level for program execution. ITM + channels have 4 groups with 8 channels each, whereby each group can be + configured for access rights in the Unprivileged level. The ITM channel 0 + may be therefore enabled for the user task whereas ITM channel 31 may be + accessible only in Privileged level from the RTOS kernel itself.

    +
    • +
+ +

The prototype of the ITM_putchar routine is shown in the +table below.

+ + + + + + + + + + + + + + +
NameParameterDescription
void uint32_t ITM_putchar(uint32_t chr)character to outputThe function outputs a character via the ITM channel 0. The + function returns when no debugger is connected that has booked the + output. It is blocking when a debugger is connected, but the + previous character send is not transmitted.

+ Return: the input character 'chr'.
+ + +

+ Example for the usage of the ITM Channel 31 for RTOS Kernels: +

+
+  // check if debugger connected and ITM channel enabled for tracing
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
+  (ITM->TCR & ITM_TCR_ITMENA) &&
+  (ITM->TER & (1UL << 31))) {
+    // transmit trace data
+    while (ITM->PORT31_U32 == 0);
+    ITM->PORT[31].u8 = task_id;      // id of next task
+    while (ITM->PORT[31].u32 == 0);
+    ITM->PORT[31].u32 = task_status; // status information
+  }
+ + +

CMSIS Example

+

+ The following section shows a typical example for using the CMSIS layer in user applications. +

+
+#include <device.h>                              // file name depends on the device used.
+
+void SysTick_Handler (void)  {                   // SysTick Interrupt Handler
+  ;
+}
+
+void TIM1_UP_IRQHandler (void)  {                // Timer Interrupt Handler
+  ;
+}
+
+void timer1_init(int frequency) {
+                                                 // set up Timer (device specific)
+  NVIC_SetPriority (TIM1_UP_IRQn, 1);            // Set Timer priority
+  NVIC_EnableIRQ (TIM1_UP_IRQn);                 // Enable Timer Interrupt
+}
+
+void main (void) {
+  SystemInit ();
+
+  if (SysTick_Config (SystemFrequency / 1000)) { // Setup SysTick Timer for 1 msec interrupts
+    :                                            // Handle Error
+    :
+    while (1);
+  }
+
+  timer1_init ();                                // device specific timer
+
+  while (1);
+}
+ + + \ No newline at end of file diff --git a/bsp/nuc140/application.c b/bsp/nuc140/application.c new file mode 100644 index 0000000000000000000000000000000000000000..4ef7c37b039050d26fff66d28342f8e5ae5e90e6 --- /dev/null +++ b/bsp/nuc140/application.c @@ -0,0 +1,26 @@ +/* + * File : app.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-01-25 Bernard first version + */ + +/** + * @addtogroup LPC1100 + */ +/*@{*/ +#include + +int rt_application_init() +{ + return 0; +} + +/*@}*/ diff --git a/bsp/nuc140/board.c b/bsp/nuc140/board.c new file mode 100644 index 0000000000000000000000000000000000000000..19607e22b8a02ff9d5838b4fc2293bdc9a3801a6 --- /dev/null +++ b/bsp/nuc140/board.c @@ -0,0 +1,65 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-01-25 Bernard first version + */ + +#include +#include + +#include "board.h" +#include "uart.h" + +#include "CMSIS/CM0/NUC1xx.h" +#include "CMSIS/CM0/core_cm0.h" + +/** + * @addtogroup NUC100 + */ +/*@{*/ + +/** + * This is the timer interrupt service routine. + */ +void rt_hw_timer_handler() +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial sam7s64 board. + */ +void rt_hw_board_init() +{ + SystemInit(); + + /* init systick */ + SysTick_Config(SystemFrequency/RT_TICK_PER_SECOND - 1); + + /* set pend exception priority */ + NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1); + +#ifdef RT_USING_UART + /* init hardware UART device */ + rt_hw_uart_init(); +#endif +#ifdef RT_USING_CONSOLE + /* set console device */ + rt_console_set_device("uart1"); +#endif +} +/*@}*/ diff --git a/bsp/nuc140/board.h b/bsp/nuc140/board.h new file mode 100644 index 0000000000000000000000000000000000000000..1cabc8e886c4c9cf52d251e194a32e33235537be --- /dev/null +++ b/bsp/nuc140/board.h @@ -0,0 +1,20 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-01-25 Bernard first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/nuc140/project.uvopt b/bsp/nuc140/project.uvopt new file mode 100644 index 0000000000000000000000000000000000000000..e09c202db1630a07060224bfdbe1993c453a5608 --- /dev/null +++ b/bsp/nuc140/project.uvopt @@ -0,0 +1,2096 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + RT-Thread NUC100 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + + DARMCM1.DLL + + SARMCM3.DLL + + TARMCM1.DLL + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 1 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0) + + + 0 + UL2CM3 + -UV0704M0Z -O78 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC4000 -FN1 -FF0NUC1xx_128 -FS00 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fault_rvds.S + + + 2 + 11 + 2 + 0 + 0 + 0 + 0 + 235 + 240 + 0 + ..\..\libcpu\arm\nuc1xx\start_rvds.S + start_rvds.S + + + + + CMSIS + 0 + 0 + 0 + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\CMSIS\CM0\system_NUC1xx.c + system_NUC1xx.c + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\CMSIS\CM0\core_cm0.c + core_cm0.c + + + + + Kernel + 0 + 0 + 0 + + 4 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\timer.c + timer.c + + + 4 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\clock.c + clock.c + + + 4 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\device.c + device.c + + + 4 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\idle.c + idle.c + + + 4 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\ipc.c + ipc.c + + + 4 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\irq.c + irq.c + + + 4 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\kservice.c + kservice.c + + + 4 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\mem.c + mem.c + + + 4 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 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+++ b/bsp/nuc140/project.uvproj @@ -0,0 +1,609 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + + RT-Thread NUC100 + 0x4 + ARM-ADS + + + Cortex-M0 + ARM + CLOCK(12000000) CPUTYPE("Cortex-M0") + + + + 4803 + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\objs\ + rtthread-nuc140 + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + + SARMCM3.DLL + + TARMCM1.DLL + + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 1 + + + + + + + + + + + + + + BIN\UL2CM3.DLL + + + + + 1 + 0 + 0 + 1 + 1 + 4097 + + BIN\UL2CM3.DLL + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 5 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + .;..\..\include;..\..\finsh + + + + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + + + + --entry Reset_Handler --keep __fsym_* --keep __vsym_* + + + + + + + + Startup + + + board.c + 1 + .\board.c + + + startup.c + 1 + .\startup.c + + + uart.c + 1 + .\uart.c + + + rtconfig.h + 5 + .\rtconfig.h + + + application.c + 1 + .\application.c + + + + + NUC100 + + + fault.c + 1 + ..\..\libcpu\arm\nuc1xx\fault.c + + + interrupt.c + 1 + ..\..\libcpu\arm\nuc1xx\interrupt.c + + + stack.c + 1 + ..\..\libcpu\arm\nuc1xx\stack.c + + + context_rvds.S + 2 + ..\..\libcpu\arm\nuc1xx\context_rvds.S + + + fault_rvds.S + 2 + ..\..\libcpu\arm\nuc1xx\fault_rvds.S + + + start_rvds.S + 2 + ..\..\libcpu\arm\nuc1xx\start_rvds.S + + + + + CMSIS + + + system_NUC1xx.c + 1 + .\CMSIS\CM0\system_NUC1xx.c + + + core_cm0.c + 1 + .\CMSIS\CM0\core_cm0.c + + + + + Kernel + + + timer.c + 1 + ..\..\src\timer.c + + + clock.c + 1 + ..\..\src\clock.c + + + device.c + 1 + ..\..\src\device.c + + + idle.c + 1 + ..\..\src\idle.c + + + ipc.c + 1 + ..\..\src\ipc.c + + + irq.c + 1 + ..\..\src\irq.c + + + kservice.c + 1 + ..\..\src\kservice.c + + + mem.c + 1 + ..\..\src\mem.c + + + mempool.c + 1 + ..\..\src\mempool.c + + + object.c + 1 + ..\..\src\object.c + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + slab.c + 1 + ..\..\src\slab.c + + + thread.c + 1 + ..\..\src\thread.c + + + + + finsh + + + symbol.c + 1 + ..\..\finsh\symbol.c + + + cmd.c + 1 + ..\..\finsh\cmd.c + + + finsh_compiler.c + 1 + ..\..\finsh\finsh_compiler.c + + + finsh_error.c + 1 + ..\..\finsh\finsh_error.c + + + finsh_heap.c + 1 + ..\..\finsh\finsh_heap.c + + + finsh_init.c + 1 + ..\..\finsh\finsh_init.c + + + finsh_node.c + 1 + ..\..\finsh\finsh_node.c + + + finsh_ops.c + 1 + ..\..\finsh\finsh_ops.c + + + finsh_parser.c + 1 + ..\..\finsh\finsh_parser.c + + + finsh_token.c + 1 + ..\..\finsh\finsh_token.c + + + finsh_var.c + 1 + ..\..\finsh\finsh_var.c + + + finsh_vm.c + 1 + ..\..\finsh\finsh_vm.c + + + shell.c + 1 + ..\..\finsh\shell.c + + + + + + + + diff --git a/bsp/nuc140/rtconfig.h b/bsp/nuc140/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..a4b72e235abb7a47c864063dd83173a1e46aa280 --- /dev/null +++ b/bsp/nuc140/rtconfig.h @@ -0,0 +1,74 @@ +/* RT-Thread config file */ +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +/* RT_NAME_MAX*/ +#define RT_NAME_MAX 4 + +/* RT_ALIGN_SIZE*/ +#define RT_ALIGN_SIZE 4 + +/* PRIORITY_MAX*/ +#define RT_THREAD_PRIORITY_MAX 8 + +/* Tick per Second*/ +#define RT_TICK_PER_SECOND 100 + +/* SECTION: RT_DEBUG */ +/* Thread Debug*/ +/* #define RT_THREAD_DEBUG */ + +/* Using Hook*/ +/* #define RT_USING_HOOK */ + +/* SECTION: IPC */ +/* Using Semaphore*/ +#define RT_USING_SEMAPHORE + +/* Using Mutex*/ +/* #define RT_USING_MUTEX */ + +/* Using Event*/ +/* #define RT_USING_EVENT */ + +/* Using MailBox*/ +#define RT_USING_MAILBOX + +/* Using Message Queue*/ +/* #define RT_USING_MESSAGEQUEUE */ + +/* SECTION: Memory Management */ +/* Using Memory Pool Management*/ +/* #define RT_USING_MEMPOOL */ + +/* Using Dynamic Heap Management*/ +#define RT_USING_HEAP + +/* Using Small MM*/ +#define RT_USING_SMALL_MEM +#define RT_USING_TINY_SIZE + +/* SECTION: Device System */ +/* Using Device System */ +#define RT_USING_DEVICE + +/* buffer size for UART reception */ +#define RT_UART_RX_BUFFER_SIZE 64 + +/* Using UART */ +#define RT_USING_UART + +/* SECTION: Console options */ +/* use console for rt_kprintf */ +#define RT_USING_CONSOLE +/* the buffer size of console */ +#define RT_CONSOLEBUF_SIZE 80 + +/* SECTION: finsh, a C-Express shell */ +/* Using FinSH as Shell*/ +#define RT_USING_FINSH +/* Using symbol table */ +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION + +#endif diff --git a/bsp/nuc140/startup.c b/bsp/nuc140/startup.c new file mode 100644 index 0000000000000000000000000000000000000000..e949e1e1b45a6585d1bf9835cd6a0c27f9c5804d --- /dev/null +++ b/bsp/nuc140/startup.c @@ -0,0 +1,111 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-01-25 Bernard first version + */ + +#include +#include + +#include "board.h" +#ifdef RT_USING_FINSH +#include "finsh.h" +extern void finsh_system_init(void); +#endif + +/** + * @addtogroup NUC100 + */ + +/*@{*/ +#if defined(__CC_ARM) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#elif defined(__GNUC__) +extern unsigned char __bss_start; +extern unsigned char __bss_end; +#endif + +extern int rt_application_init(void); + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* init kernel object */ + rt_system_object_init(); + + /* init board */ + rt_hw_board_init(); + rt_show_version(); + + /* init tick */ + rt_system_tick_init(); + + /* init timer system */ + rt_system_timer_init(); + +#ifdef RT_USING_HEAP +#ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x20004000); +#elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)0x20004000); +#else + rt_system_heap_init((void*)&__bss_end, (void*)0x20004000); +#endif +#endif + + /* init scheduler system */ + rt_system_scheduler_init(); + +#ifdef RT_USING_HOOK /* if the hook is used */ + /* set idle thread hook */ + rt_thread_idle_sethook(rt_hw_led_flash); +#endif + +#ifdef RT_USING_DEVICE + /* init all device */ + rt_device_init_all(); +#endif + + /* init application */ + rt_application_init(); + +#ifdef RT_USING_FINSH + /* init finsh */ + finsh_system_init(); + finsh_set_device("uart1"); +#endif + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main (void) +{ + rt_uint32_t UNUSED level; + + /* disable interrupt first */ + level = rt_hw_interrupt_disable(); + + /* invoke rtthread_startup */ + rtthread_startup(); + + return 0; +} + +/*@}*/ diff --git a/bsp/nuc140/uart.c b/bsp/nuc140/uart.c new file mode 100644 index 0000000000000000000000000000000000000000..6b21e00608bb635580e9c6c9fd585661dbd866fc --- /dev/null +++ b/bsp/nuc140/uart.c @@ -0,0 +1,226 @@ +#include +#include +#include "CMSIS/CM0/NUC1xx.h" + +/** + * @addtogroup NUC1xx + */ + +/*@{*/ +#if defined(RT_USING_UART) && defined(RT_USING_DEVICE) + +#define UART_BAUDRATE 115200 +struct rt_uart_nuc +{ + struct rt_device parent; + + /* buffer for reception */ + rt_uint8_t read_index, save_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; +}uart_device; + +void UART0_IRQHandler(void) +{ + rt_ubase_t level; + struct rt_uart_nuc* uart = &uart_device; + + if (UART0->ISR.RDA_INT == 1) /* Receive Data Available */ + { + while (UART0->ISR.RDA_IF == 1) + { + /* Receive Data Available */ + uart->rx_buffer[uart->save_index] = UART0->DATA; + + level = rt_hw_interrupt_disable(); + uart->save_index ++; + if (uart->save_index >= RT_UART_RX_BUFFER_SIZE) + uart->save_index = 0; + rt_hw_interrupt_enable(level); + } + + /* invoke callback */ + if(uart->parent.rx_indicate != RT_NULL) + { + rt_size_t length; + if (uart->read_index > uart->save_index) + length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index; + else + length = uart->save_index - uart->read_index; + + uart->parent.rx_indicate(&uart->parent, length); + } + } + + return; +} + +static rt_err_t rt_uart_init (rt_device_t dev) +{ + /* Multi-Function Pin: Enable UART0:Tx Rx */ + SYS->GPBMFP.UART0_RX = 1; + SYS->GPBMFP.UART0_TX = 1; + + /* Configure GCR to reset UART0 */ + SYS->IPRSTC2.UART0_RST = 1; + SYS->IPRSTC2.UART0_RST = 0; + + /* Enable UART clock */ + SYSCLK->APBCLK.UART0_EN = 1; + + /* Select UART clock source */ + SYSCLK->CLKSEL1.UART_S = 0; + + /* Data format */ + UART0->LCR.WLS = 3; + + /* Configure the baud rate */ + *((__IO uint32_t *)&UART0->BAUD) = 0x3F000066; /* This setting is for 115200bsp with 12Mhz clock source */ + + return RT_EOK; +} + +static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag) +{ + RT_ASSERT(dev != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* open receive data available interrupt */ + UART0->IER.RDA_IEN = 1; + + /* Enable the UART Interrupt */ + NVIC_EnableIRQ(UART0_IRQn); + } + + return RT_EOK; +} + +static rt_err_t rt_uart_close(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Disable the UART Interrupt */ + NVIC_DisableIRQ(UART0_IRQn); + } + + return RT_EOK; +} + +static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + struct rt_uart_nuc *uart = (struct rt_uart_nuc*)dev; + RT_ASSERT(uart != RT_NULL); + + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (uart->read_index != uart->save_index) + { + *ptr = uart->rx_buffer[uart->read_index]; + + uart->read_index ++; + if (uart->read_index >= RT_UART_RX_BUFFER_SIZE) + uart->read_index = 0; + } + else + { + /* no data in rx buffer */ + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + + ptr ++; + size --; + } + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + + return 0; +} + +static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + char *ptr; + ptr = (char*)buffer; + + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + /* check whether UART is empty */ + while (UART0->FSR.TX_EMPTY !=1); + /* write data */ + UART0->DATA = '\r'; + } + + /* check whether UART is empty */ + while (UART0->FSR.TX_EMPTY !=1); + /* write data */ + UART0->DATA = *ptr; + + ptr ++; + size --; + } + } + else + { + while ( size != 0 ) + { + /* check whether UART is empty */ + while (UART0->FSR.TX_EMPTY !=1); + /* write data */ + UART0->DATA = *ptr; + + ptr++; + size--; + } + } + + return (rt_size_t) ptr - (rt_size_t) buffer; +} + +void rt_hw_uart_init(void) +{ + struct rt_uart_nuc* uart; + + /* get uart device */ + uart = &uart_device; + + /* device initialization */ + uart->parent.type = RT_Device_Class_Char; + rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer)); + uart->read_index = uart->save_index = 0; + + /* device interface */ + uart->parent.init = rt_uart_init; + uart->parent.open = rt_uart_open; + uart->parent.close = rt_uart_close; + uart->parent.read = rt_uart_read; + uart->parent.write = rt_uart_write; + uart->parent.control = RT_NULL; + uart->parent.private = RT_NULL; + + rt_device_register(&uart->parent, + "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX); +} +#endif /* end of UART */ + +/*@}*/ diff --git a/bsp/nuc140/uart.h b/bsp/nuc140/uart.h new file mode 100644 index 0000000000000000000000000000000000000000..7b4663aa3d92aff506e26c3ef69b9657f994ae04 --- /dev/null +++ b/bsp/nuc140/uart.h @@ -0,0 +1,6 @@ +#ifndef __UART_H__ +#define __UART_H__ + +void rt_hw_uart_init(void); + +#endif diff --git a/libcpu/arm/nuc1xx/context_rvds.S b/libcpu/arm/nuc1xx/context_rvds.S new file mode 100644 index 0000000000000000000000000000000000000000..a2771d09454e14bbe62494031b13e1f729b504ca --- /dev/null +++ b/libcpu/arm/nuc1xx/context_rvds.S @@ -0,0 +1,175 @@ +;/* +; * File : context_rvds.S +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2009, RT-Thread Development Team +; * +; * The license and distribution terms for this file may be +; * found in the file LICENSE in this distribution or at +; * http://www.rt-thread.org/license/LICENSE +; * +; * Change Logs: +; * Date Author Notes +; * 2010-01-25 Bernard first version +; */ + +;/** +; * @addtogroup NUC100 +; */ +;/*@{*/ + +NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register +NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) +NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception + + AREA |.text|, CODE, READONLY, ALIGN=2 + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_thread_switch_interrput_flag + IMPORT rt_interrupt_from_thread + IMPORT rt_interrupt_to_thread + +;/* +; * rt_base_t rt_hw_interrupt_disable(); +; */ +rt_hw_interrupt_disable PROC + EXPORT rt_hw_interrupt_disable + MRS r0, PRIMASK + CPSID I + BX LR + ENDP + +;/* +; * void rt_hw_interrupt_enable(rt_base_t level); +; */ +rt_hw_interrupt_enable PROC + EXPORT rt_hw_interrupt_enable + MSR PRIMASK, r0 + BX LR + ENDP + +;/* +; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); +; * r0 --> from +; * r1 --> to +; */ +rt_hw_context_switch_interrupt + EXPORT rt_hw_context_switch_interrupt +rt_hw_context_switch PROC + EXPORT rt_hw_context_switch + + ; set rt_thread_switch_interrput_flag to 1 + LDR r2, =rt_thread_switch_interrput_flag + LDR r3, [r2] + CMP r3, #1 + BEQ _reswitch + MOVS r3, #0x1 + STR r3, [r2] + + LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread + STR r0, [r2] + +_reswitch + LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread + STR r1, [r2] + + LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + BX LR + ENDP + +; r0 --> swith from thread stack +; r1 --> swith to thread stack +; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack +rt_hw_pend_sv PROC + EXPORT rt_hw_pend_sv + + ; disable interrupt to protect context switch + MRS r2, PRIMASK + CPSID I + + ; get rt_thread_switch_interrupt_flag + LDR r0, =rt_thread_switch_interrput_flag + LDR r1, [r0] + CMP r1, #0x00 + BEQ pendsv_exit ; pendsv already handled + + ; clear rt_thread_switch_interrput_flag to 0 + MOVS r1, #0x00 + STR r1, [r0] + + LDR r0, =rt_interrupt_from_thread + LDR r1, [r0] + CMP r1, #0x00 + BEQ swtich_to_thread ; skip register save at the first time + + MRS r1, psp ; get from thread stack pointer + SUBS r1, r1, #0x10 + LDR r0, [r0] + STR r1, [r0] ; update from thread stack pointer + STMIA r1!, {r4 - r7} ; push r4 - r7 register + +swtich_to_thread + LDR r1, =rt_interrupt_to_thread + LDR r1, [r1] + LDR r1, [r1] ; load thread stack pointer + + LDMIA r1!, {r4 - r7} ; pop r4 - r7 register + MSR psp, r1 ; update stack pointer + +pendsv_exit + ; restore interrupt + MSR PRIMASK, r2 + + MOVS r0, #0x04 + RSBS r0, #0 + BX r0 + ENDP + +;/* +; * void rt_hw_context_switch_to(rt_uint32 to); +; * r0 --> to +; * this fucntion is used to perform the first thread switch +; */ +rt_hw_context_switch_to PROC + EXPORT rt_hw_context_switch_to + ; set to thread + LDR r1, =rt_interrupt_to_thread + STR r0, [r1] + + ; set from thread to 0 + LDR r1, =rt_interrupt_from_thread + MOVS r0, #0x0 + STR r0, [r1] + + ; set interrupt flag to 1 + LDR r1, =rt_thread_switch_interrput_flag + MOVS r0, #1 + STR r0, [r1] + + ; set the PendSV exception priority + ; LDR r0, =NVIC_SYSPRI2 + ; LDR r1, =NVIC_PENDSV_PRI + ; STR r1, [r0] + + ; trigger the PendSV exception (causes context switch) + LDR r0, =NVIC_INT_CTRL + LDR r1, =NVIC_PENDSVSET + STR r1, [r0] + + ; enable interrupts at processor level + CPSIE I + + ; never reach here! + ENDP + +; compatible with old version +rt_hw_interrupt_thread_switch PROC + EXPORT rt_hw_interrupt_thread_switch + BX lr + ENDP + + END diff --git a/libcpu/arm/nuc1xx/fault.c b/libcpu/arm/nuc1xx/fault.c new file mode 100644 index 0000000000000000000000000000000000000000..5b8dc6b62f29d637f36556ee841f3ca36307856c --- /dev/null +++ b/libcpu/arm/nuc1xx/fault.c @@ -0,0 +1,47 @@ +/* + * File : fault.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-01-25 Bernard first version + */ +#include + +struct stack_contex +{ + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r12; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t psr; +}; + +extern void rt_hw_interrupt_thread_switch(void); +extern void list_thread(void); +extern rt_thread_t rt_current_thread; +void rt_hw_hard_fault_exception(struct stack_contex* contex) +{ + rt_kprintf("psr: 0x%08x\n", contex->psr); + rt_kprintf(" pc: 0x%08x\n", contex->pc); + rt_kprintf(" lr: 0x%08x\n", contex->lr); + rt_kprintf("r12: 0x%08x\n", contex->r12); + rt_kprintf("r03: 0x%08x\n", contex->r3); + rt_kprintf("r02: 0x%08x\n", contex->r2); + rt_kprintf("r01: 0x%08x\n", contex->r1); + rt_kprintf("r00: 0x%08x\n", contex->r0); + + rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name); +#ifdef RT_USING_FINSH + list_thread(); +#endif + while (1); +} diff --git a/libcpu/arm/nuc1xx/fault_rvds.S b/libcpu/arm/nuc1xx/fault_rvds.S new file mode 100644 index 0000000000000000000000000000000000000000..4029306400cd1179c7f2fda9b310a20307def733 --- /dev/null +++ b/libcpu/arm/nuc1xx/fault_rvds.S @@ -0,0 +1,32 @@ +;/* +; * File : fault_rvds.S +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2006, RT-Thread Development Team +; * +; * The license and distribution terms for this file may be +; * found in the file LICENSE in this distribution or at +; * http://www.rt-thread.org/license/LICENSE +; * +; * Change Logs: +; * Date Author Notes +; * 2010-01-25 Bernard first version +; */ + + AREA |.text|, CODE, READONLY, ALIGN=2 + THUMB + REQUIRE8 + PRESERVE8 + + IMPORT rt_hw_hard_fault_exception + +rt_hw_hard_fault PROC + EXPORT rt_hw_hard_fault + + ; get current context + MRS r0, psp ; get fault thread stack pointer + PUSH {lr} + BL rt_hw_hard_fault_exception + POP {pc} + ENDP + + END diff --git a/libcpu/arm/nuc1xx/interrupt.c b/libcpu/arm/nuc1xx/interrupt.c new file mode 100644 index 0000000000000000000000000000000000000000..a1a3eb24416085c734f0bcfebfda978696bf12ee --- /dev/null +++ b/libcpu/arm/nuc1xx/interrupt.c @@ -0,0 +1,21 @@ +/* + * File : interrupt.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-01-25 Bernard first version + */ + +#include + +/* exception and interrupt handler table */ +rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +rt_uint8_t rt_thread_switch_interrput_flag; + +/*@}*/ diff --git a/libcpu/arm/nuc1xx/stack.c b/libcpu/arm/nuc1xx/stack.c new file mode 100644 index 0000000000000000000000000000000000000000..5329244c674ba305b3dbe0ead87e427488fc0529 --- /dev/null +++ b/libcpu/arm/nuc1xx/stack.c @@ -0,0 +1,54 @@ +/* + * File : stack.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2010-01-25 Bernard first version + */ +#include + +/** + * @addtogroup NUC100 + */ +/*@{*/ + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + unsigned long *stk; + + stk = (unsigned long *)stack_addr; + *(stk) = 0x01000000L; /* PSR */ + *(--stk) = (unsigned long)tentry; /* entry point, pc */ + *(--stk) = (unsigned long)texit; /* lr */ + *(--stk) = 0; /* r12 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r1 */ + *(--stk) = (unsigned long)parameter; /* r0 : argument */ + *(--stk) = 0; /* r7 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r4 */ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} + +/*@}*/ diff --git a/libcpu/arm/nuc1xx/start_rvds.S b/libcpu/arm/nuc1xx/start_rvds.S new file mode 100644 index 0000000000000000000000000000000000000000..c0058b6e8a8db69e31dfe61f65e7eb4dad4e2b57 --- /dev/null +++ b/libcpu/arm/nuc1xx/start_rvds.S @@ -0,0 +1,349 @@ +;/*---------------------------------------------------------------------------------------------------------*/ +;/* */ +;/* Copyright(c) 2009 Nuvoton Technology Corp. All rights reserved. */ +;/* */ +;/*---------------------------------------------------------------------------------------------------------*/ + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +CLK_BA_base EQU 0x50000200 +PWRCON EQU 0x00 +AHBCLK EQU 0x04 +APBCLK EQU 0x08 +CLKSEL0 EQU 0x10 +CLKSEL1 EQU 0x14 +CLKDIV EQU 0x18 +PLLCON EQU 0x20 +TEST_S EQU 0x30 + +CLK_BA_APBCLK EQU 0x50000208 + +;// Define clock enable registers + +ADC_COMP_CLK EQU 0x50000208 +ADC_enable EQU 0x10000000 +COMP_enable EQU 0x40000000 + +PDMA_CLK EQU 0x50000204 +PDMA_enable EQU 0x00000003 + +;; bit 0 CPU_EN +;; bit 1 PDMA_EN + +;// Define COMP registers base +COMP_base EQU 0x400D0000 +CMP1CR EQU 0x00 +CMP2CR EQU 0x04 +CMPSR EQU 0x08 + +;// Define ADC registers base +ADC_base EQU 0x400E0000 +ADDR0 EQU 0x00 +ADDR1 EQU 0x04 +ADDR2 EQU 0x08 +ADDR3 EQU 0x0c +ADDR4 EQU 0x10 +ADDR5 EQU 0x14 +ADDR6 EQU 0x18 +ADDR7 EQU 0x1c +ADCR EQU 0x20 +ADCHER EQU 0x24 +ADCMPR0 EQU 0x28 +ADCMPR1 EQU 0x2c +ADSR EQU 0x30 +ADCALR EQU 0x34 +ADCFCR EQU 0x38 +ADCALD EQU 0x3c + +;// Pattern Table +pattern_55555555 EQU 0x55555555 +pattern_aaaaaaaa EQU 0xaaaaaaaa +pattern_00005555 EQU 0x00005555 +pattern_0000aaaa EQU 0x0000aaaa +pattern_05550515 EQU 0x05550515 +pattern_0aaa0a2a EQU 0x0aaa0a2a + +;// Define PDMA regsiter base +PDMA_BA_ch0_base EQU 0x50008000 +PDMA_BA_ch1_base EQU 0x50008100 +PDMA_BA_ch2_base EQU 0x50008200 +PDMA_BA_ch3_base EQU 0x50008300 +PDMA_BA_ch4_base EQU 0x50008400 +PDMA_BA_ch5_base EQU 0x50008500 +PDMA_BA_ch6_base EQU 0x50008600 +PDMA_BA_ch7_base EQU 0x50008700 + +PDMA_BA_GCR EQU 0x50008F00 +PDMA_BA_GCR_base EQU 0x50008F00 + +PDMA_GCRCSR EQU 0X00 +PDMA_PDSSR2 EQU 0X04 +PDMA_PDSSR1 EQU 0X08 ;; PDMA channel select 0x77000000 +PDMA_GCRISR EQU 0X0C + +PDMA_GLOBAL_enable EQU 0x0000FF00 + +PDMA_CSR EQU 0X00 +PDMA_SAR EQU 0X04 +PDMA_DAR EQU 0X08 +PDMA_BCR EQU 0X0C +PDMA_CSAR EQU 0X14 +PDMA_CDAR EQU 0X18 +PDMA_CBSR EQU 0X1C +PDMA_IER EQU 0X20 +PDMA_ISR EQU 0X24 +PDMA_CTCSR EQU 0X28 +PDMA_SASOCR EQU 0X2C +PDMA_DASOCR EQU 0X30 +PDMA_SBUF0 EQU 0X80 +PDMA_SBUF1 EQU 0X84 +PDMA_SBUF2 EQU 0X88 +PDMA_SBUF3 EQU 0X8C + +;// Define VIC control register +VIC_base EQU 0xFFFF0000 +VIC_SCR15 EQU 0x003c +VIC_SVR15 EQU 0x00bc +VIC_SCR16 EQU 0x0040 +VIC_SVR16 EQU 0x00c0 +VIC_SCR30 EQU 0x0078 +VIC_SVR30 EQU 0x00f8 +VIC_MECR EQU 0x0318 +VIC_MDCR EQU 0x031c +VIC_EOSCR EQU 0x0130 + +;//================================== +INT_BA_base EQU 0x50000300 + +;// Parameter table +ADC_PDMA_CFG EQU 0x00002980 +ADC_PDMA_DST EQU 0xC0000000 +ADC_PDMA_SRC EQU 0xE0024200 +ADC_PDMA_TCBL EQU 0x00030008 + +;//================================== + +GPIO_base EQU 0x50004000 +GPIOB_PMD EQU 0x0040 +GPIOB_OFFD EQU 0x0044 +GPIOB_DOUT EQU 0x0048 +GPIOB_DMASK EQU 0x004C +GPIOB_PIN EQU 0x0050 +GPIOB_DBEN EQU 0x0054 +GPIOB_IMD EQU 0x0058 +GPIOB_IEN EQU 0x005C +GPIOB_ISRC EQU 0x0060 + +;//================================== + + +GCR_base EQU 0x50000000 +GPB_MFP EQU 0x0034 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + IMPORT rt_hw_hard_fault + IMPORT rt_hw_pend_sv + IMPORT rt_hw_timer_handler + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD rt_hw_hard_fault ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD rt_hw_pend_sv ; PendSV Handler + DCD rt_hw_timer_handler ; SysTick Handler + + ; External Interrupts + ; maximum of 32 External Interrupts are possible + DCD BOD_IRQHandler + DCD WDT_IRQHandler + DCD EINT0_IRQHandler + DCD EINT1_IRQHandler + DCD GPAB_IRQHandler + DCD GPCDE_IRQHandler + DCD PWMA_IRQHandler + DCD PWMB_IRQHandler + DCD TMR0_IRQHandler + DCD TMR1_IRQHandler + DCD TMR2_IRQHandler + DCD TMR3_IRQHandler + DCD UART0_IRQHandler + DCD UART1_IRQHandler + DCD SPI0_IRQHandler + DCD SPI1_IRQHandler + DCD SPI2_IRQHandler + DCD SPI3_IRQHandler + DCD I2C0_IRQHandler + DCD I2C1_IRQHandler + DCD CAN0_IRQHandler + DCD CAN1_IRQHandler + DCD Default_Handler + DCD USBD_IRQHandler + DCD PS2_IRQHandler + DCD ACMP_IRQHandler + DCD PDMA_IRQHandler + DCD Default_Handler + DCD PWRWU_IRQHandler + DCD ADC_IRQHandler + DCD Default_Handler + DCD RTC_IRQHandler + + + + + + + + AREA |.text|, CODE, READONLY + + + +; Reset Handler + + ENTRY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT BOD_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT EINT0_IRQHandler [WEAK] + EXPORT EINT1_IRQHandler [WEAK] + EXPORT GPAB_IRQHandler [WEAK] + EXPORT GPCDE_IRQHandler [WEAK] + EXPORT PWMA_IRQHandler [WEAK] + EXPORT PWMB_IRQHandler [WEAK] + EXPORT TMR0_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT CAN1_IRQHandler [WEAK] + EXPORT USBD_IRQHandler [WEAK] + EXPORT PS2_IRQHandler [WEAK] + EXPORT ACMP_IRQHandler [WEAK] + EXPORT PDMA_IRQHandler [WEAK] + EXPORT PWRWU_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + +BOD_IRQHandler +WDT_IRQHandler +EINT0_IRQHandler +EINT1_IRQHandler +GPAB_IRQHandler +GPCDE_IRQHandler +PWMA_IRQHandler +PWMB_IRQHandler +TMR0_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +SPI3_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +CAN0_IRQHandler +CAN1_IRQHandler +USBD_IRQHandler +PS2_IRQHandler +ACMP_IRQHandler +PDMA_IRQHandler +PWRWU_IRQHandler +ADC_IRQHandler +RTC_IRQHandler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, = (Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END